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Juliano Mologni, Lead Product Manager
ANSYS

Melika Roshandell & Sherry Hess
Cadence

Richard Barnett, CMO
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Editorial

EDACafe Editorial
by Roberto Frazzoli
TSMC to get CHIPS Act funding; Google’s Arm-based CPU; evolutionary algorithms in AI; Huawei’s growing importance

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Latest Blog Posts

EDACafe Editorial
by Sanjay Gangal
Navigating the Future: CadenceLive Reveals a Transformative Vision in Semiconductor and System Design

Bridging the Frontier
by Bob Smith, Executive Director
Great Lineup of Speakers Highlights CEO Executive Outlook May 9 at Keysight

EDACafe Editorial
by Sanjay Gangal
Homegrown AI Tools at Intel Shorten Design Cycles from Weeks to Hours

Industry Predictions
by Sanjay Gangal
Intel Sets New Paradigms in Enterprise AI with Launch of Gaudi 3 at Intel Vision 2024

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Jobs

Senior SOC Design Engineer for Nvidia at Santa Clara, California

Electrical Engineer - ASIC/FPGA for General Dynamics Mission Systems at Florham Park, New Jersey

FPGA Design Verification Engineer for General Dynamics Mission Systems at Dedham, Massachusetts

Advanced Mechanical Engineer for General Dynamics Mission Systems at Marion, Virginia

Senior CAD Engineer for Nvidia at Santa Clara, California

ASIC Verification Engineer, GPU - New College Grad 2024 for Nvidia at Santa Clara, California

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Upcoming Events

North America Technology Symposium at Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA - Apr 24, 2024

IP-SOC Silicon Valley 24 at Hyatt Regency Santa Clara 5101 Great America Parkway, Santa Clara CA - Apr 25, 2024

MEMS & Sensors Technical Congress - MSTC 2024 at University of California, Los Angeles 405 Hilgard Avenue, Covel Commons in Sunset Village, Housing at Luskin Center Los Angeles CA - May 1 - 2, 2024

ChipEx2024 at Tel-Aviv Expo Center & Hilton Hotel Tel-aviv Israel - May 7 - 8, 2024

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