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kbg
(Stranger )
12/05/10 09:04 PM
Verilog Program Report this article as Inappropriate to us !!!Login to Reply

Hello all,
I have no clue about Verilog and I want to understand a bit of program that might be useful to me. Would you happen to know what this means? I am trying to convert that into VHDL. I guess module is entity, wire is signal and the ports are inputs and outputs but what does the rest of the program mean? How do I convert this to VHDL?


`define rom_size 6'd8

module CLOCK_500 (
CLOCK,
CLOCK_500,
DATA,
END,
RESET,
GO,
CLOCK_2
);
input CLOCK;
input END;
input RESET;
output CLOCK_500;
output [23:0]DATA;
output GO;
output CLOCK_2;


reg [10:0]COUNTER_500;

wire CLOCK_500=COUNTER_500[9];
wire CLOCK_2=COUNTER_500[1];

reg [15:0]ROM[`rom_size:0];
reg [15:0]DATA_A;
reg [5:0]address;
wire [23:0]DATA={8'h34,DATA_A};

wire GO =((address <= `rom_size) && (END==1))? COUNTER_500[10]:1;
always @(negedge RESET or posedge END) begin
if (!RESET) address=0;
else 
if (address <= `rom_size) address=address+1;
end

reg [7:0]vol;

always @(posedge RESET) begin
vol=vol-1;end


always @(posedge END) begin
// ROM[0]= 16'h1e00;
ROM[0]= 16'h0c00; //power down
ROM[1]= 16'h0ec2; //master
ROM[2]= 16'h0838; //sound select

ROM[3]= 16'h1000; //mclk

ROM[4]= 16'h0017; //
ROM[5]= 16'h0217; //
ROM[6]= {8'h04,1'b0,vol[6:0]}; //
ROM[7]= {8'h06,1'b0,vol[6:0]}; //sound vol

//ROM[4]= 16'h1e00; //reset
ROM[`rom_size]= 16'h1201;//active
DATA_A=ROM[address];
end

always @(posedge CLOCK ) begin
COUNTER_500=COUNTER_500+1;
end

endmodule





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