I am a test engineer analysing VCD file formats. Please help me to clear my doubt.
When we want to generate a VCD file we will call the system tasks
"$dumpall, $dumpon, $dumpoff, $dumpvars" etc., inside a verilog code.
But these tasks are again used in the generated VCD file like :
"$dumpall 1*@ x*# 0*$ bx (k $end". I do not know what is the
reason to use "$dumpall, $dumpon, $dumpoff, $dumpvars" kind of
commands in the generated VCD file. Simply stating what is the need
for Simulation keywords inside a generated VCD file. (Are they used to
cross verify the dumped waveforms).
Thank you in advance.