EDAToolsCafe
   >> Verilog Discussion Board
Thread views: 6459 View all threadsNext thread*

rameshwaranm
(Stranger )
09/22/08 02:33 AM
Doubt in VCD format Report this article as Inappropriate to us !!!Login to Reply

Hi All,

I am a test engineer analysing VCD file formats.  Please help me to clear my doubt.
When we want to generate a VCD file we will call the system tasks
"$dumpall, $dumpon, $dumpoff, $dumpvars" etc., inside a verilog code.
But these tasks are again used in the generated VCD file like :
"$dumpall 1*@  x*#  0*$  bx (k $end".  I do not know what is the
reason to use "$dumpall, $dumpon, $dumpoff, $dumpvars" kind of
commands in the generated VCD file. Simply stating what is the need
for Simulation keywords inside a generated VCD file. (Are they used to
cross verify the dumped waveforms).
Thank you in advance.

Regards,
Rameshwaran






Entire thread
SubjectPosted byPosted on
*Doubt in VCD format rameshwaranm   09/22/08 02:33 AM
.*Re: Doubt in VCD format pini   11/20/08 06:26 AM
Jump to

 

CST Webinar Series



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy