you are right, I30<7:0> is a named array of instances. If e.g. I30 is an inverter then the array would consist of a bank of 8 inverters with an 8-bit input and output bus. This is a very convenient feature of the Cadence Schematic editor and I frequently use it since it saves hours of click and type. Shame on Xilinx for not supporting it. Looks like you have to break up the arrays and instantiate 8 individual components.
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