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pini
(Stranger )
05/10/08 12:42 PM
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The methodology for normal digital design is well known. Specification, block diagram of the data path, timing of the control, RTL coding, simulation, synthesis, post synthesis and post layout simulation and static timing analysis.

While this is right way of doing things, when it comes to complex digital ASIC designs, there are small number of cases where this methodology is not required.

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