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(Stranger )
02/23/07 12:06 AM
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1.can anyone give me the whole flow of pks_shell cadence tool .I am writing a vhdl file and I can go upto the" build generic" and optimize(giving error: floorplan area not specified)and write it into a verilog netlist file.if i give this verilog netlist file as input to the encounter ,it is giving error in the verilog file.

2.Does encounter tool takes input of netlist in verilog format only or a vhdl netlist can be given to it .....?

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