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08/08/06 01:36 PM
Re: VHDL to Verilog [re: nstollon]Report this article as Inappropriate to us !!!Login to Reply

Aldec claims to have a good VHDL to Verilog conversion tool. You can get an evaluation version of the tool from:
and select "Active-HDL".

This tool also have some decent documentation capabilities and a very good simulator.

Before going this route (or any other), what is the actual NEED to do the translation? Most simulation and synthesis tools will handle both languages.

If the issue is becoming familiar with VHDL, both Technically Speaking and Xilinx offers an excellent instructor led VHDL classes all over the country.

There are some decent on-line trainings and tutorials as well.

Entire thread
SubjectPosted byPosted on
*VHDL to Verilog nstollon   06/12/06 10:19 AM
.*Re: VHDL to Verilog einfochipsEIC   09/19/16 04:01 AM
.*Re: VHDL to Verilog IDS   11/07/07 07:40 AM
.*Re: VHDL to Verilog chetan   09/28/16 09:33 AM
.*Re: VHDL to Verilog dannote   10/03/07 10:23 PM
.*Re: VHDL to Verilog wkafig   08/08/06 01:36 PM
.*Re: VHDL to Verilog mayankmehta_83   09/27/07 02:53 AM
.*Re: VHDL to Verilog dave_59   08/04/06 04:21 AM
.*Re: VHDL to Verilog sandor   06/21/06 06:53 AM
.*VHDL to Verilog rashu   02/11/08 09:53 PM
.*Re: VHDL to Verilog 5nc   06/21/06 02:08 AM
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