Aldec claims to have a good VHDL to Verilog conversion tool. You can get an evaluation version of the tool from:
and select "Active-HDL".
This tool also have some decent documentation capabilities and a very good simulator.
Before going this route (or any other), what is the actual NEED to do the translation? Most simulation and synthesis tools will handle both languages.
If the issue is becoming familiar with VHDL, both Technically Speaking and Xilinx offers an excellent instructor led VHDL classes all over the country.
There are some decent on-line trainings and tutorials as well.