Based on your posting, you clearly understand the inner workings of SPICE simulators. You named many of the key areas that we’ve optimized in Analog FastSPICE. While our founders were convinced they could write a much better SPICE and RF simulator, they did not know how much performance or capacity improvement was possible while maintaining true SPICE accuracy and remaining plug compatible. The only way to find out was to invest a substantial number of development years with great attention to detail and a willingness to tackle the toughest circuits. The results speak for themselves.
If you haven’t already done so, I encourage you to review the dozens and dozens of examples on our website (www.berkeley-da.com) and in our white papers. They are all production circuits on which the designers validated that our results are identical to their “golden” SPICE simulator results down to the SPICE noise floor. Analog FastSPICE (AFS) consistently delivers at least 5x (for circuits with >1K elements and >1-hour runtimes). There are also many examples where AFS converged on extremely large circuits that traditional SPICE simulators would never converge. Our internal record is >4M total elements, and we’ve converged on several circuits with >1M transistors. (The designers in these cases were stunned.) Also check out the long list of companies who have issued press releases with us publicly stating that we deliver these results.
All that said, seeing is believing. If you have some big analog/RF verification problems, we’d love to have you confirm our results firsthand.
Berkeley Design Automation