Parallel can mean any of the three technologies that you mentioned.
For FineSim PRO parallel is distributed, parallel processing. FineSim is aimed at analog-centric, small netlists. FineSim PRO is aimed at digital-centric, large netlists. Plus, you can use the two together. Still, the capacity is limited to 100 million devices, which is below what HSIM offers by exploiting hierarchy.
I'll find out more details about AuSim. They talked about it at DAC but haven't got anything posted on their web site yet. Their application is extracted netlists with millions of elements.
As a user I want to use multiple CPUs in parallel during model evaluation to cut down long run times to fit into my work day. Most PCs and workstations are now using multi-core, so I want to keep each core fully utilized on my SPICE runs too.
Mentor's focus is transistor-level mixed with AMS languages.
Another promise of distributed, parallel processing for SPICE and Fast SPICE is to increase the capacity of my netlist.
Xoomsys will offer distributed SPICE processing to tackle the capacity and speed bottlenecks. They are aiming at highly-coupled designs that require SPICE accuracy.
I didn't yet mention Berkeley DA, however there's a thread started in this forum where they have defined a new class of simulators called Analog Fast SPICE which emphasizes difficult circuits like PLL and ADCs without compromising accuracy and with minimal simulator options. Their simulator is a flat tool with limited capacity yet with significant success stories from Japanese consumer companies.
Silvaco's SmartSpice has had a multi-CPU capability for over a decade now and SmartSpice XL has shown speed-ups using multi-threaded parallel 4 CPU machines from Sun. This is another flat simulator aimed at the high accuracy market with a lower price-point than other SPICE providers.
From Russia comes another Analog FastSPICE tool called AVOSpice that sounds like it competes with Berkeley DA and has a capacity of 1million MOS devices on a workstation with 4GB of RAM. Their simulator exploits multi-core to typically speed up by 3X when using 4 cores.
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