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(Stranger )
02/13/07 12:46 PM
2 ASIC design vacancies at San Jose Report this article as Inappropriate to us !!!Login to Reply

2 ASIC design positions at San Jose

Contact person: Sophia@synapse-da.com

Position: Modem RTL

Job Description:

Implement portions of the UWB modem design in Verilog. Complete Microarchitecture of block level designs from system and algorithm specifications. Follow coding guidelines and insure design meets system level requirements. Bring up and debug block level designs in the block level verification environment. Provide physical design team with timing constraints and make design changes as necessary to fix bugs found in verification and emulation or timing and synthesis issues found in physical design. Participate in debug of the datapath in emulation and post-silicon.

Required Experience:

· At least 5 years of experience implementing signal processing algorithms in hardware
· Expert level of proficiency with Verilog
· Experience running verilog simulation
· Experience viewing timing and synthesis reports resolving synthesis and static timing issues in RTL
· Experience bringing up modem designs in emulation or silicon
· Experience using MATLAB to analyze signal processing algorithms


Position: Top Level Design

Job Description:

Integrate design modules in the top level design including physical layer macros, I/O cells, DFT structures, test controllers, 3rd party IP, and subchips. Understand the integration requirements for each module integrated and insure that system level design requirements are satisfied in the top level design. Implement logic design of the pad ring, test control, clock and reset generation, and functional pin muxing. Support verification of the top level design including functional pin muxing, automated test modes for functional testing and DFT, power-on reset sequences, and creation of the top level test bench. Assist with generation of test cases and automation of test vector generation using gate level simulations. Participate in running the DFT tool flow for automated test vector generation scan, transition fault, I/O timing characterization, memory BIST, IDDQ, boundary scan, burn-in.

Required Experience:

· At least 8 years of experience in ASIC design with responsibility for top level design and / or DFT for 1 design of at least 1M gates.
· Experience running automated DFT tools such as TestKompress, TetraMax, MBIST, etc.
· Experience implementing functional pin muxing and JTAG boundary scan
· Experience with PCI Express and USB 2.0
· Expert level of proficiency with Verilog and Perl




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