I saw ur message on the discussion board. I'm postin u my resume. Kindly check it out.
2-1-487 , Suryanilayam,
Phone: +91 40 27635336
To work in an environment where every assignment is a challenge which will give me an opportunity to learn and improve.
B. Tech – Electronics and Communication Engineering ( 76%), 2002-2006
C.M.R. College of Engineering and Technology,
Jawaharlal Nehru Technological University, Hyderabad.
Intermediate – M.P.C (85.1%), 2000-2002
Vidyaniketan Junior College,
Board of Intermediate Education, Hyderabad
S.S.C – (75%), 2000
St.Joseph’s High School,
Board of Secondary Education, Hyderabad
VLSI DESIGNING TECHNIQUES.
Implementation of SDRAM controller using VERILOGHDL. Jan 4th ’06 – Mar 4th ’06
Electronics Corporation of India Ltd., Hyderabad, A.P
The objective of the project was to provide synchronism between the speeds of the processor and the SDRAM. This SDRAM Controller is a interface between a processor and SDRAM. The advantage in using this SDRAM Controller is it is independent of the processor type and its functionality is similar to a Direct Memory Access. This design of SDRAM Controller is programmed using VerilogHDL.
Participated in the Nation level Symposium “ELECTRON-04” and performed pretty well.
Achieved 1st prize in the seminar session about VLSI.
Achieved complements by the professors of different universities when I displayed my mini project “GRIPOSCOPE”.
Hardworking, Proactive, Analytical thinking, flexibility, determination, self-driven, good communication skills, open to learning
Father’s Name Mr. P V Ratnakar.
Date of Birth 25th April,1985
Hobbies Reading , Playing tennis.
I hereby state that all the details furnished above are true to the best of my knowledge.
Date: 13th March ,2006. Surya Prayaga