EDAToolsCafe
   >> EDA User News and Reviews
Thread views: 20745 View all threadsNext thread*

Sunil Kakkar
(Unregistered)
06/24/06 08:16 AM
There are no short cuts to verification Report this article as Inappropriate to us !!!Login to Reply

The authors are very right in observing that the selection of a mere tool/language does not mean you are almost there when it comes to verifying a meaningful chip.
There are several tool independent steps which must be taken in the right direction even before a tool/language is selected :
a) Verification begins at the architecture definition stage in the form of performance modeling and designing for verification. A meticulous tool independent plan for this is a must.
b) A thorough tool independent test plan that covers all stages of design from block level RTL -> chip integration->gate level netlist->system level validation->FPGA->eval boards is a must.
c) Evolving an assertion & a coverage methodology is a must.
d) Running application code is a must.
One can then select a language, keeping all the above requirements in mind.
But even then, no matter what language/tool is selected, the final quality of the verification platform cannot be better than the skills of the verification engineers.



Entire thread
SubjectPosted byPosted on
*Verification Languages: 3 points to ponder beyond "which one?"  06/24/06 08:16 AM
.*Goal Driven Verification is the way to go...Akiva Michelson  06/29/06 08:48 AM
.*There are no short cuts to verificationSunil Kakkar  06/24/06 08:16 AM
Jump to

 

CST Webinar Series



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy