The authors are very right in observing that the selection of a mere tool/language does not mean you are almost there when it comes to verifying a meaningful chip.
There are several tool independent steps which must be taken in the right direction even before a tool/language is selected :
a) Verification begins at the architecture definition stage in the form of performance modeling and designing for verification. A meticulous tool independent plan for this is a must.
b) A thorough tool independent test plan that covers all stages of design from block level RTL -> chip integration->gate level netlist->system level validation->FPGA->eval boards is a must.
c) Evolving an assertion & a coverage methodology is a must.
d) Running application code is a must.
One can then select a language, keeping all the above requirements in mind.
But even then, no matter what language/tool is selected, the final quality of the verification platform cannot be better than the skills of the verification engineers.