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11/27/05 07:39 AM
Your ASIC design better work on silicon the first time! new Report this article as Inappropriate to us !!!Login to Reply

Your ASIC design better work on silicon the first time!

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ankur arora
11/28/05 03:30 PM
Good Article new Report this article as Inappropriate to us !!!Login to Reply

I think its a nice article on the current need of Semiconductor industry to deliver qualtiy products on time by virtue of good verification whcih is the need of the hour, and as we are moving to converging technoligies , higher end devices , Verification would be palying a major role in achieving our goal.

11/28/05 03:52 PM
vinod Report this article as Inappropriate to us !!!Login to Reply

This is really a great article emphasizing the need of a most appropriate verification process early in the design cycle to catch the bugs, which will make first pass success on silicon

11/28/05 08:42 PM
Great Article new Report this article as Inappropriate to us !!!Login to Reply

"the silicon world not being that horrible after all" ...Companies that have done respins of their ASIC designs would realize the true potential of this statement. Sunil touches on the right cord when he says that meticullous verification strategies that leave nothing to imagination must be implemented at very early design stages to prevent the silicon world from becoming ghoulish.Readin and re-reading this article can definitily instill a desire in verification engineers to verify the silicon to the highest possible level...

Akiva Michelson
12/04/05 05:06 AM
... and on time as well... new Report this article as Inappropriate to us !!!Login to Reply

Sunil, Excellent article. I would add that a first-time quality is not the only requirement; Companies who want to win in the marketplace also need to concentrate on predictable schedules. This is slowly becoming the key differentiator between companies. Ace Verification has a world-class model for building a realistic predictable schedule for verification. Feel free to read the reference material on our web-site. .

12/05/05 09:35 PM
Good article new Report this article as Inappropriate to us !!!Login to Reply

It is quite good article, but it look like quite boring. I mean the authour shold gsupply examples or give some popular tools. We not only need to know it, but also need to know how to solve this problem

12/07/05 03:31 PM
Complete verification is a must.... new Report this article as Inappropriate to us !!!Login to Reply

Sunil you are quite right in saying that complete vrification is a essential for overall product success. Probably next time you can mention about how to achieve this with minimum effort across different designs which are not very different, thus saving time and effort.

12/23/05 06:03 AM
As Complexities Rise, Silicon Verification is Needed new Report this article as Inappropriate to us !!!Login to Reply

I strongly agree that a comprehensive verification plan is required, but it should not end at the RTL verification step. You must plan during the architetcure stage to go beyond RTL simulation and emulation. You must plan to design-in debug structures for silicon. No amount of simulation will ever completely verifiy the functionality in today's complex SoC designs. Real-world, at-speed and in-system testing must be part of the first silicon verification process. The only way to achieve this is to build debug buses, observation points and reconfigurable control structures to allow for logic analysis, assertion testing and event-driven analysis. The overhead of these extra structures is easily mitigated by the enhanced bring-up of first silicon, not to mention the reduction in respins. Search the web and see where you can find "reconfigurable debug infrastructure." Thanks for the article and I hope this adds some value to others.

01/24/06 02:29 AM
success of tape out now depends on the plan of verification new Report this article as Inappropriate to us !!!Login to Reply

As Sunil (author of this article) mentioned, considering the complexity of the functionality added in today's ASIC, more than 50% of effort in a chip design goes to the functional Verification. So its obvious that verification becomes important component and clear cut plan is needed from the beginning of the project onwards to achieve the first time success. Also we need better verification plan, tools and methodology with better coverage metrics(which drives the verification) and constrain random capability(helps to automate most of the work) along with assertion based design methodology where you can use the assertions in static(formal) and dynamic simulations are needed. Reuse is another important strategy when we develop the testbench infrastucture for SoC verification to reduce the time to market. Thats the reason why we need high level verification languages(supporting OOP/AOP) like vera or e become handy for good verification. Now after the evoluation of system verilog as a unified language with testbench features and assertions may make our job more flexible if we adopt a good verification methodology and may help us to achive the first time success in shorter time.

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