>> EDA Industry
Thread views: 4637 View all threadsNext thread*Threaded Mode

(Stranger )
10/07/08 12:11 AM
Metalor PolySilicon for interconnections ?? Report this article as Inappropriate to us !!!Login to Reply

Hello all,

In our CMOS ckt. layouts we can use metal (1-6) or PolySilicon for interconnections. I normally blindly used metal for its lower resistivity and accompanied propagation delay as compared to PolySilicon. I looked for answers in books by Pucknell, Rabaey and Uyemura but did not get an answer as to which (metal or PolySilicon) to use when and why.

Can anyone please tell when to use which and why? Or if you know any source which gives this, please provide reference. 

Thanks a lot in advance.

Jump to


Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy