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evergreenT
(Stranger )
08/02/07 03:00 PM
how to prepare/setup IPs info for synthesis tool ? Report this article as Inappropriate to us !!!Login to Reply

I'd like to write Velilog code that use my own IP blocks along with standard cells. Does anybody know how to tell Synthesis tool not to go into my IP blocks and synthesize them ?

In other words, if I create my own IPs, what kind of information should I give to Synthesis tool? and How?

I'm targeting design_compiler or design_analyzer .

Thanks a lot

 

 






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