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djepayne
(Stranger )
06/12/07 04:33 PM
DAC Report: SPICE and Fast SPICE new Report this article as Inappropriate to us !!!Login to Reply

I visited some but not all SPICE and Fast SPICE suppliers at DAC in San Diego this year. Here's a quick trip report.

Magma:
FineSim (SPICE) is parallel.
FIneSim PRO (Fast SPICE) is also parallel and unique. Has a feature to abstract transistors into gate-level black box for digital logic.
Strategy - throw your entire SPICE netlist into this simulator and use up lots of CPUs.
Lacking - customer success stories. PRO is still a flat simulator. No language integration.
Contact - KT Moore

Nascentric:
AuSIM (Fast SPICE) is hierarchical and now parallel. Their booth theatre was a hoot and they attracted full audiences to collect cool rocket toys.
Strategy - simulate flat or hierarchical designs on one or multiple CPUs.
Lacking - first customer success story. Language integration.
Contact - Dino Caporossi

Mentor:
ADiT (Fast SPICE) is flat and integrated with language simulators for both digital and AMS. Maybe next year they will be parallel.
Eldo (SPICE) is mature.
Strategy - simulate analog transistors with Eldo, digital transistors with ADiT and use digital or AMS language for the rest of your SoC.
Lacking - no hierarchy, learning curve for AMS language.
Contact - Cyril Descleves

Synopsys:
HSIM (Fast SPICE) is hierarchical and the marketing gorilla. New for this year is the XA engine which offers SPICE accuracy.
HSPICE (SPICE) - Mature.
Strategy - flat designs simulate in NanoSim, hierarchical designs in HSIM.
Lacking - parallel simulation, why offer both HSIM and NanoSim?
Contact - Mike Demler

Cadence:
UltraSim (Fast SPICE) - couldn't find it at DAC!
Spectre (SPICE) - mature.
Strategy - hierarchical simulator stand-alone or with AMS languages.
Lacking - recent customer success stories, not parallel yet.
Contact: ?

Xoomsys - Not a SPICE or Fast SPICE simulator but enables you to use a compute farm with existing SPICE simulators.
Strategy - put all those HSPICE licenses to work on long running jobs to improve run times.
Lacking - first customer success story.
Contact: Anjaneya Thakar

Summary - To tackle big transistor-level designs or long runs requires a circuit simulator to adopt some new techniques, like: Fast SPICE, hierarchy, multiple CPUs or mixed AMS languages. Most suppliers use one or two of these techniques. Synopsys, Cadence and Mentor are the most mature product choices.


Daniel Payne
EDA Marketing Consultant

brano
(Stranger )
06/13/07 01:01 AM
Re: DAC Report: SPICE and Fast SPICE new [re: djepayne]Report this article as Inappropriate to us !!!Login to Reply

Daniel,

it's really a good report, the contacts help too.

We are already working with almost all of these SPICE-FastSPICE tools.
Synopsys and Mentor seem to have the best position in the market, even if Synopsys still has some advantage; adding parallel features they will enforce furtherly their leadership.

My best regards, B






CirSimGuy
(Stranger )
06/13/07 03:42 PM
Re: DAC Report: SPICE and Fast SPICE [re: djepayne]Report this article as Inappropriate to us !!!Login to Reply

Could you please be a little more specific with your use of the word "parallel". I ask because, just as the DAC edition of EE Times muddied the water, so does your post. What did you take parallel to mean in the world of circuit simulation?

- Threaded (hyper- or multi-)?
- Multi-core (single or multi-CPU) with shared memory?
- Multi-core (single or multi-CPU) across a network?

And to what class of problems does each "parallel" [sic] simulator you mentioned in your original post best apply?





djepayne
(Stranger )
06/13/07 10:26 PM
Re: DAC Report: SPICE and Fast SPICE new [re: CirSimGuy]Report this article as Inappropriate to us !!!Login to Reply

Parallel can mean any of the three technologies that you mentioned.

For FineSim PRO parallel is distributed, parallel processing. FineSim is aimed at analog-centric, small netlists. FineSim PRO is aimed at digital-centric, large netlists. Plus, you can use the two together. Still, the capacity is limited to 100 million devices, which is below what HSIM offers by exploiting hierarchy.

I'll find out more details about AuSim. They talked about it at DAC but haven't got anything posted on their web site yet. Their application is extracted netlists with millions of elements.

As a user I want to use multiple CPUs in parallel during model evaluation to cut down long run times to fit into my work day. Most PCs and workstations are now using multi-core, so I want to keep each core fully utilized on my SPICE runs too.

Mentor's focus is transistor-level mixed with AMS languages.

Another promise of distributed, parallel processing for SPICE and Fast SPICE is to increase the capacity of my netlist.

Xoomsys will offer distributed SPICE processing to tackle the capacity and speed bottlenecks. They are aiming at highly-coupled designs that require SPICE accuracy.

I didn't yet mention Berkeley DA, however there's a thread started in this forum where they have defined a new class of simulators called Analog Fast SPICE which emphasizes difficult circuits like PLL and ADCs without compromising accuracy and with minimal simulator options. Their simulator is a flat tool with limited capacity yet with significant success stories from Japanese consumer companies.

Silvaco's SmartSpice has had a multi-CPU capability for over a decade now and SmartSpice XL has shown speed-ups using multi-threaded parallel 4 CPU machines from Sun. This is another flat simulator aimed at the high accuracy market with a lower price-point than other SPICE providers.

From Russia comes another Analog FastSPICE tool called AVOSpice that sounds like it competes with Berkeley DA and has a capacity of 1million MOS devices on a workstation with 4GB of RAM. Their simulator exploits multi-core to typically speed up by 3X when using 4 cores.

Daniel Payne
EDA Marketing Consultant


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