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avleuten
(Stranger )
03/23/07 09:59 AM
VP Design Environment Report this article as Inappropriate to us !!!Login to Reply

For a global semiconductor player we are looking for a strong and inspirational manager to lead their global team, responsible for the continous improvement of the SOC Design Environments.

You show a strong vision and bring a successful track record in the semiconductor industry and more specifically the EDA domain.

Global challenge for a successful and self motivated leader who is willing to relocate to Europe.



tjjennings
(Stranger )
10/10/09 04:37 PM
Re: VP Design Environment new [re: avleuten]Report this article as Inappropriate to us !!!Login to Reply

I would be interested in discussing this position with you. Please reply and provide an email address and I will forward my resume and referrals. I have many years of EDA design flow development for both analog, mixed signal, rf and digital environments. This includes development of EDA tools, evaluation of third party EDA tools. I have also spent time in contract (license) negotiations.


Please contact me at tim.jennings@cox.net


Regards, Tim Jennings





dlj0811
(Stranger )
12/17/11 10:37 PM
Re: VP Design Environment new [re: tjjennings]Report this article as Inappropriate to us !!!Login to Reply

Just email floor1#~


 


Huawei dealer


 





brocksolo
(Stranger )
10/26/16 09:15 PM
Re: VP Design Environment new [re: avleuten]Report this article as Inappropriate to us !!!Login to Reply

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