>> "DIG" - Design Implementation Group for MAGMA Users
Thread views: 35860 View all threadsNext thread*Threaded Mode

(Stranger )
09/23/03 06:35 AM
RTL2GDSII Report this article as Inappropriate to us !!!Login to Reply

hello world

How big the design could be for the Magma's RTL2GDSII flow?

regards, thayalan

(Stranger )
09/30/03 04:08 AM
Re: RTL2GDSII new [re: thayalan]Report this article as Inappropriate to us !!!Login to Reply

In general, on 32bit Linux (3.5GB limit) a reasonable size is 500k cells (placable components). Then runtime from import RTL all the way to final routing is still <24h.
If you just do RTL/DFT synthesis and Prototyping, you can do a million cells flat in a reasonable runtime.

(Stranger )
11/25/03 05:19 AM
Re: RTL2GDSII new [re: larsrzy]Report this article as Inappropriate to us !!!Login to Reply

Follow-up to my previous posting:

just did a 2.3 million cell design (8-9 mill. gates) flat using the Opteron build of Magma's tool. RTL synthesis only, it used up to 6GB and needed 10h to complete. Machine had a 1.8GHz CPU and 8GB RAM.
So with a decent Opteron box, everything seems to be possible ;-)


View all threadsNext thread*Threaded Mode
Jump to


S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy