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03/03/06 11:03 AM
For the design to work, the EDA tools must too Report this article as Inappropriate to us !!!Login to Reply

For the design to work, the EDA tools must too

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Sunil Kakkar
03/03/06 11:03 AM
EDA Partnership is key new Report this article as Inappropriate to us !!!Login to Reply

Very right indeed. For the silicon to work the first time, the EDA tool(s) should have been validated on a real design project. It is key that the EDA tool be verified just as thoroughly as a RTL design, before release to customers.

Tor Ekenberg
03/20/06 12:45 PM
EDA vendors must validate tools on real tape-outs new Report this article as Inappropriate to us !!!Login to Reply

At Manhattan Routing, Inc. we pride ourselves that our tools are ALWAYS validated at the next technolgy node on real chip design work by our own services group, before general release. Since we are involved in physical design 'timing closure' tools to effectively complete the job by closing the last few hundred paths that automatic optimization tools for various reasons (tool architecture, bugs, or flawed use model) can not finish, it is critical that we are experienced in 'real' chip tape-outs. This is very different from application or consulting work, where the AE or consultant is invoved in a few steps along the way, and effectively blind to up- or down-stream issues. Instead, in these projects, we need to be knowledgable of and repsonsible for the full process of physical design, and understand when and where various trade-offs can be done that can impact everything from placement and routing efficiency to physical and functional verification. What's at stake here is more than uncovering bugs in the tools, which of course is very important, but also the notion that the tools must be designed to do the right thing and appropriately work with all other tools within the IC design flows.

Dave Doman
04/04/06 09:15 AM
trust but verify new Report this article as Inappropriate to us !!!Login to Reply

Anybody that has ever used a wrench (or even a hard leather shoe heel) to pound a nail into a wall because they didn't have access to a hammer has probably come to realize that a tool (be it a hammer, an EDA tool, or a stdcell library view) is NOT a sure solution to a problem. EDA tools (and library views) DO need to be trustworthy, BUT they can never be "real" (they are just MODELS of reality), and a user of same needs to know when to question the result and to NOT blindly accept that "the tool says that it is fine". The deeper that we go in submicron, the more that this will be driven home. If not by other tools, then just by DRC decks not being DFM decks. Maybe President Reagan's comment to Premier Gorbachev about "trust but verify" should apply to design engineers and EDA tools as well...

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