EDAToolsCafe
   >> Design Automation Products
Thread views: 10463 View all threadsNext thread*Threaded Mode

timinganalyzer
(Stranger )
02/04/09 09:54 AM
Draw Timing Diagrams - Do Timing Analysis new Report this article as Inappropriate to us !!!Login to Reply

Hi All,

The TimingAnalyzer can be used to easily draw timing diagrams and perform timing analysis to find faults in digital systems. The diagrams can be saved in many different image file formats and scalable vector formats so they can easily be added to documentation.

With scripts, the user can draw large complex timing diagrams quickly, generate test vectors and testbenches for analog and digital simulations, and add new features to the program.

The plans are to have a one version that anyone can use for personal or academic use at no cost. The same version will be very low cost for commercial use when beta testing is complete.

www.timing-diagrams.com

Suggestions for new features and improvements always welcome.


Regards,
Dan Fabrizio


timinganalyzer@gmail.com





timinganalyzer
(Stranger )
08/10/09 06:07 PM
Re: Draw Timing Diagrams - Do Timing Analysis [re: timinganalyzer]Report this article as Inappropriate to us !!!Login to Reply

Hi All,


I released a new version of the TimingAnalyzer.  Below is a list of additions and changes.



  • Added a new User Delay and Constraint Editor panel. You can add, delete, or update User Delays or Constraints.

  • These User Delays and User Constraints are saved at the top of the .tim file.

  • Changing a User Delay or User Constraint updates every one of the same type in the diagram.

  • Files created with previous versions are converted to this new format when saved.

  • Added Python Interpreter, Jython 2.5. Now you can write scripts in Python.

  • Execute Python scripts using the same script dialog for the beanshell scripts or from Jython command line window.

  • Included start_app.py script in the install directory that will start the TimingAnalyzer from a Jython command line window.

  • Updated spice_pwl.bsh. This beanshell script generates spice piece wise linear test vectors for DigitalBus.

  • Included dff.py. This Python script shows how to generate a timing diagram for a D Flip Flop.


 

Edited by timinganalyzer on 08/10/09 06:12 PM.



timinganalyzer
(Stranger )
11/16/09 04:47 PM
Re: Draw Timing Diagrams - Do Timing Analysis new [re: timinganalyzer]Report this article as Inappropriate to us !!!Login to Reply

Hi All,


I have released a new version of the program.  Version 0.945. 


A lot has happened in the last few versions but the focus has been on improving the Python scripting interface,  adding logic simulation functions to both the GUI and scripting interface , and improving the GUI zoom functions.


The list below shows all the changes in from 0.94 to 0.945.


Feedback is always welcome.


Dan


www.timing-diagrams.com


----------------------------------------------------------------------------------------------------------------------


 



  • Generate Timing Diagrams from VHDL Simulations application note. Verilog example coming soon.

  • startScript() and stopScript() scripting functions.

  • Timing diagram are broken into sections separated by TimeWarps. You can now move from section to section using the "Move Start to Next TimeWarp" button.

  • "Move Diagram Left" and "Move Diagram Right" buttons now skip correctly over TimeWarps.

  •  

  • "Zoom Full" button in toolbar. 

  • "Zoom In Between" function. 

  • addInverter() scripting function.

  • addBuffer() scripting funtion.

  • addDFF() scripting function.

  • addCounter() scripting function.

  •  

  • Inverter with optional tphl and tplh delays

  • Buffer with optional tphl and tplh delays

  • zoomIn(startTime,endTime) scripting function

  • new scripting functions. See Scripting/TimingAnalyzer and Scripting/TimingDiagram

  •     * fileNew()

  •     * fileSave()

  •     * setStartTime()

  •     * setEndTime()

  •     * setTimePerDivision()

  •     * zoomIn()

  •     * zoonOut()

  •     * addTextBelowSignal()

  •     * addTextAboveSignal()

  • Synchronous Binary Up/Down Counter with rising or falling edge clock, and optional enable, parallel load, reset, and preset inputs and clk2q delays.

  • Optional synchronous reset and preset inputs to DFF.

  • Synchronous DFF with rising and falling edge clock, and optional enable, and clk2q delays. 

  • Auto decrement when adding pulses.  This makes down counters easier.

Edited by timinganalyzer on 11/16/09 04:50 PM.



flowerjeni
(Stranger )
07/13/15 10:58 PM
Perl Training in Chennai new [re: timinganalyzer]Report this article as Inappropriate to us !!!Login to Reply

Perl really remains for "Viable Extraction and Report Language," however you don't generally need to realize that unless you need to inspire your geek companions. Perl is a scripting dialect which utilizes a language structure like C/C++. It is generally utilized by Web developers to make scripts for Web servers. Perl is particularly great at parsing content, so developers frequently utilize it for perusing and seeking through content documents.  perl training in chennai


 



Perl is a programming language developed by Larry Wall, especially designed for processing text.

agnes90
(Stranger )
09/04/15 02:41 AM
Re: Perl Training in Chennai new [re: flowerjeni]Report this article as Inappropriate to us !!!Login to Reply

Electronic design software solutions for OrCAD and Cadence Allegro PCB design ... OrCAD Cadence Allegro Autodesk EMA Design Automation More Products ...http://www.trainingintambaram.in/php-training-in-chennai.html  | http://www.trainingintambaram.in/web-designing-training-in-chennai.html





rock11
(Stranger )
12/01/16 11:34 PM
Re: Draw Timing Diagrams - Do Timing Analysis new [re: timinganalyzer]Report this article as Inappropriate to us !!!Login to Reply

This is my first visit to this website and I have read many posts here. These all are very informative for me and it increases my knowledge also. I will must visit here again to read more posts.


Top supplier of horse mats in UK






View all threadsNext thread*Threaded Mode
Jump to

 

CST Webinar Series



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy