Videos -> Virage Logic


View "Avoiding Test Escapes to Achieve Near-Zero Defects", Manish Bhatia Views: 1634 View "Logic NVM for Digital Rights Managment (DRM)", Craig Zajac Views: 1235 View SiPro Webcast Views: 2251

View "DDR High-Speed Interface Solutions", Luigi Ternullo Views: 1235 View CEO Interview:Dan McCranie, Virage Logic Views: 1377 View "Design Challenges at 32nm and Beyond Technology Nodes", Vipin Tiwari Views: 2395

View "Highly Configurable Memory for Advanced Power Management", Lisa Minwell Views: 1894 View "Optimized MIPI Application Demo", Hezi Saar Views: 675 View "Standard Cell Logic Libraries for Demanding Speed Requirements", Ken Brock Views: 2045

View "DDR High Speed Interfaces for Increasing Performance and Reducing Power", Luigi Ternullo Views: 1385 View "Addressing DDR System Level Concerns", Luigi Ternullo Views: 1429 View "DDR All-Digital PHY+DLL", Luigi Ternullo Views: 2283

View "Logic NVM for Wireless Applications", Craig Zajac Views: 5246 View "NVM for Power Management", Craig Zajac Views: 1331 View "Demo of SiPRO PCIe PHY" Views: 1324

View "Live Demo of DDR3 IP in 65nm" Views: 939

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