The "folding" architecture is one of a number of possible serial or bit-per-stage architectures. Various architectures exist for performing A/D conversion using one stage per bit, and the overall concept is shown in Figure 1. A multistage pipelined subranging ADC with one bit per stage and no error correction is basically a bit-per-stage converter. In practice, this type of pipelined converter generally uses a 1.5 bit per stage approach to provide error correction (this is discussed in more detail in Reference 1).
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Editorial
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DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
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