This Getting Started tutorial demonstrates how to compile a simple digital signal processing (DSP) filter written in C into HDL, ready for FPGA synthesis. The goal of this application will be to generate a 16-bit, 12-tap FIR filter as hardware in the form of either VHDL or Verilog. Although this is a relatively simple example in terms of the required lines of C code, it does illustrate some key concepts of Impulse C including the use of streaming and pipelining for high performance.
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Editorial
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DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
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