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Floorplanning is the process of identifying structures that should be placed close together, and allocating space for them in such a manner as to meet the sometimes conflicting goals of available space (cost of the chip), required performance, and the desire to have everything close to everything else.

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"Challenges for Digital Timing Sign-off at the 20nm Node", Ruben Molina, Magma
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"New PCIe UVM Verification IP and UVM Tips", Craig Stoops
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"New TotalHistory Debugging for Rapid Prototyping ", Shyam Uma Chander
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Corporate Newsletters

AWR E-News Jan. 2011: Thermal Analysis White Paper and SDR Application Note

KiloPass MemoryPill, Issue #1 January 2012

News from Apache Design - January 2012

Cadence News Jan. 2012: Save on CDNLive! - New Advanced Verification Book - 2012 Forecast

Aldec Design and Verification Newsletter Q1, 2012

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Important Notices

DVCon 2012 Technical Program and Registration, Feb. 27 - Mar. 1

Common Platform Technology Forum, March 14: A Decade of Invention… A World of Solutions

Sensors - Technology, Design & Application - March 21 Santa Clara CA

Call for Papers - ASQED 2012, Malaysia due April 4

ICCAD 2012: Preliminary Call for Papers due April 16

Editorial

	Russ Henke EDA Weekly Silicon Valley: EDA Magnet! Since this writer began the current series of EDA WEEKLY articles back in November 2009, the exploits of …
Archived Weeklys

	Mark Gilbert EDA Careers Corner & More A BILLION DOLLAR AQUSITION YEAR...WOW... The Synopsys Magma Merger, what it really means to Careers...My take on Career Prospects for 2012
Archived Careers Corner

	Dr. Russ Henke EDA & IP Commentary The EDA and MCAD/MCAE Almanac -Nominal Q3 2011
Archived Commentary

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Upcoming Events

Tin Whiskers - A 2011 State of the Industry Assessment at United States - Feb 14 - 21, 2012

Pan Pacific Microelectronics Symposium at Sheraton Poipu Resort Kauai HI - Feb 14 - 16, 2012

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