September 29, 2003
Make New Friends, but Keep The Old
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
| by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!
Gary Smith is the chief EDA analyst for Dataquest/Gartner Group. I asked him in a recent phone call to talk about the evolution of EDA tools and to comment on the advisability of re-packaging or re-purposing older tools under the guise of new tools. Gary, by his own admission, has been in the industry for a long time - as a customer and an industry analyst. It's for good reason that when Gary speaks, the industry listens. His wide-ranging comments on the evolution of the tools are as follows:
"Basically, the main driver of the tools is the silicon. In essence, an EDA lifetime [for a generation of tools] is two process nodes. Every two process nodes, we run into significantly more severe problems, so that we [find ourselves] having to re-tool. That's been the driving force for moving to the next generation of tools. But the fact that the products [that emerge as a result of the new tools] are more complex, means that the boards are more complex and means that the tools have a wide effect in delaying [the introduction of new products] out into the market."
"[As it turns out], every 10 or 12 years, there's a major inflection point where we come to a place in [design] complexity that we can no longer use the current methodology and timing [strategies] to produce functional silicon. So far, we've seen three generations of tools."
"Initially, there were CAD companies - Calma and the like. The tools from these companies were used to design transistor-type designs, designs that included a handful of transistors like the 7400 logic family from TI. When a maximum of hundreds of transistors started stretching into VLSI-type designs, which included thousands of transistors, we started running into problems."
"Then we moved to the next level of abstraction - gate-level technology, where you designed a physical library, and that physical library became the basis for a design platform, which was basically schematic capture and logic simulation. At the transistor level or CAD level, Spice was our simulator. Those were the days of Daisy-Mentor-Valid and those tools not only did IC design, but also started doing the PCB design, which at that point started to be automated as well."
"[However], once we started approaching 20,000 gates, we found we could no longer get designs out. [Meanwhile], the design cycle has been 9 months to a year FOREVER. They talk about ever-decreasing time for designs - it had decreased by 1997, in fact, in every industry except the automotive industry. The auto industry tried to get it down to 9 months, [but had difficulty doing that]. Historically, the aeronautics industry took 3 to 5 years to get a design out, the automotive industry takes 1 to 2 years, but the computer guys were always at 9 months. Now, everybody is at 9 months."
"[As a result], when you start a design you always ask, 'How much functionality can I put into a design in 9 months?' When we hit 20,000 gates, we found we really couldn't get that many gates done in a 9-month period. That's when you saw the emergence of the RTL technology. [RTL] was pushed commercially - remember LSI was renowned for having the first gate-level simulator, or maybe we can blame IBM, but Synopsys and Cadence came along with this RTL methodology.”
“The RTL technology has proven to be fairly robust - it's been [the norm] for longer than 10 years. We went into floorplanning-based design and the infamous IP snafu, and saw productivity go up by 360%. It's all been due to the major boost out of RTL design."
"Now, however, we're out of steam - as of last year, actually, with 90 nanometers. [Today], we're in the middle, somewhere between the 130 and 90-nanometer tool families. But at 100 million gates, none of the initial products for power users are useful - we find we don't have the tools.”
“[It's true], there are quite a few designs with 40 to 50 million gates, some for example from IBM, some from Agere Systems, and you're now seeing a second generation of designs coming out of the big guys at 77 million gates. I've even heard stories in excess of 90 million gates - they're doing the design with ESL methodology and in-house tools. Well, actually, there are some commercial tools [in use there as well], but designs are being done with a combination of in-house ES-level tools and brute strength."
“I was on a panel recently at DATE [in Europe] and heard discussion of 25 designs that have been done with SystemC. SystemC is part of the reason that we're being able to move up [into higher levels of abstraction in design]. Everybody [on the panel] had used CoCentric tools after the architectural tools were done. There were some low-level tools being used - Axis Systems' XoC tool was a major breakthrough in ESL verification. [Today], Cadence has Incisive, which is a similar tool, but not as powerful - it doesn't [have the] concentration on the software side.”
“One mistake that all of the EDA vendors have made is that they forgot about the software. [Historically], they concentrated on the hardware tools, but ESL tools have to combine both hardware and software [considerations].”
“As a sidebar here, it's important to note that one of the reasons that Verilog doesn't compete with SystemC is that it's not a software-centric tool at all. Verilog's an RTL tool and SystemVerilog is just a misnomer. I had a guy tell me at DATE that when we first attempted this - in 1994, or '95, or '96 - we were going to use VHDL with all of its software capability. But we [ended up] saying, 'Ouch - that was painful!' I head another comment at DATE: 'You think that writing software in VHDL was painful, try writing it in Verilog!' Also the other comment I heard being made at DATE: 'SystemVerilog is great. It's finally caught up with VHDL!'”
“[Meanwhile] back to tool evolution - what did Synopsys do? They took over the RTL-level methodology, which made them Number 1. [After all], if you own the methodology whose sales go from the RTL level to the gate level, money will be made at the ES level. That's one of the reasons that Synopsys hasn't put together a good virtual silicon prototype. Because when they do, mainstream users won't use their tools any more. Their customers are the ASIC designers and the company wants those guys to buy their layout tools. There's a big reluctance to admit that your world, the one that you own, is going away. [Historically], that was Mentor's problem as well.”
“Mentor's good news/bad news was that they owned the military world. But as we moved up to the RTL level, military budgets got slashed as the Berlin wall came down. The military were power users and they didn't move to the RTL level. Mentor sat around and asked their customers - the military - if they were going to make the move and the customers said they'd never do that. Mentor said, 'You won't?' The military said, 'We need a good framework.' So the Falcon framework was developed, while Synopsys and Cadence took the rest of the market away.”
“[Today], Cadence has lost the power users to Synopsys - their customers are mainstream. Cadence customers are saying, 'We need a good framework.' So today there's OpenAccess. Now there's nothing wrong with a good framework - a completion of the methodology so that you can take engineers and move them up into ES level work and design. If ES becomes the design level, then RTL becomes the implementation level, just as ASIC implementation is design in the gate-level world - give them a netlist and let them do it in silicon.”
“Meanwhile, power users are going to continue to do their own layout. They know that you always lose 15% when you move up to the next level. But as you get better, older, more mature - you know you always have to lose 15% as you get that much farther away from the silicon. That's a given.”
“We've got something I call the old tool syndrome. You've always used your old tools. They're in the flow, they're being used. The oldest tool is Spice. We've found that in RTL and all the way throughout, when the problems get tough
I first saw it in 1990 or '91 with critical paths - the Verilog timing analyzer was not accurate enough to pick up all the timing violations. At the time, I told a guy he could just Spice those critical paths, because the timing violations wouldn't pass. The guy asked me what Spice was, and I said it was analog simulation. He wouldn't use it. The next time somebody asked me for a solution and I suggested Spice, I said it was transistor simulation.
Then it was
used and used successfully. Even now as we're moving up, we're seeing fast Spice being used a lot - providing the accuracy of the old transistor level.”
“Engineers are by nature very conservative, their motivation is the engineering. When the pain gets large enough, however, they'll change. Part of it is the fear factor - 'Am I too old to be doing this?' But I went through this in the 1980s and that's a bunch of BS. Engineers do sometimes drop out and become implementation engineers, letting the design world pass them by. In the transistor world, for instance, they became library developers because they couldn't think in gates. But today, if you've got a full set of engineers in the flow, those who are doing design and those who are doing implementation, you'll find they'll work in a team.”
“You've got two choices as an engineer today. You can remain at your level and be the implementation engineer - the transistor guy or the library developer. Or you can move up with the design trend to ESL and remain even more important on the project. The question is - are you a designer or do you just want to perfect the implementation?”
“Either way, if you enjoy thinking and growing, you enjoy being an engineer. It's hard work and you have to keep up with a rapidly developing industry. But in fact, there's nothing better than an old engineer working on a design team - they've been there, done that. I like the concept of the long, tall engineer. I've seen studies that say performance increases by 70% over the lifetime of a working engineer. Just look at the ITRS roadmap - you'll see significant improvements in productivity when somebody actually understands the flow.”
“Oh yeah, and don't throw away your old tools. Make new friends, but keep the old.”
Polling the Industry
I sent out an informal poll asking companies to detail the evolution of some/all of their tools and tool suites. Admittedly, this is a difficult question to put forth. My e-mail request said:
“Lots of the readers of EDAToolsCafe wonder whatever happened to some of their old favorite products and companies. Can you tell me which tools you have either [obtained] through acquisition and are still marketing, or which tools your company has re-purposed under a different product name, but are still major contributors to the product portfolio.”
“This is not a thinly veiled attempt to show that old tools are being marketed as new tools. Neither is it a scientific survey. It's more of a qualitative look at tool evolution in the EDA industry. Please deal with it in that spirit.”
I am grateful to the companies who took the time to respond, or more importantly had the courage to respond. The responses are listed in alphabetical order, with the exception of the response I received from Altium, Ltd. Altium's narrative was lengthy and compelling (please look past the embedded marketing message) and told a story indicative of how technology developments are woven into the history and fabric of a company.
1 - Applied Wave Research, Inc.
ACOLADE from I/Q Com Corp. was acquired by Applied Wave Research (AWR) in 2000 and re-launched as Visual System Simulator (VSS)in 2002.
2 - Cadence Design Systems, Inc.
The old OrCAD PCB tools that were acquired by Cadence and renamed several different times under the Cadence brand (Orcad PCB, Allegro, etc.). Recently they emerged again under the old OrCAD brand from Cadence, but they are being marketed by a distributor - a unique development.
3 - Fintronic USA, Inc.
Fintronic developed the FinSim line of Verilog simulators and sold the first one in 1993. Also, in mid 1993, Fintronic did a multi-million dollar OEM deal with Intergraph, which marketed the FinSim simulator under the name of Veribest and sold over 1000 licenses to numerous companies including Scientific Atlanta, Hitachi, Xillinx, AMI, etc. The OEM deal was amicably terminated in 1999, and Fintronic continued to develop and market the FinSim simulators, as well as to offer maintenance to all the owners of Veribest simulators.
4 - Icinergy Software Co.
Icinergy reports no acquisitions to date, but the company did recently repackage their products, so that what was SOCarchitect is now known as SoC Prototype.
5 - Mentor Graphics Corp.
Innoveda was acquired by Mentor Graphics and is now part of the Mentor Graphics Systems Design Division. Innoveda resulted from the previous merger of ViewLogic, PADS and HyperLynx. Mentor Graphics continues to invest in the PADS product line, the market standard for Windows-based complex PCB design. The latest version, PADS Suites provide complete, front-to-back, PCB system design flows in three configurations; PADS PE, PADS XE, and PADS SE, with increasing functionality to support a variety of design needs from individuals to small teams. Another former Innoveda tool, HyperLynx, which is a powerful and easy-to-implement PCB tool suite for pre- and post-layout signal
integrity (SI) simulation and analysis, is part of Mentor's high-speed PCB design solutions. The latest version, HyperLynx 7.0, is available in two versions, the HyperLynx EXT tool for mainstream designs with clock frequencies under 500 MHz, and the HyperLynx GHz tool for multi-gigabit designs.
Accelerated Technology is now part of the Mentor Graphics Embedded Software Division. Mentor Graphics continues to market the Nucleus Real Time Operating System and the Code/Lab Developer Suite. The Accelerated Technology products were merged with the Mentor Graphics embedded software tools that included the VRTX Real Time Operating System, the XRAY Debugger, and the Microtec Compilers.
IKOS Systems is now part of the Mentor Graphics Emulation Division. Mentor Graphics continues to sell and market the VStation emulation system family. The latest version was a 30-million gate capacity emulator.
6 - Sequence Design, Inc.
Sente's Watt Watcher technology is currently part of Sequence's PowerTheater.
Sapphire's FormIT and FixIT, as well as Frequency's Copernicus, are part of Sequence's PhysicalStudio tool for the concurrent optimization of timing, power, noise and voltage-drop.
Frequency's Columbus is still Sequence's Columbus solution for the extraction of capacitance, resistance and inductance.
7 - Synopsys, Inc.
Following are samples of specific products acquired through acquisitions [over] the past two years.
Through the Avanti acquisition, Synopsys [obtaied] Milkyway (design database), Astro, Apollo, JupiterXT, Star-RCXT. All continue to be marketed under the same name. HSPICE was also acquired from Avanti and continues to be marketed and sold. It is now part of the new Discovery AMS solution that was announced on Monday.
Through the InnoLogic acquisition Synopsys gained its ESP products, ESP-BV, ESP-CV, ESP-LV, which are functional equivalence checking tools for memory designs. They continue to be marketed and sold under the same name.
Through the Numerical Technologies acquisition, Synopsys acquired CATS and i-Virtual Stepper. Both products are sold and marketed under the same name.
Through the InSilicon Corp. acquisition, the following IP cores are still marketed and sold under the same name: PCI Express, PCI-X, PCI, USB 2.0 Full Speed On-The-Go, USB 2.0 PHY, USB 2.0, USB 1.1, 10/100 Ethernet, Gigabit Ethernet, IEEE 1394, JPEG2000, JPEG, Java Accelerator.
8 - Verisity Design, Inc.
Verisity acquired SureFire Verification in 1999. The main tool we got from that acquisition is SureCov, which the company is still marketing and selling.
9 - Altium Ltd.
Acquisitions have been intrinsic to Altium's strategy and provided the primary motivation for the company's decision to go public in 1999. To date, the value of these investments has totaled nearly US$100M. The focus has been to acquire technology (and the people behind it whenever possible) in order to complement our internal development efforts. Principle acquisitions have been around the PCB, FPGA and embedded design space, as well as IP. The goal is to assemble a complete, integrated design platform consisting of high-quality technology that is accessible to mainstream engineers.
Altium's business and development models have been engineered to support the acquisition process. This has allowed us to quickly and profitably integrate new companies and technologies into our environment with minimal risk or disruption. We've learned that it's vital to quickly transfer the acquired core technologies into our development stream for delivery to customers. Ownership of technology, as opposed to licensing/OEM agreements, is an important element in our acquisition strategy as it safeguards our ongoing ability to package, deliver and upgrade our products at reasonable cost.
Fundamental changes in the electronic component industries are driving this requirement for more integration, particularly the move to large FPGAs, which creates the need to integrate the board-level and FPGA-level design processes. This is because of the high FPGA pin-counts and the large portion of board-level logic now going onto the FPGA. The inclusion of embedded software technology and IP cores will allow the incorporation of microcontrollers and processors into these FPGAs. This combination of hardware and software design capabilities within a single platform will allow mainstream engineers to approach design at the system level using the skills and methodologies with which they are
The high cost, complexity and poor integration of current design flows now constitutes a significant barrier for the bulk of the electronics industry to the point where only the biggest companies have resources sufficient to overpower these obstacles. Altium will provide a comprehensive solution to this problem which has been engineered, packaged and priced for the balance of the industry.
Acquisition of NeuroCad Inc. for NeuroRoute autorouting technology. Since purchase, this technology has been developed and extensively re-engineered by Altium for inclusion as standard in the full-featured Protel and P-CAD product lines - the latest generation is referred to as “Situs” topological autorouting technology.
This acquisition was the first in a long line of substantial technology purchases aimed at taking Altium to the fore of the EDA industry by differentiating and positioning Altium's products as 'complete design solutions', as opposed to the path taken by most, if not all other vendors, which provided a collection of what are really “point tool solutions”. For example, the process of printed circuit board (PCB) design includes the processes of schematic capture, circuit board layout, autorouting, logical and physical circuit analysis and generation of various manufacturing outputs. Altium believes that all of these technologies must be included in any board design solution. More
users should expect these technologies to be seamlessly incorporated into the standard design flow of a single application and solution, rather than being treated as separate processes.
Acquisition of CUPL Programmable Logic Device (PLD) compiler technology from Logical Devices. This technology is currently featured in Altium's Protel and nVisage products.
Acquisition of signal integrity technology source code license from INCASES Engineering GmbH. This technology has been actively developed and is included in Altium's Protel and P-CAD products, where it is supplied as a standard feature of the full package, not as a high-priced extra. This is in line with our core philosophy to provide the widest possible access to technologies, and to integrate into the standard tool mix previously expensive and restricted technologies.
Acquisition of MicroCode Engineering. When Altium acquired Microcode it sold two main products - CircuitMaker (schematic capture & simulation) and TraxMaker (PCB layout and routing). Following the acquisition, Altium bundled the technologies together and released the “CircuitMaker 2000” product, eliminating the need to purchase multiple products and giving entry-level designers & electronic design educators a Virtual Electronics Lab in one low-cost package. MicroCode's mixed-mode simulation technology has also been extensively developed post-acquisition and features as standard in Altium's Protel, P-CAD and nVisage products.
Acquisition of Accolade Design Automation. Accolade Design Automation, Inc., was a system-integrator and producer of VHDL simulation and VHDL-based FPGA design solutions. At the time of the acquisition, Accolade primarily sold two product lines - PeakFPGA & PeakVHDL - with Accolade OEM'ing much of the technology from Green Mountain and Metamore Inc.
Acquisition of VHDL compiler and simulation technology (permanent, unrestricted source-code license) from Green Mountain Computing Systems. The acquisition of the Accolade product line, coupled with the acquisition of the Green Mountain source code (an important technology component of Accolade's PeakVHDL simulation products) provided Altium with key VHDL and FPGA design technology and products. These technologies are core to Altium's strategy of providing accessible, integrated solutions for all aspects of electronic design, from the initial phases of design entry to the physical realization of components on a board including FPGAs.
Acquisition of ACCEL Technologies, Inc. This acquisition was somewhat different from the selected technology driven acquisitions that both preceded and followed the acquisition of ACCEL, and was initially seen as a market share growth opportunity. However, through innovative re-design of the former ACCEL product line and a re-structuring of ACCEL's sales model to rapidly integrate it into its own sales structure, Altium was able to turn what was essentially a loss making business into a positive cash flow business in less than four months. In fact by June 2000, five months after the acquisition, sales of the reinvigorated P-CAD brand surpassed all previous revenue records held in the
history of Accel Technologies, Inc. Further P-CAD product releases strengthened and encouraged brand loyalty by providing customers with all necessary tools for specialised PCB design without increasing the cost of tools.
Acquisition of Innovative CAD Software, Inc. best known for their CAMtastic Computer-Aided Manufacturing (CAM) software product line. Altium continues to develop and sell the CAMtastic product as an independent CAM verification tool and has also integrated the CAM technology into the Protel & P-CAD product lines as a standard feature.
Acquisition of Metamor Inc. for FPGA/VHDL synthesis technology. The acquisition of Metamor and its widely used FPGA synthesis products, combined with the acquisitions the previous year of Accolade Design Automation and the Green Mountain VHDL simulator, gave Altium the necessary design technology to further broaden its product range and spearhead its participation in the FPGA design market - one of the fastest-growing EDA market segments.
Today these technologies are featured in Altium's nVisage FPGA design tool and will also live in future BoC technology-based products.
Acquisition of TASKING BV. products continue to be developed, marketed and sold as Altium's world-leading brand of tools for embedded software development for targeted processor architectures. Furthermore this acquisition of embedded software development tools is very much a key component of Altium's strategy to define the next generation of the electronic design tools, and to further its strongly-held view about the need for convergence between the EDA and embedded software domains.
Various microprocessor IP core and virtual component acquisitions from vendors such as Evatronix S.A., Silicore Corp., and CAST Inc.
For now, Altium has all the necessary technology it needs to produce its next-generation design products. The major ongoing development project has been to integrate the acquired technologies with Altium's in-house technology. This work is now nearing fruition as evidenced by our recent BoC technology demonstrations (May 2003) - the first of many such announcements in this area in the near future.
Altium's acquisition strategy, however, is very much an ongoing process - as we see new emerging technologies and processes becoming important for mainstream engineers, we will seek to add them to our existing tools or generate new product lines. Altium's uniquely scaleable and opportunistic business model is aimed at directly connecting engineers with design technologies. Our acquisition strategy has been formed to compliment our internal development and is designed to support this business model.
Industry News -- Tools and IP
Aptix Corp. announced that the ARM926EJ-S core-based Soft Macrocell Model (SMM) runs on Aptix pre-silicon prototyping systems, the Aptix System Explorer and the Aptix Software Integration Station, and is now available for immediate use by Aptix customers. The companies say that ARM processor system designers now can use ARM IP and “take advantage of the speed and debugging capability of the Aptix systems.”
Axis Systems, Inc. announced that SOC Design Center of Canon Inc. has acquired an Xtreme-II emulation system to verify SoC designs used in next generation copiers, digital cameras and printers. The companies say that the Xtreme-II will be used in the SOC Design Center at Canon's Platform Technology Development headquarters in Japan. The Canon design team will use the Xtreme-II system for simulation acceleration and targetless emulation on multiple levels of abstraction, including gates, RTL, and behavioral, as well as for the verification of software early in the design cycle. Yasuhiro Tani, General Manager of SOC Design Center, is quoted in the Press Release: "After evaluating
Axis' technology, we expect to see dramatic reductions in design time as all of our designers start to use the Xtreme-II system with its small form factor, ease of use, and HW/SW co-verification capability."
BindKey Technologies, Inc. announced its RapiDesignClean layout tool will adopt the OpenAccess database, which the company says will enable tight links with the newly introduced Cadence Virtuoso custom design platform. Tom Daspit, Director of Marketing for BindKey, is quoted in the Press Release: "Support for OpenAccess is an integral part of our commitment to making RapiDesignClean's unique, must-have advantages available to as many layout engineers as possible. In addition to supporting OpenAccess, we are also a member of the Cadence Connections Program. Our participation on both fronts further contributes to open interoperability and ensures ease of tool integration for our
Also from BindKey - The company said that RapiDesignClean will add support for the Linux operating system. BindKey is a DuPont Photomasks company, which introduced a major redevelopment of RapiDesignClean earlier this year that the company says included support for manufacturing design rules at 90 nanometers and below.
Cadence Design Systems, Inc. announced version 3.2 of the company's Encounter digital IC design platform. The company says that Encounter 3.2 delivers “enhanced timing optimization, placement, and other technology for very large, fast ICs. The result is more rapid design closure and shorter overall development times.” The new release permits designers to assess the routing feasibility of different chip-floorplan and package-layout combinations, new ECO routing capability in NanoRoute, NanoRoute technology in virtual prototyping, and improved clock tree algorithms for high-speed designs. Rick Sergi, Technical Manager for the IO Floorplanning Group at
Agere Systems, is quoted in the Press Release: “We are impressed with the recent progress made within Encounter to support concurrent silicon-package design. As partners with Agere in developing these new capabilities, Cadence has been extremely responsive in introducing tools that will facilitate a collaborative approach to design of the silicon-package interface.”
Also from Cadence - The company announced it has started a collaboration with dSPACE, a supplier of tools for developing and testing new mechatronic control systems. The companies say the collaboration will support the Cadence “vision, flows, and methodologies for the design of distributed safety critical control applications for car electronics.” Cadence says that, in collaboration with various European automotive companies, it has been adapting and extending existing components of its system-level design technologies for automotive-specific uses and creating a distributed model-based design environment for car electronic architectures. The environment extends the
approach - targeting a single electronic control unit (ECU) at a time, from specification to software implementation - to a work flow where the entire system, constituted by a network of ECUs, is modeled and validated by running simulations on a host workstation. The company also says that the work flow supports the shift from physical prototyping to virtual prototyping, by providing capabilities for model import, integration, and simulation before hardware is available.
Celoxica announced the immediate availability of a new C synthesis tool package that provides “a low-cost entry point into C-based system-level design.” The company says the Platform Developer's Package (PDP) allows engineers to target C algorithms to off-the-shelf development boards or evaluate C-based design methodologies, and that the product provides “cycle-accurate design simulation and C-based synthesis to FPGA logic.” PDP is described as an entry-level version of Celoxica's DK Design Suite of system design tools, one that includes a board support package for targeting designs to one of several supported development boards.
Good news for Carl Murphy, Vice President and CTO at Accord Solutions, who is quoted in the Press Release: “The effectiveness and quick results made possible by Celoxica DK tools on a critical kernel directly led to a large contract win. Now with the PDP product's pricing and associated board platforms Accord Solutions can afford to make delivery of a fully operating PDP environment and board package to our clients. This is key to our client's ability to raise more funds for our technology advancement.”
Emulation and Verification Engineering (EVE) announced that its ZeBu (Zero Bugs) tool integrates with key software technology from Synplicity Inc. The company also announced that EVE has joined the Synplicity Partners in Prototyping Program. The companies say that through this partnership, EVE customers can use Synplicity's technology to implement their designs into the Xilinx Virtex II Platform FPGAs used in EVE's verification system. Lauro Rizzatti, Vice President of Marketing at EVE, is quoted in the Press Release: “Synplicity is an important and valued partner. Joining its partner program ensures ZeBu customers have access to powerful software used for ASIC or FPGA
LogicVision, Inc. announced its new generation of test solutions, LV2004. The product offering is an integrated family of products that the company says “streamlines the integration of embedded test into SOC designs and enables test automation and access at the design, debug and manufacturing test stages, and throughout the SOC life-cycle on boards and in the field. With LV2004, designers can easily integrate powerful embedded test structures into their designs, removing barriers to achieving significant quality and cost benefits downstream.”
The company says that LV2004 simplifies embedded test integration into SOC designs, resulting in minimal design cycle impacts, with the Embedded Test Planner predictive analysis tool used to discover incompatibilities between an SOC's design architecture and embedded test requirements, improved links and automatic generation of design constraints and timing analysis to increase the compatibility of test with the physical design process, the first industry use of Wrapper TAP (WTAP) technology for hierarchical and fully scalable access to all embedded test structures, compatible with the IEEE P1500 industry standard, and support for Linux RedHat. Additionally, the new product includes memory
BIST controllers that perform repair analysis concurrently with the at-speed test of the memories, improved contactless I/O test capability for highly accurate I/O leakage testing using existing IEEE1149.1 boundary scan hardware, and new automated test support for high speed AC-coupled I/O interconnects that are fully compatible with the IEEE 1149.6 standard.
In addition, the company says that two lower cost debug stations are now available from LVReady Partners, Inovy's Ocelot, and Teseda's V500. Both these ATE systems are now fully qualified with LV2004. LV2004 has also been integrated with and qualified on ATE platforms from Agilent (Smartest) and LTX (Envision).
Mentor Graphics Corp. announced that Zoran Corp. has adopted Mentor's Calibre xRC tool as its internal standard for GDSII parasitic extraction. Noga Dayag, CAD Manager at Zoran's operations in Israel, is quoted: “Calibre xRC is the only tool that extracts both gate and transistor-level parasitic data from a GDSII environment. The sign-off procedure based on the extracted GDSII data is the most reliable and accurate way to validate the design performance. In addition, it was easy to integrate Calibre xRC with our layout and static timing tools.”
Just in time for ITC - Mentor Graphics announced the availability of improved performance and advanced at-speed test capabilities in FastScan automatic test pattern generation (ATPG) tool. The company says these enhanced test capabilities improve defect detection for nanometer designs and permit customers to improve the quality of test for their complex integrated circuits (ICs). The latest version of the FastScan tool includes user-defined capture procedures, accurate at-speed fault simulation, improved performance, and diagnostics for at-speed patterns.
Raj Raina, Manager of Design Technology & Standards for Network & Communications Systems Group of Motorola's Semiconductor Products Sector, is quoted: “Pattern generation time was reduced from weeks to days and the user-defined capture procedures facilitated accurate at-speed testing using the device's on-chip clocks. We are now testing the core at 25 times the maximum speed of the test equipment, with no additional requirements placed on the tester itself.”
Finally, also from Mentor -- The company announced that Procket Networks, Inc. has standardized on the Mentors' FastScan ATPG tool for development of its multi-million gate SoC designs. Utilizing the latest improvements in the FastScan tool, Procket realized a 10X improvement in performance as well as a 20 percent reduction in pattern count on its latest 17-million gate design, for its industry-leading Very Large Scale Integration (VLSI) technology.
Jeff Purnell, Vice President of Engineering at Procket Networks, is quoted in the Press Release: "The performance improvements Mentor Graphics has made to its FastScan tool have allowed us to reduce run times from weeks to days, and in some cases, from days to hours. At the same time, we also realized a significant reduction in pattern count. To meet the stringent quality and reliability requirements of our systems, Procket Networks employs a robust test suite of Path Delay and Transition Fault vectors for speed testing. Mentor was extremely responsive to our
needs in developing these tests, and made significant improvements in the generation of test vectors. As we move to our next generation VLSI design - our biggest design yet at 40 million gates - the FastScan tool will play a crucial role in helping us meet our time to market, cost and quality goals."
MIPS Technologies, Inc. announced that Zoran Corp. has taken additional licenses for the MIPS32 4KE cores, and a new license for the 32-bit M4K core. The companies say that these new agreements broaden Zoran's adoption of the “industry-standard MIPS architecture as the company continues to develop leading solutions for high-growth embedded markets.”
Neolinear announced that 25 of its semiconductor design customers will receive an enhanced version of the Rapid Analog Design layout engine NeoCell. Some of the new RAD capabilities include a faster analog router, a new “clean algorithm” that minimizes the number of vias used during routing, enhanced functionality to clean and update any routing that has been rendered invalid as a result of an engineering change order (ECO), new analog constraints, routing of self-symmetric nets to achieve balanced routing for structures such as T-nets, support for partially-symmetric nets, enhanced module generators, plan generation capabilities, and an API to access the in-memory
automates the generation of cell layouts in the background and migrates existing layouts to a different technology or a different set of device sizes.
Synopsys, Inc. announced the availability of Discovery AMS, which the company describes as a “new and comprehensive simulation solution that delivers significant productivity improvements for analog and mixed-signal verification.” According to the company, with Discovery AMS, designers can now create their entire design with Accellera's Verilog-AMS language, launch all simulations from a single integrated control environment, and efficiently use parasitic data for post-layout analysis.
Discovery AMS is built upon VCS MX, NanoSim, and HSPICE, to deliver “superior performance, capacity and accuracy for mixed-signal simulation compared to SPICE based solutions.” The product has a built-in simulation control engine that provides design partitioning, a single engine to launch simulation runs, and a unified display of both analog and digital signals. HSPICE, with foundry-certified device models, provides the requisite simulation accuracy when used with VCS during the design phase.
NanoSim, the fast SPICE simulator, coupled with VCS delivers simulation throughput during the verification phase.
Bijan Kiani, Vice President of Marketing for the Analog Mixed-Signal group at Synopsys, is quoted: “Discovery AMS is tightly integrated with Star-RCXT for efficient use of parasitic data, enabling our customers to meet their toughest mixed-signal verification objectives. Synopsys worked with leading edge analog mixed-signal customers including Toshiba to provide further validation of our solution in this increasingly critical area.”
Also from Synopsys - The company, in conjunction with Artisan Components, Inc., announced a collaboration to provide mutual customers with advanced design flows and broad technology support for "certain" Synopsys Galaxy Design Platform tools for 130-nanometer designs and below. Specifically, the companies say they are cooperating to provide Artisan customers access to free library views for noise for Galaxy signal integrity (SI), timing, and power using scalable polynomial modeling, TetraMAX ATPG, and Hercules physically verified components. The companies add that they will broaden joint efforts to develop and deliver new products for nanometer-scale design, and that they have
already defined SI modeling capabilities in the Liberty (.lib) open library standard, to be delivered via Artisan's Foundry Library Program.
Undoubtedly the two companies agree that having omnipotent ARM endorse the announcement is a good thing. Simon Segars, Executive Vice President for Engineering at ARM, is quoted in the Press Release: “As a leader in the design and delivery of synthesizable microprocessor cores, hard microprocessor cores and synthesizable peripherals for SoCs, we foresee real benefits from the ease of use, performance and predictability afforded by using Synopsys tools with Artisan's silicon libraries."
Meanwhile - Synopsys and ARM have announced that the ARM-Synopsys Reference Methodology, first introduced in 2001, now supports Galaxy SI, within the Galaxy Design Platform. The companies say adding signal integrity enhancements that address crosstalk delay, noise (glitch), IR (voltage) drop and electromigration to the ARM-Synopsys Reference Methodology gives ARM Partners a "complete SI-aware implementation solution for all ARM synthesizable processor IP.”
Simon Segars, Executive Vice President of Engineering at ARM, is also quoted in this Press Release: "Three years ago, we started working on the ARM-Synopsys Reference Methodology, this has been continuously refined and augmented. This Reference Methodology is used as a standard flow inside ARM for hardening IP. We have had success in multiple hardening projects and we are currently working on timing closure at 90 nanometers. Complete, integrated reference flows have already been delivered to
our ARM1136JF-S core Partners, the new signal integrity capability, enables our Partners to resolve noise and cross-talk issues through the use of Synopsys' PrimeTime SI and Astro-Xtalk."
Teseda Corp. announced that Dai Nippon Printing (DNP) purchased a Teseda V500 design-for-test (DFT) focused engineering test system. DNP says the company is using the V500 to test engineering samples for customers who use DNP's IC design services. Osamu Ootake, Manager for the LSI Design & Development Department at DNP, is quoted in the Press Release: "Our customers used to obtain untested engineering sample devices from the foundry because the cost of testing small samples of devices was too expensive. With the V500, we can provide our customers with samples that have been tested at an affordable price. Because our engineers can debug tests very quickly with the V500, we can
also provide customers with tested devices soon after we receive the samples from the foundry."
Coming soon to a theater near you
Network Processors Conference 2003 - This 3-day event will be taking place in San Jose, CA from October 21st to the 23rd. Organizers say, “More than 50 of the sharpest minds in the world of networking-silicon will gather at the Conference to share their vision of where this fast-moving field is heading. Linley Gwennap, the leading analyst in this field, has put together an outstanding program focused on major trends, new announcements, and significant breakthroughs. A special OEM session will be held featuring leading equipment manufacturers Nokia, Siemens, and Extreme Networks. This year we are featuring two keynote speakers: Mark Granahan of Agere Systems and Jerry Fiddler of
River. The program is packed with practical information on the latest advances in network processors plus demonstrations of the hottest new products. Here's your chance to get up to speed in the areas that are critical to your success.”
Who can argue with success? Sounds like you'll be wanting to attend. (
Seminar and Workshp on SystemVerilog - The question posed at this event - "Is SystemVerilog in Your Future?" - is one you might want to ask before attending either this workshop or the one described below. Assuming that you've determined that the answer is “Yes,” however, then maybe Stu Sutherland's half-day seminar, which introduces extensions to the existing Verilog language that enable modeling and verifying larger designs, is for you. The Sutherland HDL workshop is happening on October 2nd in Folsom, CA, and on October 13th in San Jose. It does cost to attend, but includes lunch and refreshments. There's also a lengthier 4-day version offered in October in San
those who really want to dive in up to their elbows in the “nuts and bolts” of the language. (
SystemVerilog Technical Seminar - Axis Systems, Mentor Graphics, Novas Software, and Synopsys are jointly sponsoring a free SystemVerilog technical seminar and product demonstrations in four North American locations beginning October 8, 2003. Each seminar will be presented by Cliff Cummings, President of Sunburst Design, Inc. and noted Verilog design expert. Seminar organizers say the “SystemVerilog NOW!” technical seminars will provide design and verification engineers with practical and up-to-date information about SystemVerilog's capabilities and demonstrate how they translate into increased productivity and silicon success using design and verification tools
SystemVerilog today. If you're lucky enough to be in Austin on October 8th, Santa Clara on October 22nd, Boston on October 29th, or Ottawa on November 12th, you'll be able to catch Cummings' presentation. (
Synplicity Seminar - Entitled “Lowering the Cost of ASIC Verification” and offering “solutions to the most pressing problems of an ASIC designer” (No, this is not a seminar on Dress-for-Success for the Single Guy), this half-day event will be happening multiple times, October 16th in Sunnyvale, CA, October 28th in Westford, MA, and October 29th in Columbia, MD. You should be planning to attend if you're interested in “The Verification Zone,” implementing your ASIC design into a multi-FPGA prototype, and building debug access into your RTL source code. Satisfied Synplicty customers will be demo-ing use of the company's products. Breakfast is
SAME 2003 - This event is described as the “6th Edition” of the forum on MicroElectronics, taking place in Sophia Antipolis, in the south of France, on October 8th and 9th. Organizers say it will offer an “exceptional venue for discussions and demonstrations with the opportunity to meet exhibitors displaying microelectronics related products.” The emphasis is on tutorials rather than technical papers, and two very controversial panels - one on SoC/IP and one on Design Methodologies - are promised to those who come. Most intriguingly, a “very attractive dinner debate” between the general managers of Sophia Antipolis' major semiconductor companies
will offer differing perspectives on
the wireless industry. Hopefully the “attractive” part refers to the fine French wines, which will accompany the meal. Perhaps an “attractive” Guigal Cote Rotie 1989, but tastes may differ in this area. (
SOPC World 2003 - System on a Programmable Chip 2003 is Altera's global annual design conference that the company says brings together system architects, designers, and manufacturing executives from around the world to learn about the latest applications, features, and benefits of using programmable logic technology. The company says this year, if you come, you'll see detailed technical sessions and hands-on demonstrations - importantly with no charge for attendance. Topics include developing custom peripherals and instructions for embedded programmable processors, using advanced FPGAs to solve high-speed design, signal integrity, and board layout challenges, using FPGAs to simplify
high-speed memory interfacing and control, and implementing DSP functions in FPGAs for greater performance and lower cost. Naturally Altera products will be front and center, but if you're still bringing yourself up to speed on programmable devices, you should be planning to attend nonetheless. The conference is happening across a plethora of locations from late September through mid-November. (
X-FAB Lunch & Learn Seminar - Organizers says the seminar will cover the challenge of design and testability of embedded non-volatile memories and ESD protection methods for mixed-signal and high-voltage designs, October 7th in Irvine, CA, and October 8th in Santa Clara, CA. Holger Haberla will talk about “IC-Design and Testability of Embedded EEPROM and Flash Memory Options in mixed-signal Environments” and Cornelia Foss will address "Enhanced ESD Protection Methods for mixed-signal and high-voltage Designs." The event is free, so why not plan on attending. (
Cadence Design Systems, Inc. says it will join with Russian education and industry leaders to mark “key milestones for a Cadence-sponsored master's program centered on analog/mixed-signal SoC design at the Moscow Institute of Electronic Technology (MIET). The event, which will be held at MIET, will focus on progress made with the International Institute of Device and System Design, a program begun last year to develop curriculum for and train Russian engineering graduate students seeking an MSEE. MIET Rector.
Yuri Chaplygin and Spencer Clark, Cadence Vice President and Chief Learning Officer, will be among the officials offering remarks. Milestones achieved thus far include the following: all 23 remaining students from the initial class are beginning their final term and are working in Russia as part of their study programs, all have post-graduation job offers, the two-year, four-term MSEE curriculum in analog/mixed-signal design has been completed, 27 students have been selected through a competitive process for the second class and began their first term on Sept. 1.
Cadence says the foundational program is designed to benefit Russia's high-tech industry and community by developing a “continuous stream of master's degree graduates highly knowledgeable in analog/mixed-signal design.” The International Institute of Device and System Design is one of several global initiatives by Cadence and the second in Russia. It offers 24 technical courses as part of a comprehensive two-year MSEE curriculum. Many of the students are expected to move on to positions with international technology companies operating in Russia. The program is
administered by Mirantis Inc., a company based in Foster City, CA. Cadence donated computer equipment and software licenses, instructor funds and student stipends, and provides technical guidance and training.
Mentor Graphics Corp. announced that Avnet Cilicon has joined its FPGA Advantage Solutions Thrust (FAST) Partner Program. The company says that through the FAST Partner Program, Avnet Cilicon will receive access to Mentor Graphics' FPGA design tools, methodologies, and training and can serve as a certified Mentor Graphics design resource to customers implementing FPGA design.
Open Core Protocol International Partnership (OCP-IP) and Silicon Integration Initiative (Si2) have announced memberships in each others respective organizations, saying that mutual memberships will allow the industry organizations to collaborate more closely and gain a greater awareness of the direction for each organization. Both organizations say they believe working together will increase awareness in the design community, while at the same time illustrating and strengthening the belief that open technologies are the wave of the future.
Steve Schulz, President of Si2, is quoted in the Press Release: “While Si2 is currently focused on the overall design flow, OCP-IP supports those same goals by standardization of SoC IP interfaces. Collaboration by both organizations will greatly benefit the industry as a whole.”
Meanwhile, Ian Mackintosh, President of OCP-IP, is quoted: “As the only truly open, fully supported industry standard socket, it is important that OCP-IP enter relationships such as this; that facilitate improved collaboration, helps us communicate to our memberships and thus better serve industry interests. We look forward to working with Si2 in the future.“
The VSI Alliance (VSIA) announced a strategic alliance with the Fabless Semiconductor Association (FSA), the purpose of which according to the two organizations is to accelerate the adoption and rollout of the VSIA Quality IP (QIP) Metric, and to further extend it to accommodate hard IP including silicon verification. The work extending the QIP Metric will be done jointly in VSIA's Quality Development Working Group (DWG). Under the agreement VSIA has established a Hard IP sub-DWG within the Quality DWG and appointed Vin Ratford, FSA member and Chairman of the IP Education Working Group of the FSA's IP Committee, as Chair of the new sub-DWG. The FSA will also provide resources
the sub-DWG to assist in developing the Hard IP extension for the VSIA QIP Metric.
The FSA and VSIA say they expect to have the Hard IP extensions in place within 12 months. Members from both organizations will have free access to the VSIA QIP Metric for Soft and Hard IP. The FSA and VSIA will be promoting the use of the Metrics as they become available to their members. The FSA will also create and lead an additional working group focused on the rollout of the QIP Metric to the fabless community. VSIA members will be invited to join this group. At the same time, VSIA will create and lead a QIP Adoption Group that will focus on technical issues of adoption including tools to automate the process of generating and verifying the final score. FSA members will be invited to
join the QIP Adoption Group.
VCX Software, Ltd. announced that it has been incorporated as a privately held entity, formally acquiring all assets of the Virtual Component Exchange (VCX), including the IP portal www.thevcx.com, the underlying technology, expertise, and staff of VCX. The new company says its corporate structure and name reflect the company's focus as a commercial, integrated software provider for the EDA industry. The previous entity was funded in part by Scottish Enterprise and in part by a large group of private companies, and created and managed an on-line IP listing and exchange service.
The new company says its business model will include client-server based software tools, web-service packages, and data services that will improve time to market and the costs of IP for providers and semiconductor foundries. Simon Davidmann, founder and president of Co-Design Automation, has been named as Chairman of the Board. Andy Travers will be CEO, Thierry Marcelis will be COO, and Pat McTaggart will be CFO.
I had a chance to talk briefly by phone with Andy Travers about the announcement. His comments were wrapped in a brilliant Scottish accent: “VCX was formed five or six years ago and designed to be an exchange for buyers and sellers of IP. The buyers could browse listing and use templates for acquisitions of IP - the whole thing was backed by the Scottish Government.”
“But we've changed [that model]. Now we're privatized and have acquired all of the assets of the old VCX. We're no longer focused on being a central repository for IP, and are working instead on custom solutions for both buyers and sellers. This is a very big change for us that comes out of necessity and natural evolution. The necessity arises from the paranoia and fear of those providing IP, which affected the success of a central IP exchange. We realized a year or so ago, that people wanted a different type of IP exchange environment. We had started to work with companies for custom
solutions through web facilities, the packing and transferring of IP between companies. Those companies started feeding back to us that they preferred that we be a strictly commercial entity. You would think they would have wanted to get something for free through a government-sponsored entity, but the customers actually preferred that we be motivated by money and not by [what they were concerned might be] hidden government agendas. This conversion to a privately held company was essential for some of our more serious customers.”
In the category of ...
'Camp EDAC Accord' hints at possible Nobel Peace Prize
Cadence Design Systems, Inc. and Mentor Graphics Corp. announced that they have agreed to settle all outstanding litigation between the companies relating to emulation and acceleration systems. The companies also announced an agreement that, for a period of seven years, neither will sue the other over patented emulation and acceleration technology. (Perhaps of greater or lesser importance, Mentor has also announced it will pay Cadence $18 million in cash.)
In addition, the companies said that an immediate customer benefit of the agreement is that Mentor will now join Cadence in the OpenAccess Coalition, sponsored by Si2.
Meanwhile, in the spirit of the moment, Ray Bingham, President and CEO at Cadence is quoted in the Press Release as having said: “Healthy competition yields better technology platforms and results for our customers; chronic litigation does not. While it will always be important for us to protect our intellectual property, right now our customers, who face a continued weak economy and unprecedented challenges in chip design, need our undivided attention.”
Not to be outdone in the area of Collegiality and Magnanimity, Walden C. Rhines, Chairman and CEO at Mentor Graphics, is similarly quoted in the same Press Release: “We are pleased to have settled this litigation in a fair and reasonable manner. Helping customers keep pace with the growing complexity of today's SoC and ASIC designs is our overriding objective, and the end of this litigation will help us achieve that aim.”
All joking aside
Kudos to Cadence Design Systems for donating $675,000 to the new Georgia Travis Center for Women and Children in San Jose, CA. Originally opened 10 years ago at a site a few blocks from the new location, the Georgia Travis Center had outgrown its capacity. With the help of the donation from Cadence, raised at the Cadence Stars & Strikes bowling fundraiser last year, InnVision was able to purchase and renovate a large warehouse for a working facility that provides 10,000 more square feet for counseling, children's programs, dining, laundry/showers, classrooms, a computer lab and a dedicated medical exam room. The new facility will serve over 5,000 people per year.
The numbers are in
EDAC's Market Statistics Service announced that the EDA industry revenue for the second quarter of 2003 was $946 million, an 8 percent increase over $876 million in Q2 2002. EDAC says this is the second consecutive quarter of sequential revenue growth and that Q2 2003 was also the first quarter to show positive revenue growth (compared to the prior year's quarter) since Q4 2001. Consortium Chairman Wally Rhines said, “We are very encouraged to report a return to revenue growth for the EDA industry in Q2. Second-quarter growth was strong enough to lift year-to-date revenue to $1,854 million, one percent higher than the $1,837 reported in the first half of 2002.”
You can find the full EDACafe event calendar here
To read more news, click here
-- Peggy Aycinena, EDACafe.com Contributing Editor.