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March 15, 2010
Static Timing Analysis Is Not Staying Static
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Gabe Moretti - Contributing Editor

by Gabe Moretti - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Static timing analysis (STA) has been around more than 30 years. However, in the last fifteen years its importance has grown to the point that it has become an essential step in the design of digital circuits.

Initially STA was used to find hold and setup violations in the clock tree, due to logic errors by designers. Then as silicon geometries became smaller and smaller, circuit topology also needed to be taken into consideration. Logic circuits that seemed safe in theory, would at times experience glithches in signal transmission due to marginal clock distribution issues. The use of STA tools then became a required step in the certification of circuitry before producing a final tapeout.

As fabricated geometries shrank below the 90nm process node, the use of multiple clocks became a general approach to partition the design into both functional blocks and power distribution and use segments of the design. Cross talk and other sources of noise, which at best had always been second order effects, must now be taken into consideration in verifying and certifying an IC before release to manufacturing. STA is not only required, but the tools themselves must be more powerful and more complex, as they take more physical effects under consideration, deal with multiple clock trees, and handle much larger designs.

Over the last five years or so a few sign-off advancements such as composite current models (CCS) models, distributed multi-mode/multi-corner (MM/MC), and location-based on-chip variation (OCV) analysis have been incorporated into sign-off flows. Bigger design teams, bigger machines and more complicated analysis have also been leveraged to handle the increasing design complexity enabled by advanced process nodes.

While the STA timing analysis flow (load design, load constraints, load parasitics, update timing graph, produce timing reports) essentially remains the same, the combination of design complexity and the amount of analysis required for advanced technology nodes has raised the stakes for STA. As instance counts continue to double, the number of clocks is growing. Wading through multiple timing reports and evaluating the timing closure status and/or strategy can be exhausting.

Statistical STA (SSTA) was introduced with the intention of adding statistical variation analysis to the traditional STA-based sign-off flows. Using statistically-created libraries, designers can evaluate their design's susceptibility to variation. At 65 nm, traditional sign-off continued to produce working silicon using PVT-based sign-off and margins (OCV). At 40 nm and below, design teams are taking another long look at SSTA as a potential solution for improving yields and reducing timing analysis.

Sign-off tool capacity requirements are a major and costly problem for teams and the problem is exacerbated by the fact that the number of timing scenarios is doubling or tripling with each generation. At 28 nm, it becomes nearly intractable because 50 scenarios will be required for mainstream designs. To address this problem the only alternative has been to use more sign-off tool licenses and more hardware. Designers can run MM/MC timing analysis provided they have a sufficient number of STA licenses and number of machines. This drives costs and budgets up and runs exactly counter to the concept of a solution that qualifies as better.

With growing demand for consumer and hand-held products, IC designers need to reduce dynamic and static power to maximize battery life. Adoption of advanced technology nodes enables higher performance cells, more density per square millimeter and lower power. For the high-volume ICs targeted at hand-held devices, power requirements are more important than performance and many advanced power management techniques are used to minimize power.

As low power requirements drive supply voltages down below the 1V threshold, design teams have observed that standard delay models will not sufficiently address process variation. At 28 nm, transistors operating under 1V exhibit strong delay nonlinearity with respect to PVT parameter variations.

One viable solution for low-voltage 28-nm designs is to complement traditional corner-based STA with a statistical timing engine that supports nonlinear delay distributions. SSTA can be used to obtain an accurate estimate of design performance while limiting the number of timing iterations.

Designers, to be sure that a circuit will have acceptable yields and will executed as expected in the product, need advanced STA tools. Unfortunately the tools often require long execution times, even with expensive high end computing platforms. This is a major problem for companies trying to keep development costs as low as possible. They must contend not only with the non recurring cost of the computing machinery, but also, more importantly, with the time required between executions. With every design change, designers need to wait for the tool to finish executing, then they must analyze the results, make changes, perform another place and route function, go through circuit parameters
extraction and then run STA again.

The Latest Entry

A few days ago Magma Design Automation announced its new timing analysis product: Tekton. For those who like to know where the name of the product came from, I can offer two origins. The word "tekton" is a Greek word that means "one who constructs", and thus Magma is saying that this product will help designers construct their IC. But, sticking with the geological nature, typically volcanic, of Magma's products, tekton is the Greek root of the English word tectonics, and can be found as a proper name to describe plate tectonics, the origins of earthquakes. Thus the product name would fall into the Magma family tree.

The company says that unlike other solutions, Tekton runs multi-scenario analysis efficiently on low-cost hardware without requiring a large number of expensive servers and software licenses. Leveraging breakthrough technology, this new platform addresses complex sign-off challenges and is suited for today's most challenging designs.

"The complexity of timing sign-off has reached crisis proportions, forcing design teams to re-evaluate resource planning, design architectures and final sign-off solutions," said Premal Buch, general manager of Magma's Design Implementation Business Unit.

Tekton has been designed to perform both parameter extraction and circuit analysis using parallel execution architecture, whether on single or multiple CPU machines. Taking advantage of the experience accumulated in STA applications over the years, Magma has been able to design a tool that addresses today's problems with today's architectures and algorithms. The company claims that the new product was designed to more efficiently handle on-chip-variation (OCV), composite current source (CCS) models and crosstalk analysis. The Tekton platform includes Tekton QCP. Its architecture enables multi-corner extraction with small increases in runtime as additional process, voltage and temperature
(PVT) corners are added for each process node migration. Tekton and Tekton QCP can be used together in a single STA timing session.

To address the timing closure challenges design teams face at 40 nm and below, Tekton supports advanced OCV (A-OCV) margin reduction techniques. By incorporating A-OCV into timing closure flows, design teams can minimize global pessimistic margins that lengthen tapeout schedules and potentially increase die sizes. For critical path and net analysis, Tekton and Tekton QCP offer high accuracy modes that leverage Tekton's integrated SPICE engine and Tekton QCP's accurate extraction.

Magma has stated that Tekton and Tekton QCP used together produce results that are as accurate as Synopsys' Prime Time but use less computing resources while, at the same time, decreasing the Engineering Change Order (ECO) cycle by a factor of ten.

The Gold Standard

Magma's, as well as all other vendors', reference to Prime Time is a recognition that the Synopsys tool has been considered the Gold Standard STA tool in the industry almost since its introduction. The company has kept up with the increasing demands of more and more complex designs by expanding the original tool into a suite of products that now includes PrimeTime, PrimeTime SI, PrimeTime PX and PrimeTime VX. The tools in the suite take advantage of Synopsys HSPICE accuracy in circuit analysis.

In order to address the explosion in the number of scenarios which need to be verified, Synopsys introduced Distributed Multi-Scenario Analysis (DMSA) capability in Prime Time. DMSA allows designers to set up, distribute, run, and perform ECO fixes simultaneously across multiple scenarios, thereby reducing overall turnaround time.

Time-to-market pressure, chip complexity, and control of SI effects are all factors requiring an accurate, fast, and trusted analysis and signoff solution. With shrinking process geometries and rising clock frequencies for nanometer designs, signal integrity (SI) effects such as crosstalk delay and noise (or glitch) propagation can cause functional failures or failed timing. It is essential for designers to address these SI problems to ensure that their designs are delivered to market correctly in the shortest amount of time. PrimeTime SI extends Prime Time capabilities by adding accurate crosstalk delay, noise (glitch), and voltage (IR) drop delay analysis to address signal integrity
effects at 90-nm and below.

The expansion of the market for portable devices, as well as the shrinking geometries of IC have elevated power consumption to great importance. The PrimeTime PX solution expands the PrimeTime timing and signal integrity environment to perform dynamic and leakage power analysis for design geometries at 90-nm and below. Synopsys aims to provide designers with a single, unified analysis environment for timing, signal integrity and power analysis anchored by the PrimeTime static timing solution.

For example, netlist, parasitic and constraint file reads, and tool setup steps are not repeated. As a result, the PrimeTime PX solution delivers up to two times (2x) faster time-to-results (TTR) over separate, standalone solutions.

PrimeTime VX is an SSTA tool. It extends the PrimeTime environment to analyze device and interconnect variations at 65-nm and below using statistical techniques. Variation-aware analysis with the PrimeTime VX solution delivers improved margin control, avoiding the over- and under-design of circuits. Design robustness is improved by pinpointing areas of the chip most susceptible to variations so that designers can reduce this sensitivity and improve the parametric yield of production chips.

PrimeTime VX analyzes systematic or deterministic process variation (die-to-die) as well as random process variation (on-die) in a flexible environment. PrimeTime VX uses a Monte Carlo algorithm that, according to the company, is very efficient and keeps run time to the minimum. By the companies own statements, both Extreme DA and Magma are aiming at replacing PrimeTime in existing deployed installations. They both have stated that the results from their respective products are equal to those of Prime Time. To my knowledge Synopsys has not publicly contested those claims.

Other STA tools

Gary Smith's Wallcharts (available in electronic format at www.gabeoneda.com), provide a database of EDA tools divided by application areas, that are easily searchable by designers. In the segment that lists Timing Analysis tools, Gary lists the following vendors in addition to the two already mentioned: Apache, Cadence, Extreme DA, Incentia Design Ssystems, Mentor, Prolific, and Simucad. To give a better picture of the state of this market segments, it is necessary to briefly describe the products of each of these vendors.

Apache Design Solutions

Although Apache is better known for its power analysis tools, it also offers a timing analysis solution, since power and timing are now closely correlated. At 130nm and above, noise caused by signal crosstalk had the most impact on the chip's performance, whereas at 90nm and below, noise caused by dynamic voltage drop became the main contributor. Now, at 65nm and beyond, both crosstalk and power supply noises are impacting the chip's performance. And since from a device perspective, it is not possible to distinguish whether the noise is caused by crosstalk or dynamic voltage drop, the solution must be able to understand both signal and power supply noise concurrently.

According to the company's description "RedHawk-PSI is a full-chip clock network integrity (jitter) and critical path timing signoff solution for high-performance nanometer designs. It considers the concurrent and interdependent effects of power and signal integrity on clock jitter and critical path timing. Certified by TSMC's Reference Flow, RedHawk-PSI delivers cell-based ease-of-use and performance with true Spice accuracy."

RedHawk-PSI is a dynamic solution, an SSTA, with critical path analysis that is based on real waveform simulation versus a linear approximation. It uses actual Vdd/Vss instance waveforms rather than effective Vdd/Vss approximation of instance supply voltages. The tool represent the effects of dynamic voltage drop and ground bounce on timing by performing dynamic transient analysis of the full-chip power grid and generating dynamic voltage drop waveforms for each instance in the design.

Engineers can obtain standard-cell capacity with a SPICE-accurate simulation of clock tree networks and critical paths, including all the nanometer and high-speed effects, such as crosstalk and dynamic voltage drop. RedHawk-PSI utilizes a true-Spice simulator with proprietary BLSN (big linear, small non-linear) technology to accelerate the solving of networks that have an enormous number of linear elements, and a smaller number of non-linear elements.

Cadence Design Systems

Cadence is one of the very few vendors that offer all the tools required by designers to progress from design implementation to release to a silicon fab. Cadence's timing analysis capabilities are integrated in the company's Encounter family of products. The company states that "with Encounter Timing System, designers benefit from a consistent, integrated, multi-CPU enabled, static timing analysis (STA) environment for place-and-route optimization and signoff verification, leading to faster design closure and better flow convergence." The tool can also be purchased separately, but seems to have been designed to be an integral part of the Encounter Digital Implementation System.

The Encounter Timing System helps designers analyze and debug multimillion-gate designs. Global timing debug pinpoints the root cause of timing and constraint issues at the push of a button. Sophisticated delay calculation ensures accuracy and performance. The tool uses the effective current source model (ECSM) for advanced timing, power, signal integrity (SI), and statistical delay modeling.

Extreme DA

This vendor focuses almost exclusively on timing analysis tools. Its product is called GoldTime. The company literature and web site state that "it is capable of running nominal, statistical, Monte Carlo, and SPICE analyses on the full design or any part of the design."

Recognizing the position that Prime Time enjoys in the market, GoldTime is SDC compatible and presents results in the PrimeTime environment. The portion of the tool called GoldTime Analysis performs timing and clock tree analysis. It further calculates the effect of process variation on crosstalk noise and delay. GoldTime Analysis computes variation sensitivities for each cell. Variation sensitivities are the mathematical models for measuring the cell's contribution to yield or clock skew and a key technology driving the statistical optimization engine.

Another component called GoldTime Optimization does post-layout optimization to meet more aggressive constraints and improve design robustness. The company states that "conventional optimization flows based on worst-case corner models tend to push the design to unrealistic performance, causing significant wastage in area and power consumption. GoldTime optimization takes advantage of modeling and analysis capabilities to achieve optimal balance between the performance yield target and power and area requirements."

The product uses a technology called "ThreadWave" that allows the analysis to proceed along a virtual wavefront through the design, and capacity requirements grow sub-linearly with an increase in design size. As only the wavefront consumes system memory, GoldTime with ThreadWave technology can analyze the largest flat designs.

From an execution throughtput point of view, the company claims that on a single CPU workstation, GoldTime demonstrates up to 5X better speed and capacity than current timing analyzers (obviously not including Tekton). On multi-processor workstations, the speed improvement scales with the number of processors.

Incentia Design Ssystems

TimeCraft is Incentia's high-speed, big-capacity, static timing analyzer (STA) for nanometer timing analysis and sign-off. It is the base product of Incentia's complete timing solution offering, including signal integrity (SI) analysis, power analysis (PA), statistical static timing analysis (SSTA), and constraint management (CM).

As with other tools in this market segment, it is compatible with Prime Time. it uses a multi-threaded technology to improve execution time and claims a highly efficient multi-task MM/MC allowing for analyzing more corners in significantly less time while minimizing the use of memory.

Mentor Graphics

The Mentor Graphics timing analysis solution is integrated in its Olympus-SoC IC implementation solution. This flow is highly focused on power analysis, but, of course, includes timing analysis capabilities.

Olympus-SoC provides concurrent optimization for both power and timing, covering all operating modes and process corners through all stages of the flow. It automates multi-supply-voltage design flows with automatic power grid routing for multiple voltage supplies, support for Dynamic Voltage and Frequency Scaling (DVFS) to handle varying supply voltages and clock frequencies, and auto placement and routing of special cells such as level shifters, isolation cells, and MTCMOS switches. Olympus-SoC also provides concurrent multi-Vt optimization, power gating, retention flop synthesis, support for gas station methodology, and power-aware buffering and sizing

To reduce dynamic power, Olympus-SoC provides automatic power-aware clock tree synthesis (CTS) with smart clock gate placement, slew shaping, register clumping and concurrent multi corner multi mode (MCMM) optimization, with the goal of ensuring a balanced clock tree with the minimum number of clock buffers.

Olympus-SoC supports the Unified Power Format (UPF) throughout the netlist-to-GDSII flow, including the ability to describe design intent through power state definition tables.


Unlike most of the products from the other vendors covered in this article, Prolific's ProTiming is a tool designed to work with Synopsys Prime Time. Unlike other optimization tools, which modify RTL, the standard-cell libraries, or placement, ProTiming is a final-pass solution that is run on a "completed" design. ProTiming runs Synopsys' PrimeTime to measure performance. ProTiming performs design-specific timing optimization during the static timing analysis step of the physical design flow. The software makes use of cells already existing in the library and can provide a 5-10% performance increase without modifying RTL or adding new cells to the library. If desired, ProTiming can also
specify new cells that are created as needed, either by traditional methods or automatically by Prolific's ProGenesis tool suite, for an additional 5-10% performance increase.

The result before and after the final pass timing optimization are consistent with the Prime Time results, since the RTL has not been modified. In conjunction with PrimeTime SI, ProTiming also fixes signal integrity problems and removes hold time violations. Improvements are gained in addition to any optimizations that were made earlier in the design process. ProTiming minimizes the impact of its changes on the design, and produces a change file for an ECO, if required.

ProTiming also supports a more aggressive approach; ProTiming will replace all cells after STA with low L (low power) or half drive strengths, then fix timing by increasing the drive strengths only in the critical paths required to meet timing. The company claims that this methodology results in power savings of up to 20% or more.


Simucad's AccuCore is not a traditional STA tool, and, just like ProTiming does not aim to replace Prime Time or any other full circuit STA tools. AccuCore is a block characterization and modeling tool that uses STA techniques to achieve the following goals.
  • Generates Synopsys' Liberty (.lib) timing models, generates a gate-level verilog netlist and generates or reads DSPF files for STA
  • Exports fully sensitized SPICE deck for selected critical paths and clocktrees with measurements
  • Automatically partitions blocks into cells
  • Automatically extracts cell functions and generates vectors required for accurate SPICE characterization
  • Includes fast API-based SmartSpice characterization engine
  • Complete block and full-chip gate-level STA environment for rapid bottleneck analysis and timing verification.
  • Conclusion

    Ever since the beginning of the EDA industry, tools developers have had to trade off accuracy with execution speed. Low execution speed means that designers are idle while waiting for results in order to fix bugs or improve the quality of the design. Lower accuracy may mean that a circuit which is thought to be good will either not have good yields or have functional faults. Although in the previous century market conditions could allow companies to accept slower execution speeds in favor of accuracy, today consumer driven markets make this choice unrealistic.

    The penalty for not being first in the market, or for missing the optimum release date, often means the loss of million of dollars. Tools must be both accurate and fast in order to keep development time to a minimum. Unfortunately for EDA vendors, circuit sizes continue to increase, and smaller process geometries increase the complexity of the analysis by requiring designers to consider more and more parasitic effects that can negatively impact the performance of their circuits.

    Credit must be given to EDA vendors for continuing to improve the tools to meet the new challenges. It is unfortunate that the EDA industry has not yet found a way to generate profits commensurate to its contribution to the semiconductors and entire electronics industry.

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    -- Gabe Moretti, EDACafe.com Contributing Editor.

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