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July 20, 2009
DAC: A Standing Ovation for All …
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Let’s give a standing ovation for all of the hard-working folks putting together DAC this year. Late July is a hellish time to be trying to mount a tech conference in one of the most expensive cities in the U.S. – particularly in the midst of the worst recession in decades.

If you’re on the Executive Committee (that‘s you, Andrew, Sachin, Patrick, Narendra, Yervant, Limor, Dennis, Greg, Soha, Leon, Nanette, Georges, Kazutoshi, Diana, Ramesh, and Anne), stand up and take a bow!

If you’re working for MP Associates (that‘s you, Kevin, Lee, Susie, Nannette, Kathy, Regina, Marie, Pat, and staff), stand up and take a bow!

If you’re chairing a Workshop or a Tutorial, and you’re a’feared it will be under-attended, but you’re persevering nonetheless, stand up and take a bow!

If you produce the DACeZine (that‘s you, Gabe and Nanette), stand up and take a bow!

If you’re hosting the Denali party (that’s you, Sanjay), stand up and take a bow!

If you’ve contributed Big Bucks to facilitate a free Exhibition Hall all week long with the fabulous
DAC Fan Club (that’s you, Scott, Sanjay, Ajoy, and your respective teams), stand up and take a bow!

If you work for EDAC (that’s you, Bob, Jennifer, and Paul), stand up and take a bow!

If you’re giving a keynote (that’s you Wally (x2), Aart, and Lip-Bu), stand up and take a bow!

If you’re paying tens of thousands of dollars (or orders of magnitude more) to exhibit at DAC, even though you’re not sure you can afford it (that’s too many of you to name), stand up and take a bow!

If you’re laboring to prepare Press Releases in a last manic rush just before the show (that’s all of you out there in PR and Marketing), stand up and take a bow!

If you’re leaving early, getting home late, and losing sleep trying to figure out if you’ve done everything you should’ve and could’ve done to make it all a success for your committee, your company, your organization, your publication, your reputation, and/or your bottom line, at the expense of time with family and friends (and that’s pretty much all of you), stand up and take a bow!

And, if you’re not on this list, but should be and can’t believe I forgot to mention you, stand up and take a bow!

I salute you and look forward to congratulating you in person next week in San Francisco. I’ll see you at DAC, and please know that if you can’t be there, you will be missed!


Additional events of note at DAC …

Things I will add to my hope-to-attend list at DAC. I’ll post the complete list later this week in
Thursday’s Child.

Monday, July 27

* North American SystemC User Group (1 pm)

* Atrenta Booth Blogfest & Panel Discussion re: Early Design Closure (2 pm)

Tuesday, July 28

* Accellera Breakfast - Scott Sandler moderating (7 am)

* SystemC & TLM-Driven Design Replacing RTL? Lunch Panel (11:30 am)

* Interoperable PDK Libraries (IPL) Workshop &Lunch: “The EDA Earthquake” (12 noon)

* User Track: Verification (4:30 pm)

* Accellera-SPIRIT Reception celebrating the new combined organization (6 pm)

Wednesday, July 29

* User Track: Timing Analysis in the Real World (9 pm)

* User Track: Poster Session & Ice Cream (1:30 pm)

Thursday, July 30

* User Track: Analog & Mixed-Signal Design (4:30 pm)


It’s a Blog, Blog, Blog, Blog World …

Celebrating Natural Selection in EDA

More than ever today, customers are holding their EDA vendors accountable for the ROI of the tools. Time-based license renewals are being heavily scrutinized and, as discretionary tool purchases have all but evaporated, it falls to the EDA suppliers to respond.

The Top 10 Must-Do’s at DAC

No. 3 – TSMC has just joined Si2, but is not yet a member of EDAC, although The MathWorks is. Figure out when TSMC will become a member of EDAC.

Semicon &Wally Rhines

A lot of people were at Semicon this week in San Francisco. Organizers were said to be expecting 25,000 for the 38th Annual Gathering of the Global Semiconductor Ecosystem, but clearly not everybody showed up.

ASQED: Get Three to Kuala Lumpur

Cool stuff’s happening next week in Malaysia as ASQED, the debut edition of Asia ISQED, unfolds in Kuala Lumpur on July 15th and 16th.

IC Manage & Europe - Back to the Future

Once again, bright entrepreneurs are working to deliver on the promise of web-based design, project management, tool evaluation and sales.

The ESL battle for hearts and minds

If you plan to start designing at higher levels of abstraction, and you're probably going to have to soon, best to figure out ESL on your own — in private contemplation away from the hue and cry of today's principle vendors.

Power and Verification AlwaysMatter

One day I turned around and found Verification Methodology Manual for Low Power sitting on my desk.

MIA: Women in EDA

The question is not where have all the women technologists gone. The question is, were there ever any women technologists at these conferences in the first place?

GQ at DAC: The Studelicious Report

A secret panel has been convened to spot the Best Looking Guys at DAC. Why? The better question is, Why not? Details to follow in EDA Confidential.


The Twitter Project …

EDA Luminaries profiled to date:

E.Kuh, R.Kahn, MJ.Irwin, I.Markov, J.Jess, J.Hogan, S.Srivastava, S.DasGupta, J.Ousterhout, D.Patterson, S.Devadas, R.Rohrer, C.Huang, R.Newton, J.Bourgoin, J.Hennessy, J.Kibarian, R.Bryant, G.DeMicheli, R.Brayton, B.Sutherland, I.Sutherland, C.Sechen, P.Narain, H.Walker, J.Benkoski, S.Hailey, K.Hailey, L.Nagel, D.Fairmairn, R.Saleh, J.Solomon, D.Pederson, L.Conway, S.Levitan, B.Aronson, W.Sansen, G.Martin, S.Sapatnekar, A.Kuehlmann, G.Gielen, G.Delp, D.Gajski, R.Aitken, H.DeMan, J.Costello, M.Wong, P.Groeneveld, A.Sangiovanni-Vincentelli, T.Williams, R.Dutton, Y.Zorian, S.Hassoun, L.Stok, K.Cheng, A.Shubat, D.Pan, J.Rajski, K.Keutzer, A.deGeus, L.Pileggi, C.Rowen, W.Wolf, A.Yang,
J.Rabaey, R.Camposano, D.Sylvester, L.Lanza, C.Mead, P.Moorby, S.Mitra, J.Darringer, W.Rhines, J.Cong, J.Sanguinetti, A.Kahng


Money matters …

* Azuro announced “record sales and revenue for the first six months of 2009.”

* EDAC Market Statistics Service announced EDA industry revenue declined 10.7% in Q1’09 to $1.192 billion, compared to $1.334 billion in Q1’08, “driven primarily by an accounting shift at one major EDA company. EDAC Chair Wally Rhines is quoted: “Q1 EDA revenues [declined] in all regions except Asia Pacific.” Companies that EDAC tracks say they employed 26,561 in Q1 2009, down 2.8% from the 27,329
employed in Q1 2008, and down 2.7 percent from the 27,311 employed in Q4 2008. That means there was only a net loss of 18 jobs in all of 2008. That seems confusing and/or inaccurate, somehow.


People matter …

* ACM and IEEE announced the first recipients of the A. Richard Newton Technical Impact Award in EDA are Robert Brayton, Richard Rudell, Alberto Sangiovanni-Vincentelli, and Albert Wang for their 1987 paper: “MIS: A Multiple-Level Logic Optimization System,” published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

* CebaTech announced Joe Rash has been named VP of Business Development & Marketing. Previously, he served in executive roles at Qimonda and Nortel. He began his career at IBM Corporation where he developed ASICs, firmware for communication co-processor adapter cards and ATM switches and routers. Rash is co-author of 7 patents, and has a BSEE from the University of Central Florida.

* EDAcon announced consulting services to EDA companies, including a worldwide network of distributor. The company is headed up by Verisity alum, Coby Hanoch.

* The MathWorks announced three new offices in Tokyo, Nagoya, and Osaka, Japan, which the company says “reflects its transition to a direct sales operation in that country.”

* Mentor Graphics announced they’ve engaged Trident Techlabs as a distributor in India.

* Mephisto Design Automation announced it’s joined the Interoperable PDK Libraries Alliance (IPL).

*Oasys announced its arrival on the EDA Scene, led by a bevy of EDA heavy hitters. Paul van Besouw is President/CEO, and the Board includes Joe Costello, Sanjiv Kaul, and Larry Yoshida. If you do not know who these folks are, you haven’t been in EDA long enough.

* The Open Virtual Platform celebrated its one-year anniversary. Founded by Imperas with “the help of 18 companies and individuals from the embedded systems user community, processor IP developers, EDA, service providers and academia … OVP technology provides solutions to the problems embedded software developers incur when modeling the multi-core SoC that hosts their software. [In the past year], more than 1,200
individuals have registered on the OVP website with more than 8,000 downloads of models and tools.”

* Si2 announced its Board: Cadence’s Charlie Huang, AMD’s Ward Vercruysse and John Goodenough; IBM’s Leon Stock, Intel’s Rahul Goyal, LSI’s Ameesh Desai, National Semiconductor’s James Lin, NXP’s Barry Dennington, Sequence Design’s Vic Kulkarni, and
Synopsys’ John Chilton.

* Syntill8, “experts in 8-bit microcontroller IP,” announced a reseller agreement with Mentor Graphics.

*TSMC announced that Board Chairman Morris Chang has been selected to serve as CEO of the company, as well. In addition, Rick Tsai has been named President of TSMC’s New Business Development Organization.

* Tuscany Design Automation announced Keith Mueller has been named President & CEO. Previously, Muller was VP at Apache Design Solutions, VP at Silicon Perspective, and VP at Anagram. He also served in a management capacity at Quickturn, Silicon Compilers, Quantum Corp, and National Semiconductor.


Places matter …

* IEEE SF Bay Area Nanotech Council is having their Tuesday lunch on July 21 at National Semi in Santa Clara. This time it’s co-sponsored by AICE (the Chemical Engineering guys) and covers “Synthesis and Applications of Carbon Nanotubes and Nanofibers.”

*ARM DevCon says you’ve got until July 28th to submit papers for consideration. The Conference takes place in Silicon Valley on October 21-23. Will you be able to get there? If so, maybe you should be presenting.

* ISQED 2010 says you’ve got til September 29th to submit your paper ideas for the March 22-24, 2009, conference in Silicon Valley.

* Hot Chips will be happening at Stanford August 23rd to 25th.

* Hot Interconnects will be happening in New York City August 25th to 27th.

* SAME 2009 is happening in Sophia Antipolis September 22nd & 23rd.


But Things matter most …

* Aldec announced a low-cost mixed language RTL simulator, Active-HDL Designer Edition, which the company says “closes a gap in the mixed RTL FPGA simulation market … by providing a mixed language simulator for less than $2,000 … By purchasing Active-HDL Designer Edition, FPGA designers receive technical support directly from the EDA manufacturer. Additionally, software revisions and library maintenance are the same across all
configurations of Active-HDL “

*Altera, GiDEL and Impulse C announced support for Florida’s Novo-G, “being built at CHREC, the NSF Center for High-Performance Reconfigurable Computing. Novo-G will be the most powerful reconfigurable computing machine ever fielded for research. It links 24 PCI Express PROCStar III Gidel boards, equipped with 96 Altera Stratix III FPGAs and 408GB of memory. These boards are hosted in 24
servers with 576 GB of memory and 20 Gb/s InfiniBand.”

*Altos Design Automation announced Liberate MX, “an ultra-fast, general purpose library characterizer for memories and custom macro blocks, [which] generates instance specific library models in Liberty format including advanced current source models for timing and noise.” The company also announced Liberate LV, “to validate cell libraries [by] checking all functional, timing, noise, and power data
for potential problems.” Note, CSR is using Liberate LV for library qualification and validation.

*Altos also announced its partnering with EdXact “to improve characterization turn-around time, especially for large cells and macro blocks, [by developing] an integrated flow between Altos characterization products, Liberate, Variety, and Liberate MX, and EdXact’s Jivaro parasitic reduction platform.”

* Atrenta and Mentor Graphics have collaborated on an high-level synthesis power optimization flow, which “has resulted in an interface between Mentor’s Catapult C Synthesis high-level synthesis tool and Atrenta’s SpyGlass-Power RTL power estimation and reduction tool to automate multi-level clock gating.”

*Avery Design Systems announced that its PCI-Xactor verification IP now supports the PCI Express 3.0 draft standard.

* AWR announced Version 2009 of its Microwave Office design suite. Per the Press Release: “The latest release of AWR's flagship product features new MRHB technology that dramatically increases the speed and reduces the computer memory required to perform steady-state analysis of complex nonlinear systems with multiple signal sources.”

* Blue Pearl Software announced Cobalt Timing Constraint Management, designed to

“implement new designs more efficiently by automatically managing complex timing constraint files for synthesis, static timing analysis and P&R. Per the Release: “The management of SDC constraints includes migrating block-level constraints to top-level and merging constraint files for P&R, as well as migrating constraints from top-level to block-level after synthesis for better implementation and faster timing closure … Cobalt Timing Constraint Management works on both RTL and netlist constraints to automate the process.”

* Cadence Design Systems announced a “unified TLM-driven design and verification methodology enabling … transaction-level modeling. [It] combines C-to-Silicon Compiler with new memory compiler integration and C/C++ usability, Incisive® Enterprise Simulator with new TLM/RTL metric-driven verification and source level debug visualization, Calypto sequential logic equivalence checking, the first version of the
TLM-driven design and verification methodology, and customer adoption services.

“The new TLM-driven design and verification methodology encompasses SystemC modeling guidelines for virtual platforms and high-level synthesis, and defines the process for performing multi-language OVM-based functional verification of TLM, TLM/RTL, and RTL … New capabilities include migration from C/C++ to enable automatic conversion of legacy design sources to SystemC TLM; high-level synthesis integrated with popular memory compilers to optimize for each architecture; and side-by-side analysis and traceability of SystemC and synthesized RTL.”

* Cadence also announced that Toshiba Information Systems is using Virtuoso Custom IC and Encounter Digital Implementation System for its mixed-signal design environment.

* Cadence also announced that National Semiconductor is using Virtuoso Accelerated Parallel Simulator to verify “large, complex” analog designs.

* Cadence also announced that Richoh Co. has joined the Power Forward Initiative “after completing two complex power management SoC designs using the Cadence Low-Power Solution.

*Cadence also announced that Hitachi implemented a 50-million+ chip design in five weeks using the Encounter Digital Implementation System.

* Cadence also announced that STARC has implemented a Cadence flow for designs larger than 20-million gates. STARCAD-CEL V3.0 methodology was defined to describe a “comprehensive RTL-to-GDSII design methodology for quickly designing semiconductor systems of this size.”

* Calypto Design Systems announced SLEC 4.0, which the company says “has up to five times the capacity of the previous version and provides tighter integration with the leading high-level synthesis tools from Cadence Design Systems, Mentor Graphics, and Forte.”

* CAST announced a new H.264 encoder core that the company says “delivers some of the best looking compressed video available. [The core] is intended for applications that require the transmission of the highest quality video over low bit-rate channels, including remote medical diagnostics, military targeting, satellite reconnaissance, and

advanced surveillance systems. It offers this quality for screen sizes from handheld (CIF, 352 x 240 pixels) to full HD (1080p30, 1920 x 1080 at 30 frames per second).”

* CEVA announced a collaboration with Tessera to create “high-performance face detection and face tracking capabilities,” using Tessera’s FotoNation embedded image enhancement tools on the CEVA-MM2000 portable multimedia platform.

*ChipVision Design Systems announced enhancements to PowerOpt in system-level power optimization, increased synthesis speeds up to 10x that of competitive tools, and support for designs written in ANSI C, C++ and SystemC.

Per the Press Release: “Many new innovations in PowerOpt bring significant reductions in power consumption in synthesized designs, [including] enhanced loop pipelining with automatic run-out support for automatic pipeline flushing; memory access optimizations; false path elimination and SDC constraint generation, enabling creation of the lowest-power architectures that can be synthesized to gates using RTL synthesis; enhanced clock-gating optimization to determine lowest-power configuration on a register-by-register basis, as well as finite state machine encoding that minimizes switching activity to reduce power.”

* CoFluent Design announced Siemens is using CoFluent Studio to create timed transactional models of its complex Industrial Ethernet switch component, running SystemC models on the CoWare Platform Architect SystemC kernel.

* CoWare and EVE announced “the first fully-integrated, high-performance solution combining virtualization and emulation to enable pre-silicon software development and hardware/software co-verification for multicore ARM AXI-based SoC designs. CoWare Virtual Platform and EVE’s ZeBu emulation uses CoWare’s fast untimed emulation adapters and EVE’s Synthesizable AXI Transactors … to bridge the gap between
the virtualized, transaction-level representation of the system for software development and the RTL implementation of subsystem hardware in emulation, enabling transaction-based communication of RTL design blocks with an ESL environment at 100,000s transactions/second.”

* CoWare and ARM announced that NXP is using software jointly developed by CoWare and ARM, which integrates Fast Models from ARM for Cortex processors in CoWare’s Virtual Platform technology. Per the Press Release: “NXP uses the joint ARM-CoWare offering in their own SystemC based Virtual Prototyping Environment (VPE). VPE is NXP’s internal development environment utilizing the virtualized
representation of an electronic system … Using their VPE with the ARM® Cortex-A9 processor-based Fast Model, NXP ported Linux in record time, ahead of RTL availability and faster than with traditional emulation based development methods.”

* CWS and Physware announced a joint White Paper: “Enabling System-level Electrical Co-design for Mixed-Signal System.”

* Duolog Technologies announced Weaver, an EDA tool for chip assembly that forms part of the Socrates Chip Integration Platform. Per the Press Release: “Weaver is used to quickly and efficiently package and integrate the IP components of a system using rules-based integration, a methodology that promotes a formal method for SOC integration .. The formalization underlying Weaver’s rules-based integration encompasses the standardization of
IP metadata, powerful assembly primitives that manipulate the metadata and high-level integration functions that automate the different assembly tasks.”

* edXact announced Jivaro 4.3 includes EM analysis tool compatibility, “extended support for RC subnets modeling large power nets and substrate, and improved support of highly hierarchical netlists.” The company also announced Comanche 3.1 includes “an API, faster calculation of effective resistance, visualization of the most resistive part of a path.”

* The IEEE approved the IEEE 1450.6.1 Standard for Describing On-Chip Scan Compression. “Also known as the Open Compression Interface (OCI), it was initially created within the Accellera standards-setting organization and was transferred to the IEEE following Accellera's ratification.”

* Evatronix SA announced today its C68000 IP core has been used in the HAPA 100 Controller series for printers.

* EVE announced Ze-Bu-Server, “a scalable emulation system capable of handling up to one-billion ASIC gates … The ZeBu-Server compiler includes a multicore [to reduce] compile time on large designs. In early tests, the ZeBu-Server software compiled a 200-million gate design in less than 10 hours, and a one-billion gate design in less than 12 hours … ZeBu-Server is suitable for all SoC verification needs across the entire
development cycle, from hardware verification, hardware/software integration to embedded software validation. It can be used as a multi-user, multi-mode accelerator/emulator with a typical performance of 10 MHz on a 40-million gate design.”

* GateRocket announced RocketDrive for Altera's Stratix IV FPGAs. Per the Press Release: “RocketDrive cuts verification and in-system debug time for advanced single or multi-FPGA based projects while adding significant value through seamless integration with a design team’s existing verification environment, with no changes to the flow or verification methodology.”

* IMEC announced developments in dielectrics and metallization technologies, as well as integration approaches. Per the Press Release: “Great progress has been obtained in the metallization of 22-nanometer interconnects, in Cu/low-k reliability assessment and in the suppression of low-k integration damage. The results contribute to deliver the interconnect performance and reliability beyond the 32nm node.”

* IMEC also announced “promising results in the race to scale CMOS to 22 nanometers and below, [including] a successful integration of the laser-anneal technique in a high-K/metal-gate first process and a step forward towards fabricating aggressively scaled germanium-pFET transistors.”

* Incentia Design Systems announced the latest ECOCraft release includes CPF/UPF power format support, SPEFflow support, signal integrity awareness and setup time fixing.

* Incentia also announced that Via Telecom is using Incentia's DesignCraft and TimeCraft for logic synthesis and STA in its new 3G CDMA cell phone chip tapeouts.

* Jasper Design Automation announced JasperCore, which the company says “harnesses the proven capabilities of the company’s formal analysis engines to boost productivity and decrease the cost of deployment by performing numerous parallel runs using ProofGrid, a new capability that distributes formal technology. Together, JasperCore and ProofGrid allow users to implement multiple proofs, tasks, and applications, across multiple cores and
computers, efficiently serving multiple users … Proof Grid [is] included in both JasperCore and JasperGold.”

* Lynguent announced two new toolkits for its ModLyng Integrated Modeling Environment (IME): Radiation Hardened By Design (RHBD) Toolkit, and BSIM4 Compact Model Toolkit. Per the Press Release: “The RHBD Toolkit includes models and tools which provide a modeling and analysis capability for Single Event Upset (SEU) behaviors in deep sub-micro processes. The BSIM4 Compact Model Toolkit includes a high fidelity BSIM4 model which provides more
flexibility than has ever been available for adding new effects to existing processes built upon the BSIM foundation.”

* Magma Design Automation announced the launch of its PCIe SmartLink, which uses “PCI Express technology for interconnection between servers and/or storage units using PCIe interconnect technology … PCIe SmartLink can be scaled on its communication bandwidth to an aggregate data rate of 4Gigabyte/sec between two Host Computers or between a Host Computer and Storage unit.” Features include: configurations that allow for
connectivity between servers, workstations and expansion chassis; eliminating TCP/IP overhead on inter-communication; ability to boot from existing OS without changes; low latency data transfer.

* Magma also announced that STARC evaluated Talus Vortex and Hydra, and is “presenting Talus Vortex and Hydra to member companies as a complete hierarchical flow to manage multimillion-gate design complexity and achieve timing closure.”

* Magma also announced that Camtek Ltd. integrated Magma's YieldManager software into Camtek’s Falcon automated wafer inspection and metrology systems, and will sell it as an option.

* Magwel NV announced two products: Power Transistor Modeler (PTM), “which extracts series-on-resistance (Rdson) of very large power transistor arrays, [highlighting] current hot-spots and electro-migration problems directly on the GDS layout“; and Substrate Noise Modeler (SNM), which analyzes substrate noise injection (both minority and majority carrier injections) and noise coupling to sensitive circuits, which is
typically found in power management devices. SNM takes GDS layout and technology information as input and provides 3D device simulation accuracy with very fast simulation speed.”

* Mirabilis Design and TOPS Systems jointly announced the “Android on VisualSim” architecture exploration platform. Per the Press Release: “Systems designers of Android devices can use this platform for hardware-software architecture exploration and power and performance analysis of consumer devices. “Android on VisualSim” integrates the Android virtual prototyping environment to both a statistical and instruction-set level hardware model in VisualSim. The complete suite of analysis tools generates task latency, device utilization, system throughput and energy consumption … and generates the software activity for the target hardware platform. The hardware platform simulates the accurate system operation including arbitration, cache misses and queuing effects … Android Architect can select the optimal system configuration for a set of applications; optimize the software for lowest power consumption; and determine the best task distribution across multiple processing cores. The hardware platform enables early identification of system bottlenecks and identifies
areas for cost reduction.”

* NetLogic Microsystems and TSMC announced collaboration on a 40-nanometer-G semiconductor process technology for NetLogic Microsystems' next-generation advanced knowledge-based processors and 10/40/100 Gigabit Ethernet physical layer (PHY) products. The companies say “NetLogic Microsystems is one of first companies to tape-out and sample multiple silicon products in TSMC's advanced 40-nanometer technology node.”

*NXP Semiconductors and TSMC announced delivery of “the industry's first single-chip 45-nanometer global LCD TV platform, TV550, [with] NXP's PNX85500 processor built on TSMC's 45nm Low Power process technology. The TV550 platform is a production-ready reference design [that] allows TV viewers to enjoy HD digital content and internet access with unparalleled picture quality.”

* Oasys Design Systems announced RealTime Designer for physical RTL synthesis of 100-million-gate designs, synthesizing RTL to placed gates in a single pass and in a fraction of the time compared to traditional synthesis. Per the Press Release: “RealTime Designer features a unique RTL placement approach that eliminates unending design closure and iterations between synthesis and layout. RealTime Designer is already in use in production flows
at leading-edge semiconductor and systems companies worldwide.”

* OneSpin Solutions announced RootCauseAnalyzer that “boosts formal ABV by speeding SVA and RTL debug [and] eliminates most of the time-consuming, error-prone manual analysis of complex information otherwise necessary to trace the root causes of assertion failures, speeding assertion and design debug by up to 10x.” The new release has 4 components: WaveformAnalyzer, displays diagnostic information; StructuralAssertionAnalyzer, an SVA
code debugger, TemporalFaninAnalyzer, automatically traces signal in assertion failure back to related design signal; ActiveCodeAnalyzer, marks RTL source code regions associated with assertion failure.

* Tieto and OneSpin Solutions announced an agreement to use OneSpin’s 360 MV formal assertion-based verification tool in Tieto’s high-end FPGA verification flow. Tieto’s largest division, telecom and media, will use 360MV.

* Premier Farnell announced Altium and EMA Design Automation have “integrated Premier Farnell’s DesignLink web-service environment. Per the Press Release: “DesignLink allows electronic designer engineers to immediately search and find parts from within their CAD design environment, without ever having to leave the program.”

* Real Intent announced that the Ascent product family now includes “the first commercially available automated solution to ensure X-robust designs, available through the Ascent Path-Based Verification (PBV) product … Ascent PBV offers a multi-faceted solution that addresses the problem through structural and formal analysis, as well as by augmenting simulation using Ascent SimPortal. Explicit and implicit X sources are automatically
detected. Innovative formal techniques are used to prove X-optimism safe designs. Ascent SimPortal can augment simulation to detect X-excitation, control X-pessimism, as well as eliminate X-optimism without loss of efficiency.”

* Sagantec announced that MoSys used Sagantec's Anaconda-M tools to help migrate its high-performance interface IP designs from 65 nanometer to 45/40 nanometer technology. The first implementation has been silicon-proven.

* Satin IP Technologies, Toppan Photomasks France, and XYALIS SaRL announced a collaboration within the Crystal partnership program to intended to improve design for mask manufacturing (DFMM) by “breaking the barriers that have traditionally separated IC designers from mask shop engineers. Crystal is a European collaborative R&D program sponsored by the Cluster for Application and Technology
Research in Europe on NanoElectronics (CATRENE). Other participants include Atmel and CEA-LETI.

Per the Press Release: “While the old design rule checkers developed into sophisticated and pro-active DFM tool suites, the mask rules checks are still implemented at the final phase when the GDSII data is released. RET and OPC further restrict the ability to revise the design or even to take into account the mask manufacturability issues for an additional design cycle. One of the Crystal work packages is devoted to identification and formalization of recommended design practices to make mask manufacturing a more efficient and less iterative process. Crystal will also provide the tools to deploy and monitor those practices throughout the design chain.”

* Sequence announced PowerArtist-XP, described as the “first and most comprehensive analysis-driven, automatic RTL power-reduction technology within a completely integrated environment. [The tool] allows IP and SoC RTL designers, without becoming power experts, to analyze, visualize and reduce power by 10-to-60% or more within minutes on multi-million instances, with 50% fewer RTL edits, and productivity gains of 10X at a minimm …
PowerArtist-XP is compatible with all standard design flows, including synthesis, simulation, and formal verification, and all leading formats and constraints including CPF, UPF, and Synopsys Design Constraints (SDC).”

* Silicon Frontline Technology announced its Fast 3D extraction software for post-layout verification has been qualified at TSMC’s 40 and 65 nanometer processes. Per the Press Release: “The tool supports TSMC's new iRCX format to improve parasitic extraction and modeling accuracy, and ensures EDA tool interoperability for high performance chip designs.”

*Synfora announced PICO Extreme Power, which the company says “is the industry’s first algorithmic synthesis tool to automatically minimize power consumption at the system-level based on a variety of techniques, including automatic multi-level clock gating insertion … Researchers at Rice University designed and evaluated a low-density parity check (LDPC) decoder for w next generation wireless handset SoC… and demonstrated a
23.5% reduction in dynamic power over an identical design using a standard flow. The Indian Institute of Science (IISc) evaluated the effectiveness of the approach using eight complex applications from video, imaging and wireless domains, [and] results indicate as much as 50% savings in dynamic power for executing a single task in some of the applications and as much as 30% savings while executing a large number of tasks.”

* Synopsys announced its DesignWare minPower Components IP, which the company says “dramatically reduce power in datapath logic compared to traditional power optimization methods. By using the DesignWare minPower Components, leading wireless, networking and DSP companies achieved power reduction of up to 48 percent in datapath logic.

* Synopsys also announced that Achronix Semiconductor is using IC Compiler and IC Validator for designing next generation high-end FPGAs.

* Synopsys also announced that NetLogic Microsystems has agreed to establish Synopsys as its primary EDA partner.

* Synopsys also announced DesignWare IP for PCI Express (PCIe) 3.0, which includes digital controllers, PHY and verification IP, and “enables easy integration of the 8.0 GT/s PCI Express 3.0 interface into SoCs for high-performance enterprise computing apps.”

* TSMC announced an enhanced version of its 0.13-micron process. Per the Press Release”

“The 0.13-micron/0.11-micron family now includes a slim standard cell, SRAM and I/O with substantial area reduction … The process also adopts LD-MOS (5V~20V) on RF platforms to enable analog and power management applications. The slim platform is available in the third quarter this year while the LD-MOS on RF platforms will be available in Q4 this year.”

* Zocalo Tech announced the company’s Zazz product is now shipping. Per the Press Release: “The Zazz Front End includes an advanced incremental parser, elaborator and design viewer. An existing design or new design is read into Zazz, where it is parsed, elaborated, and graphically displayed … and then modified with the editor of choice without leaving Zazz. Zazz supports Verilog 1995, Verilog 2001 and SystemVerilog design

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-- Peggy Aycinena, EDACafe.com Contributing Editor.

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