June 22, 2009
Bryant the Beer Guy & Your Plans for DAC
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| by Peggy Aycinena - Contributing Editor
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There’s lots going on at this busy time of year, particularly in the weeks running up to DAC in San Francisco. Not suprisingly, this edition of EDA Weekly is busy, as well.
Herein you’ll find some suggestions for a calendar at DAC, how the Balance of Power in EDA has shifted of late, how Real Intent is looking towards its next 10 years of business, how Portland’s ADi helps tech folks learn what they need to know, links to recent blogs about open source EDA, decoding the design flow, and the EDA Town & Gown Twitter project. Of course, there’s also lots of news about money, people, and tools, as you would expect in June when DAC is in July. Of particular interest,
the legendary standards bodies – Accellera and SPIRIT – are merging.
It’s pretty clear that engineering and electronic design are serious stuff and consume our lives at this time of the year. But just in case you still have a life outside of work, and hopefully you do, we’re going to start out on a somewhat lighter note.
Bryant the Beer Guy & The Brews of San Francisco ….
Bryant the Beer Guy and I met on a plane. He was headed to the American Craft Beer Fest in Boston to appear on a panel about, well, beer. During the course of our (dreadful, turbulence-afflicted) flight from SFO to BOS, he kept our minds off of our immanent death by telling me about beer.
That’s why, if you’re into beer and you’re coming to the Design Automation Conference in The City in July, this is your lucky day. Because the following, highly exclusive info – courtesy of Bryant – is everything you’re going to need to know to track down the Best Brews in San Francisco, The True Epicenter of the American Craft Beer Movement. If you’re smart, you’ll print out the following, fold it up, put it in your wallet, and have it with you every day you’re in San Francisco.
* The Bars:
Tornado at Haight & Fillmore – Tornado is a famed dive bar, but it’s a total institution in the Beer World with an amazingly diverse & cheap tap selection – 60 or more, in fact, but who’s counting?
Magnolia Brewpub at Haight & Masonic – The beer’s brewed in the tiny basement of this gastro-pub. Also, it’s a great place for dinner, including burgers, fish & chips, steamed mussels, and salads. It’s Californicated Irish’ish and a bustling place to hang out.
Thirsty Bear Brewpub on Howard – This one’s closest to Moscone Center (and DAC), and a famous venue for software developers everywhere. Bryant says to try the Vanilla Ale.
* The Stores:
City Beer Store on Folsom between 7th and 8th – You’ll find an amazing selection of the most ingenious brewers’ fruits from near and far. Beers can be taken away, or enjoyed in-house. Owners Craig & Beth will direct you to the right beer for any mood and/or thirst.
Whole Foods at 4th at Harrison – Although you’ll find less personal service at Whole Foods, the selection’s great.
* Northern California’s Greatest Local Brews:
Lagunitas – “IPA” – a balanced, yet crisply hoppy beer. (Petaluma)
Russian River – “Pliny the Elder” – an Imperial IPA and über-hoppy. (Santa Rosa)
Bear Republic – “Racer 5” – a super citrus hop explosion (Santa Rosa)
Anderson Valley – “Boont Amber” – a balanced, malty beer with a smooth hop finish (Booneville)
Speakeasy – “Prohibition Pale” – Bryant makes a shout-out to this local favorite. (San Francisco)
Anchor – “Anchor Steam” – Arguably the pioneer of the American Craft Beer Movement, this is the first brew that is a true American-originated style, “California Common.” (read, “It’s not British, German, or Belgian!”) The temperature in San Francisco was cool enough that the folks at Anchor could use lager yeast and ferment the brew in the cool, nighttime temps they found right up on their own rooftop. (San Francisco)
* One last note from Bryant the Beer Guy – Don’t forget that both grapes and hops grow best in the very same climates. However, the financial reward of growing grapes for Northern California’s wine industry incented more vineyards be planted, pushing
out the hop growers. Now, most American hops are grown in the cooler, slightly more northern climes of Oregon and Washington. Nonetheless, if you like beer, the brews you’ll find in San Francisco come July have enough character to satisfy every taste, mood and pocketbook.
Now that you know what and where to drink, it’s time to establish your plan for DAC itself.
The 2009 Design Automation Conference …
This year’s extravaganza is really jam-packed. General Chair Andrew Kahng (UC San Diego) and the entire Executive Committee, not to mention everybody on every committee, plus the hard-working folks at MP Associates, are pulling out all the stops to get this Cable Car out of the barn on time and in tip-top shape. After studying the schedule for several hours – and it’s intense – here’s how I’ve constructed my schedule at DAC. Don’t forget in reading this, however, that the new User Track at DAC will be racing along in and around all of the events listed below.
Saturday, July 25
* Design Automation Summer School
Sunday, July 26
* Tutorials on UML and Multiprocessor Design, plus DFM&Y (events run all day)
* The Traditional Sunday Evening Welcome to DAC event, but only if you’re sure it’s actually happening. (Check local newspapers for listings.)
Monday, July 27
* Workshop for Bio-design Automation (8 am)
* Workshop for Women in Design Automation (9 am)
* The Young Faculty Workshop (9 am)
* Gary Smith on what’s Hot to Trot at DAC (9:30 am)
* DFM Workshop (all day)
* Texas Hold’em at ClioSoft (3 pm)
* Pavilion Interview with 2009 MRP Winner Telle Whitney (3:30 pm)
* Kid Gloves & High Tea (4:30 pm) with the current EDA Triumvirate, Wally Rhines, Aart de Geus, and Lip-Bu Tan (Yes, John – Rajeev most definitely should have been there. Shame on all of us for not insisting!)
* The DAC Student Design Contest Awards (5 pm)
Tuesday, July 28
* Opening session (8:30 am) and keynote to hear TSMC’s plans for the future of EDA
* User Track session on Timing Analysis (9 am)
* Pavilion Panels discussing Piracy Defense (10:30 am) and Interoperable PDKs (2:30 pm)
* CEDA Adjunct Event re: Research & Education (12 noon)
* Special Session on 22 nanometers (2 pm)
* Pavilion Panel on Embedded Multicore (3:30)
* The Final Panel for Management Day (4 pm – I’m moderating)
* The Accellera/SPIRIT Event
* The Denali Party for those whose Cool Quotient Qualifies.
Wednesday, July 29
* The WACI Special Session to start off the morning (9 am)
* At least 3 hours pounding the pavement in the Exhibition Hall
* Nvidia Keynote on Throughput Computing (11:15 am)
* Pavilion Panels on Green Electronics (12:30 pm), AMS (3 pm), and Design Reuse (5 pm)
* Special Sessions on Post-Turing Computation (2 pm) and Multicore Computing (4:30 pm)
* The Mixed-Signal Tech Panel (4:30 pm).
* For those still on their feet after 4 or 5 days of hard labor, there’s the DAC Party
* Before you go, mingle with the folks milling around outside the all-day NASA/ESA Conference on Adaptive Hardware and Systems.
Thursday, July 30
* Bug Hunt Special Session (9 am)
* High-School Musical goes High-Tech (10 am)
* Plenary Panel: Wally Rhines on Green Tech (12 noon)
* Tech Panel on Watts, milli & mega (2 pm)
* Special Session on Green Data Centers (4:30 pm)
* ACM Symposium on Nanoscale Architectures (all day, plus Friday).
Friday, July 31
* Pick a full-day tutorial to attend (yes, it costs extra)
* Two flavors of Verification,
* Parallel Programming
Saturday, August 1
* Try to decipher at least 1000 pages of notes
Also coming soon to a theater near you ….
* Denali MemCon 2009 – June 22-25 in Silicon Valley
* Asia ISQED’09 – July 15-16 in Kuala Lumpur
* SEMICON West – July 14-16 in San Francisco
* Hot Chips – August 23-25 at Stanford
* Hot Interconnects – August 25-27 in New York City
* SAME 2009 – September 22-23 in Sophia Antipolis
EDA: A New World Order ….
EDA is changing, make no mistake. Just as a New World Order emerged in the 1990's after the collapse of the Soviet Union, a similarly seismic re-ordering of the EDA world is taking place today.
The fall of the Berlin Wall in 1989 was the most notable sign of the end of the Old Order in the Global Politik. The fall of Cadence CEO Mike Fister et al in 2008 was the most notable sign of the end of the Old Order in EDA.
With the end of the Soviet empire, the U.S. emerged as the lone superpower in the world. With the collapse of the Cadence empire, Synopsys now emerges as the lone superpower in the EDA.
Real Intent Looks to the Future ….
Real Intent is really intent on growing its business, here in its tenth year of business, according to CEO Prakash Narain, and Vice President of Sales and Marketing Carol Hallett. I spoke to them both recently by phone.
Narain said, “We’ve always been a verification products company – very stable with a set of loyal customers. They’ve been happy with our products over the last 10 years, and we continue to be excited about our opportunities even in these economic times. [Of course], this will be a mixed year for everyone. We’re seeing that a lot of funding at our customers has been curtailed. Nonetheless, we’re fortunate, because there’s also a lot of willingness to look at tools and products at this time.”
I asked how it is that companies today have the money to evaluate new tools. Narain said, “The urgency to start the next generation [of products] may be a bit less, but there are still gaps in the flow. As a result, people are still finding the time to look at new tools and technology.”
Hallett added, “We’re seeing in the military portion of the industry, for example, there are projects and budgets for those projects. It’s easy for them to say, ‘I’ve got a budget, a requirement, and I want to look at your tools.’ In other places, customers are working on new projects and have already used our tools in their flow. They’ve already done a tapeout and now are trying to clean up those designs for reuse. We can show them how to find a solution.
“Finally, there are the startups. They may not have the budgets for a project, but we’re helping them find ways to move those projects forward nonetheless. [Overall], we’re finding lots of different opportunities, even today.”
At my request, Narain articulated the tools in the Real Intent portfolio, “First off, we have automated functional verification tools, which provide a way to detect and eliminate a very large number of bugs in the design, even before simulation. Those tools include Ascent and Conquest, which apply our strategy in a very comprehensive way.
“Then we look at a second dimension of verification through our Meridian CDC and PureTime, which address clock-domain crossing and timing analysis issues, respectively – also in an automatic and comprehensive way. Our tools [help] you to gain the confidence that formal analysis and automatic formal verification bring to design, but without the difficulties.”
I asked Narain if there are, in fact, two classes of verification – formal analysis and automatic formal. He said, “First, there’s equivalence checking, which is purely combinational formal verification. It’s the most automate for and has been widely used for quite a while. The next level of complexity depends upon how large a sequential behavior you are looking to verify. In our case, by doing automatic formal verification on a large collection of relatively simple behaviors, we can automatically detect up to 50 percent [of the design bugs], which provides tremendous value to our users.”
And how does one find a ‘simple behavior’? Narain said, “We look at the RTL, the way the RTL is written, and from that we can infer implied intent. Using our tools, you don’t have to do much to clear up a large gap in the design quality, even before simulation and testbenches.
“We automatically formulate thousands of checks, which will not cover every bug, but will quickly detect more than half of the bugs in the design. The design to quality build up is therefore very fast, without the latency, so the project moves much more quickly. And the tools can be used by the design engineer, without help from a verification engineer, which provides a high return on investment.”
Do Real Intent tools need to be used in a linear fashion for complete coverage? Hallett laughed and said, “As a sales person, I would certainly say yes!”
I noted that some years ago, there was a big Verification Fad in EDA, and asked if that had been helpful or harmful to Real Intent. Narain said, “That’s a good question, and I’m quite ambivalent about the answer. Verification is a very difficult problem. Typically what happens is, something shows up in the technology and all of a sudden, people get very excited about it. It becomes the talk of the town for a year or two, but technology takes a lot longer than that to develop into usable products.
“The big issue at the time [of the Verification Fad] had to do with the fact that there were multiple verification companies out there. But it’s a tough space requiring lots of investment and hard work. That’s when you need money to outlast the competition and investors who understand what you’re trying to accomplish.
“The attention we got in [the Fad Years] was helpful, but there was also a lot of competition for that attention. However, it’s always been the bigger EDA companies that have been our real competition, and that's no different today than it was back then. [And in fact], we’re not even really competing with the big companies. We’re competing with the image of the Big Three!”
Hallett said, “If you look at our four products and their capabilities, there’s no one really who directly competes with us. There is perhaps some overlap with Mentor, Synopsys, and Cadence, [such that] a customer might say, ‘Why should I pay for your solution, when there’s a solution offered by my big EDA vendor?’
“But the solutions from the Big Three are not always what they’re made out to be. If you don’t want to pay for our solution, you may very well get caught after tapeout having to spend more money on engineering time to fix the things you would have found earlier if you had used our tools. So, you can pay earlier in the process or you can pay later one in the process, after tapeout, if you use the [lesser solutions] from the Big Companies.”
Narain agreed and said, “That’s always the toughest problem for the customer, the pressure to buy a solution versus accept the free, albeit less complete, solution.”
Portland’s ADi & Animation ….
Is there such a thing as enjoying your work too much? If so, Kate Ertmann may be the worst offender. Not only does she love her work – she’s President of Portland-based ADi – but the stuff her company produces is way too cool to describe in words. So before you read on, check out the ADi website, in particular the Case Studies link ...
Okay. Did you check it out? I’m particularly partial to The Snow Globe, Epic Imaging, and the ADi 2009 New Year Project, a hauntingly abstract journey through the clouds. Clearly ADi is populated by some pretty creative people with superb technical skills.
Ertmann told me, when we spoke recently by phone, “ADi does any type of animation, but we excel in that creative space between story telling and technology – creative but still based on physics and math. We love using animation to explain new technology, demonstrating a concept visually that would otherwise be so much harder to grasp.”
If the folks at ADi like physics and math so much, I asked Kate if her company develops the fundamental algorithms that drive the animations, or if they get them from customers. She said, “We can do both. We can create the geometry of a model based on the data provided and then we apply the shading algorithms to that model or our customers can give us their CAD data – something we call the ‘heavy model’ – and we can lighten it up to more easily move it around in a 3D space.”
Given the complexity of the 3D animation and images produced by the company, it’s not surprising that ADi has a huge render farm. They also have huge range of customers, everyone from Intel to eco-friendly enterprises based locally in Oregon.
“We work with a lot of different types of industries,” Kate said. “We do a ton of work with Intel, for instance. We’ve been helping them for 10 years now, to visualize new processes for their employees or new products for their customers. We can create animations for technologists to communicate with other technologists, or for tech folks to help their sales and marketing people reach a wider audience.
“But we work for other types of industries, as well. For example, attorneys working on patent disputes will hire us to create animated tutorials to help illustrate a technology for a judge or jury. It serves as a way to demonstrate to a layman what people are talking about in a complicated patent case.”
Given her company‘s track record in high-tech, I asked Kate if she could envision a way ADi might provide animation services to the EDA industry. “Absolutely,” she said. “There’s been a lot of work done lately looking at the human factor in technology, particularly how people learn to use technology.
“At ADi, we can take a photo of a real device, or the user interface for a software application, and render it into something that’s far more stylized and far more [appealing and interesting]. We can create an animation of an object or idea, which then serves as a great way for people to learn how to use a technology.”
Could ADi produce an animation demonstrating how to use an EDA tool, or a detailed voyage ‘through’ an IC designed with that tool? Again Kate said, “Absolutely, that‘s exactly what we do. If a picture is worth a thousand words, an animation is worth even more. When people learn this way, so much time is saved.”
It’s a Blog, Blog, Blog, Blog World ….
* Open Source EDA Tools defeat Lock-in – Dream on
“If a shared-code mechanism evolves between the EDA vendors and the open source EDA developers, there may come a time someday when open source-like solutions are applied to problems in electronic design as effectively as open source solutions today tackle problems as diverse as accounting, graphics, and office productivity.”
* String of Pearls vs. Web of Wonder
“I suspect I’ll find that the line of tools I’m attempting to unearth isn’t a line at all, but a multi-dimensional mesh of interconnected applications from a wildly interconnected set of vendors that’s devolved over time from a streamlined flow into a rat’s nest of confusion and overlap.”
* The EDA Town & Gown Twitter Project – 100 Days of Glory
“I added my lack of Tweets to the idea that lots of info could be packed into an itty bitty space, and combined that with the impression that the people connected to me on Twitter were mostly from EDA, plus my conviction that the academics and industry types together have created this industry, and voila! The EDA Town & Gown Twitter Project was born.”
* The EDA T&G Project
Virtual cool ….
* Dassault Systèmes announced that the Bureau of Shanghai World Expo Coordination has chosen the Dassault’s 3DVIA, to create the “first ever World Expo Shanghai Online … accessible to anyone anytime, providing virtual visitors with 3D lifelike experiences, real-time interaction and a global platform to allow everyone’s online presence at the Expo.” Very cool!
Linking arms ….
* Accellera and SPIRIT announced they will be merging into a single organization. This is the result of a complicated decision on the part of the two organizations to combine resources, seek and find synergies, and move boldly forward with a new vision that embraces progress on both the design language and IP standard fronts. It’s a commendable act of unity to create the new organization, which will be branded Accellera. The
industry can certainly expect a great deal of contribution from this new and even more powerful force in the industry.
* CoWare and EVE announced what the companies are calling “the first fully-integrated, high-performance solution combining virtualization and emulation to enable pre-silicon software development and hardware/software co-verification for multicore ARM AXI-based SoC designs. CoWare Virtual Platform and EVE’s ZeBu emulation uses CoWare’s fast untimed emulation adapters and EVE’s Synthesizable AXI Transactors
… bridging the gap between the virtualized, transaction-level representation of the system for software development and the RTL implementation of subsystem hardware in emulation.”
“The hybrid, off-the-shelf solution enables fast and efficient development of hardware-dependent software and hardware/software co-verification ahead of first silicon. By enabling transaction-based communication of RTL design blocks with an electronic system level (ESL) environment at 100,000s transactions/second, it accelerates the development cycle for SoC designs while increasing verification productivity.”
* Synopsys announced its System-Level Catalyst Program “to accelerate the adoption of system-level design and verification.” Everybody’s welcome … EDA vendors, IP vendors, embedded software guys, and service providers. If you join, you get access to Synopsys’ system-level and rapid prototyping products, plus use of the Synopsys System-Level Catalyst logo with your related produced.
Gary Smith says it’s a great idea and a lot of companies agree, including: Agilent EEsof, Altera, ARC, Carbon Design, Cebatech, ChipVision, Cofluent, CoWare, CriticalBlue, Doulos, Emsys, Enterpoint, Forte, GreenSocs, IBM, Imperas, JEDA, Jungo, Lauterbach, MCCI, NoBug, SDV, Steepest Ascent, Synfora, Target Compiler, Tensilica, VaST, and Xilinx.
Money makes the world go’round ….
* Teklatech announced a $1 million round of funding “from a group of private investors in syndication with major Scandinavian venture fund Vækstfonden.” Jesper Noerregaard, business angel and new board member of Teklatech, is quoted in the Press Release: “Even in a cold capital market, there's always money for really great ideas”
* Cadence Design Systems announced a restructuring to “streamline operations and … achieve annual operating expense savings of approximately $30 million, through a combination of workforce and other expense reductions … The Company expects to eliminate approximately 225 full-time positions, representing 5% of its global employee base. The reductions come primarily from resizing the worldwide field organization to current business levels,
decreasing the level of investment in the manufacturing side of DFM and other infrastructure areas of the business.”
* Magma Design Automation reported revenue of $34.1 million for Q4 and $147.0 million for its 2009 fiscal year, both ended May 3, 2009. Magma reported a GAAP net loss of $127.1 million for fiscal 2009, compared to a GAAP net loss of $30.8 million for fiscal 2008.
* Mentor Graphics Corp announced results for fiscal 1Q.2010, ending April 30, 2009. For the quarter, the company reported revenues of $193.8 million, and a GAAP loss per share of $.14. Bookings for the quarter rose 25-percent over 1Q.2009.
Human interest ….
* Cadence announced that U.C. Berkeley’s Alberto Sangiovanni-Vincentelli, well-known member of the Cadence Board of Directors and a co-founder of the company, is being honored by IEEE and the Royal Society of Edinburgh with the 2009 IEEE/RSE Wolfson James Clerk Maxwell Award for pioneering research in the field of EDA. The award ALSO acknowledges Sangiovanni-Vincentelli’s contributions to advancements in the
semiconductor and electronics industry, and his enthusiasm and love of engineering.
* CebaTech announced that Joe Rash has been named Vice President of Business Development and Marketing. Previously, Rash served in an executive capacity at Qimonda, and worked in an engineering manager capacity at IBM, Nortel, and Applied Micro Circuit. Rash holds 7 patents, and has a BSEE from the University of Central Florida.
* IMEC announced that Luc Van den hove has been named President and CEO. Gilbert Declerck has been elected a member of the Board of IMEC International. In addition, Declerk will continue to serve IMEC as Executive Officer, concentrating on key governmental and industrial relations and on strategic advice. Changes will become effective on July 1, 2009.
Per the Press Release: “Luc Van den hove has spent his entire career at IMEC, where he started as a team leader in silicide and interconnect technologies research. In 1988, he became manager of IMEC’s micro-patterning group (lithography, dry etching). As of 1998, he led as Vice President the Division of Silicon Process and Device Technology. Since 2007, he served as Executive Vice President and Chief Operating Officer.”
* Mentor Graphics announced the call for submissions its 21st annual Technology Leadership Awards competition, recognizing excellence in Printed Circuit Board design. Mentor says their program is the longest running competition of its kind in the EDA industry. Judges will include: Happy Holden, Gary Ferrari, Pete Waddell, Andy Kowalewski, and Rick Hartley. If you’re a board designer, these guys
need no introduction.
* Silicon Image announced Tim Vehling has been named Vice President of Worldwide Marketing. Previously he served at Micronas and LSI in executive capacities, and earlier at C-Cube Microsystems, ATI Technologies, Chromatic Research, and VLSI. Vehling has a BS.ECE from Valparaiso University in Indiana.
* Synfora has named Bruce Costello as Vice President of World Wide Sales, Alok Mehrotra as Director of Sales, North America, and Chris Rottner as Sales Director, Northern Europe. The company also announced “additional financing.” Costello previously served in executive capacities at Right Hemisphere, Cadence, and EDS. Mehrotra previously served in executive capacities at Sagantec, SDS, and
Magma. He has an MBA from Santa Clara an MSEE from SUNY. Rottner previously served at Agility Design. He has a BSEE from Salford University.
* Telle Whitney, President and CEO of the Anita Borg Institute, has been named recipient of the 2009 Marie R. Pistilli Women in Electronic Design Automation Achievement Award. The award honors Whitney for her extensive contributions to women working in technology, both as a role model while she worked in the semiconductor and telecommunications industries and as a leader with the Anita Borg Institute, as well as her
other volunteer and professional roles. For further information on Dr. Whitney, please read
* CEDA and EDAC are seeking nominations for the 2009 Phil Kaufman Award. The nomination deadline is June 30, 2009. Information is available on the EDAC website.
* AcAe-Software announced design migration support from Mentor Graphics Design Architect / Board Station suite to Cadence Concept / Allegro platform. Per the Press Release: “The DART Design Migration Technology product family simplifies and streamlines the migration of electronic design data across EDA vendor platforms.”
* Agilent Technologies announced a foundry-certified PDK that supports TriQuint Semiconductor’s TQPED GaSs E/D pHEMT process.
* Agilent Technologies also announced Advanced Design System (ADS) 2009 Update 1, “which integrates 3-D EM analysis, wireless standards-based design verification libraries, X-parameter* simulation, statistical design and yield optimization, and enhancements for MMIC design.”
* Agnisys Inc. announced a free version of its IDesignSpec, which creates correct-by-construction code from the specification without manual effort.
* ANSYS announced Siwave 4.0, which includes “new features for signal-integrity, power-integrity and electromagnetic compatibility testing.”
* austriamicrosystems announced analogbench, a “design, simulation, and analysis tool to evaluate the performance of austriamicrosystems’ DC-DC ICs … analogbench generates a design proposal tailored to meet the user’s requirements, automatically calculates external components, and configures the application circuit.”
* austriamicrosystems and Fraunhofer Institute for Integrated Circuits (IIS) announced they will co-develop a new generation of magnetic motion sensing ICs, which will be based on Fraunhofer’s HallinOne magnetic sensor technology. “This sensor technology allows measuring of magnetic fields in horizontal and vertical dimensions, providing magnitude and direction of the magnetic field at any measured point. The HallinOne sensor
can be implemented in a standard CMOS process, and can be seamlessly integrated with signal processing on a single die.”
* Atrenta announced that STMicroelectronics is including Atrenta’s SpyGlass-MBIST insertion tool as part of its front-end design kit. Per the Press Release: “This kit is accessible to all ST design teams worldwide as well as STMicro’s ASIC customers.”
* AWR and Rohde & Schwarz announced AWR Connected, which integrates the capabilities of R&S WinIQSIM2 simulation software within its Visual System Simulator (VSS) system analysis software.”
* Berkeley Design Automation announced that Newport Media Inc. is using BDA’s Analog FastSPICE platform for all analog, mixed-signal, and RF verification.
* Cadence announced product capabilities that “provide design and implementation engineers with … predictability of chip performance, area, power consumption, cost, and time to market across [a] range of design activities, including system-level design and IP selection through final implementation and signoff. The features result from an integration of Cadence’s InCyte Chip Estimator and Encounter Digital Implementation System technologies.
Per the Press Release: “Using the new Cadence solution, designers can quickly and accurately estimate die size, power and cost, including real-time IP and manufacturing process what-if analysis to ease IP selection and determine design architecture and feasibility.
Perhaps more importantly: “As a milestone in Cadence's open, multi-vendor approach to IP, the solution leverages the vast ecosystem of IP at the ChipEstimate.com portal where over 200 IP suppliers and foundries contribute data to enable this accurate what-if analysis capability.”
* Cadence also announced that Casio Computer is using the Cadence’s C-to-Silicon Compiler for high-level synthesis.
* Cadence also announced that Faraday Technology used the “CPF-enabled” Cadence Low-Power Solution to tape out 20+ low-power chip designs.
* Cadence Design Systems also announced that the Chinese Academy of Sciences Institute of Computing Technology is using the Incisive Xtreme III System for “accelerating the development of RTL design with a verification flow for its … 64 million+ gates Loongson III advanced multi-core microprocessor.”
* Calypto Design Systems announced that Casio will use Calypto’s SLEC in its ESL design flow for digital cameras.
* Denali Software announced that Netronome Systems used Denali Databahn PCI Express (PCIe) design cores, MMAV, and PureSpec verification IP to design their high-performance Network Flow Processor NFP-3240, which targets “unified computing architectures.”
* eASIC Corp. announced that ARM validated eASIC’s Cortex-A9 MPCore multicore processor using eASIC’s Nextreme NEW ASICs.
* The eBeam Initiative announced that steering group members D2S, e-Shuttle, and Fujitsu Microelectronics have validated the DFEB methodology for low-volume, 65-nanometer SOC designs. Per the Press Release: “D2S and Fujitsu Microelectronics worked on the design while e-Shuttle manufactured the test chip to confirm the DFEB technology for the 65-nm node.”
* EMA Design Automation announced version 3.0 of the EMA Component Information Portal, which the company says “provides access to the Newark electronic parts database through OrCAD Capture CIS.”
* EVE announced Fujitsu Microelectronics Solutions is using the ZeBu hardware-assisted verification platform for hardware-software co-design.
* Forte announced that Ricoh Corp. designed a multi-million gate SoC design for its latest commercial printing products using Forte’s Cynthesizer SystemC high-level synthesis software.
* Gemini Design Technology announced that advICo Microelectronics has standardized on Gemini’s GSim simulator for use in all its complex, high-performance mixed-signal designs.
* LFoundry announced a high performance PDK for A/MS electronic designs, developed using Tanner EDA's HiPer Silicon software, for its LF150 modular 0.15-µm Low Power and RF CMOS process. Per the Press Release: “This grants Tanner EDA customers access to Europe's leading pure-play foundry CMOS technology … LFoundry offers a cost-efficient rapid prototyping service, known as Multi-Project Wafer (MPW) with the most frequent
schedule currently offered in the industry. LFoundry will provide special incentives to their initial customers requesting participation in the service through to July 2009.”
* Magma Design Automation announced Talus 1.1, described as “a new RTL-to-GDSII chip implementation system that delivers the fastest timing closure on the largest and most complex semiconductor designs. Talus 1.1 utilizes the new Talus COre technology, which leverages Magma's unified data model to perform timing optimization concurrently during routing.”
* Magma also announced that NVIDIA is using the Talus 1.1 IC implementation system in full production.
* Mentor Graphics announced that Fujitsu Microelectronics “qualified and adopted Mentor’s Calibre design-to-silicon platform for physical verification and DFM of advanced IC products.”
* Mentor Graphics also announced PADS 9.0. Per the Press Release: “This significantly-enhanced release of the PADS flow adds new levels of functionality, scalability and integration … Functionality now integrated in the scalable flow includes the addition of manufacturing and collaboration tools, and the world’s most powerful thermal, signal and power integrity analysis, as well as many core design entry and layout enhancements.”
* Open Core Protocol International Partnership (OCP-IP) announced a new white paper discussing an approach to Performance Analysis of Network-on-Chip Architectures for Video SoCs. Per the Press Release: “The paper describes a typical video SoC system, and the traffic profiles for each of the processing engines providing performance analysis measures of interest. Using the performance analysis measurements provided, companies can easily and quickly
determine the performance of the analyzed system.”
* PDTi announced that SpectaReg.com, the industry's first true SaaS hardware/software EDA tool, has been adopted by Nethra Imaging for the design of their latest multi-core SoC. Per the Press Release: “SpectaReg is an essential web-based register automation tool for software/hardware interface design … Specifications are easily read into the tool and matching hardware logic, hardware verification, firmware,
documentation and more are all rapidly auto-generated from a single source.”
* Physware announced that the PhysWAVE 3D fullwave design tool “has been optimized to assist design of MIMO Antennas for RF front ends and wireless ASICS.”
* Richtek announced a “Worldwide Unlimited License for SmartSpice and Verilog-A” from Simucad Design Automation.
* Signal Integrity Software announced support for the NFP-32xx from Netronome Systems. The companies say they have worked together “to analyze and ensure the signal integrity on all the NFP-32xx high-speed network interfaces … The work performed by SiSoft has resulted in a set of layout guidelines that can be used by NFP-32xx users to accelerate implementation.”
* Silicon Image announced its SiI5923 SteelVine Series 3 Core storage processor and the SiI3723 SteelVine Series 3 Core SATA 1:2 port multiplier. Per the Press Release: “Key applications for these new single-chip solutions include PCs, DVRs, and consumer electronics motherboards, as well as storage enclosures.”
* Solido Design Automation announced a new application for its Variation Designer tool that the company says, “analyzes and solves well proximity effect problems that become major concerns at 90-nanometers and below. The new Solve Well Proximity application allows … designers to proactively address well-proximity effects during the circuit-design stage without area sacrifices or increased design time resulting from other approaches. For example,
in a 90-nanometer power management system amplifier design, guard-banding area was reduced by 95 percent compared to the traditional methodology.”
* Synfora announced PICO Extreme Power, which the company says is “the industry’s first algorithmic synthesis tool to automatically minimize power consumption at the system-level based on a variety of techniques, including automatic multi-level clock gating insertion. Multi-level clock gating enables clock gating to be applied to a computation block in an application accelerator at any level in the hierarchy.”
* Synopsys and Actel announced a “multi-year extension” of their OEM agreement for FPGA design tools. Per the Press Release: “Actel maintains rights to provide Actel-specific versions of Synopsys' Synplify Pro, Identify and Synplify DSP software as part of the Libero IDE.”
* Synopsys announced the DesignWare SATA AHCI host and device digital controller IP for the SATA 6Gbps data transfer rate, as defined in the Serial ATA Revision 3.0 specification.
* Synopsys also announced that its DesignWare DDR3/2 PHY and digital controller IP is “the first DDR3 IP fully verified in test silicon at 1600 Mbps, the maximum data-rate of the JEDEC DDR3 specification.” The company says test chips were manufactured at 65 nanometers.
* Synopsys announced that Exar Corp. has chosen Synopsys as its “leading EDA partner … The Synopsys' Galaxy Implementation and Discovery Verification platforms will be Exar's key design environment for designs at 65-nanometers and below.”
* Synopsys also announced that Infineon Technologies used IC Compiler with Zroute technology “provided a near 100-percent redundant via rate, enabling leading-edge device reliability and allowing Infineon to successfully tape out the lead product of its high-performance automotive 32-bit microcontroller platform in an advanced embedded Flash technology.”
* Synopsys also announced that SMIC is using Synopsys' HSPICE circuit simulator and WaveView Analyzer for design and verification of 65-nanometer and 45-nanometer IP blocks, I/O circuitry, and standard cell characterization flows.
* Synopsys also announced that Fujitsu Microelectronics used the Galaxy Implementation Platform for low power digital electronics and mobile application ICs.
* Synopsys also announced that New Japan Radio Co., Ltd. used IC Compiler's multi-corner/multi-mode capability and enjoyed 2X faster design closure.
* Synopsys also announced that TriQuint Semiconductor is using TCAD Sentaurus device simulation software for R&D on “high-frequency and high-power semiconductor devices targeting mobile handsets, 3G and 4G base stations, Wi-Fi, WiMAX, and defense and aerospace applications.”
* Tensilica announced that SiliconXpress is now an “authorized design center.” Tensilica’s Chris Jones is quoted in the Press Release: "SiliconXpress offers deep understanding of the entire chip design process, so companies can use them as a valuable resource for parts, or all, of their chip designs.”
* Tensilica also announced that TranSwitch Corp. has “integrated two Xtensa customizable Dataplane Processor Units (DPUs) into its recently introduced Atlanta 2000 gigabit-rate communications processor product family.”
* X-FAB Silicon Foundries announced what the company is calling “the industry’s first foundry process for the production of integrated Hall sensor ICs in 0.18-micrometer technology. Its 0.18 micrometer low-power CMOS process, known as XH018, allows the combination of Hall sensor elements with high-voltage devices and Non-Volatile Memory (NVM) options … [enabling] the sensing element to be integrated on the same chip as its control logic and
interface circuitry. Due to its small geometry resulting in high integration density, high magnetic sensitivity can be achieved with minimal parasitic effects.”
There will be a quiz ….
* TSMC announced its iRCX, interoperable EDA data format for TSMC’s 65-nanometer and 40-nanometer technologies:
Per the Press Release: “TSMC collaborated extensively with EDA ecosystem partners in the iRCX initiative, defined the unified format based on TSMC process requirements, worked with EDA partners to implement the new format support in the tools, and closed the loop by qualifying tool accuracy against actual silicon measurements, eliminating data inconsistency, reducing customer tool evaluation time and improving design accuracy … Multiple EDA companies are participating in the qualification program.”
More info: “The iRCX format unifies interconnect modeling data delivery, and ensures data integrity and interpretation. EDA tools which support iRCX format will be able to receive accurate interconnect modeling data from the iRCX files developed and supported by TSMC. Interconnect-related EDA applications, including P&R, RC extraction, EM analysis, power integrity analysis, and EM simulation [will] benefit from iRCX … the first of several interoperable EDA interface formats co-developed between TSMC and its design tool partners as part of the TSMC Open Innovation Platform (OIP).”
Per Shauh-Teh Juang, Senior Director for Design Infrastructure Marketing at TSMC: "iRCX is part of the TSMC Open Innovation Platform [OIP] that includes the Active Accuracy Assurance [AAA] Initiative. This new unified EDA data format provides designers the ability to select qualified EDA tools to match their design needs, improve compliance with TSMC processes, and ensure design accuracy for first time silicon success."
And did you know: “The TSMC Open Innovation Platform promotes timeliness-driven innovation amongst the semiconductor design community, its ecosystem partners and TSMC's IP, design implementation and DFM capabilities, process technology and backend services. The Open Innovation Platform includes a set of ecosystem interfaces and collaborative components initiated and supported by TSMC that efficiently empowers innovation throughout the supply chain and enables the creation and sharing of newly created revenue and profitability.”
Also, you should know: “TSMC's AAA initiative is a broad-based program that encompasses all design ecosystem components. It provides accurate standards for all TSMC partners, EDA vendors, IP providers, library developers, and Design Center Alliance (DCA) members. The standards apply to tools, building blocks, and technologies, including TSMC Reference Flow 9.0, DFM tools, PDKs, design support and backend services.”
* Pop Quiz:
Distinguish between TSMC’s OIP, DAC, AAA, Integrated Sign-Off Flow programs. Your answer should no longer than 500 words in length and must be postmarked by Midnight, 20 June 2009. All responses become the Property of HomeBrewedTools.com and will not be returned to the respondents.
Why you should attend the TSMC Keynote at DAC …
* Apache Design Solutions announced that the Company’s RedHawk has been certified to support TSMC’s iRCX 65-nanometerm and 40-nanometer technologies. In addition, RedHawk is included in the TSMC Integrated Sign-off Flow.
* Azuro announced its PowerCentric low power clock tree synthesis tool has been included in TSMC's Integrated Sign-Off Flow.
* Cadence Design Systems announced the Cadence QRC extraction signoff technology has adopted the TSMC iRCX data format.
* IMEC announced a new and expanded research agreement with TSMC, whereby TSMC will base its extended European research efforts at the IMEC premises. Per the Press Release: “In this way, TSMC can benefit from IMEC’s state-of-the-art clean room infrastructure which is currently been expanded to house the most advanced – often pre-production – semiconductor manufacturing tools, allowing to research technologies ahead of
industrial needs. IMEC and its members can benefit from TSMC’s broad-based technology roadmap and platform expertise, customers, suppliers, and ecosystem partners.”
* Legend Design Technology announced its Model Diagnoser has been selected by TSMC for use in the quality assurance of the company’s standard cell libraries.
* Magma announced that its QuickCap NX has been certified to support the parasitic extraction and modeling accuracy requirements of the TSMC iRCX format for 65-nanometer and 40-nanometer ICs.
* Synopsys announced that TSMC selected Synopsys' Galaxy Implementation Platform for their new Integrated Sign-Off Flow. The new flow is now available for 65-nanometer designs with planned extensions into other process technology nodes.
Looking forward to seeing all of you at DAC in San Francisco in July!
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-- Peggy Aycinena, EDACafe.com Contributing Editor.