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May 25, 2009
Popcorn at DAC, Azuro’s CTS, Lotsa news, Cooley’s War
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor


by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


When I was a kid, we had a copy of Post Cartoons: 1935 to 1945 floating around the house. Me and my brothers and sisters loved that book. We pored over the cartoons for years on end, memorizing them all. So much so that still to this day, family conversations continue to be peppered with references to images and taglines from the book.


Now on the eve of the 46th Design Automation Conference, I find myself thinking repeatedly about my favorite among those Post cartoons. Two guys in shredded clothing are struggling along in the desert, clearly at death’s door. One guy is down on his knees, about to succumb to thirst and starvation, while the other guy is still on his feet, gazing off into the bleak distance and scratching his stubbly neck. The standing guy says to the fallen guy, “Oddly enough, I keep thinking about popcorn.”


That’s how I feel about DAC. Everybody and their brother’s in a lather about the conference. Is DAC down on its knees? Will attendance falter due to the economic downturn? Will there be too few exhibitors, too much expense, too few parties, buzz, or news? Will Europe show up given that late July is their vacation time? What’s the significance that Cadence is back, but ARM is gone? Will Cooley & Co. snicker about reduced attendance, the ratio of academics to industry types, the marketing hype, happy as always to revel in other people’s woes and disappointments?


I don’t know. Somehow oddly enough, I keep thinking about popcorn.


I love DAC. It’s exciting to have so many smart and quirky people all in one place. So many computer scientists, electrical engineers, designers, vendors, barkers, PhDs, marketing & sales folks, PR people, prima donnas from the press, pundits, overpaid corporate executives, caterers, booth talent, academics, industry types, ideas, presentations, keynotes, panels, gossip, chotskies, and Futurists all in one place. I also love San Francisco. It’s my hometown and it’s a great town. Does it get any better than having DAC in San Francisco?


Okay, so yeah – it makes more sense to be upset about everything related to DAC. Budgets, attendance, politics, factions, Cooley, cut-throat competition, etc. But oddly enough, I keep thinking about popcorn. Hope you do, too.


And, I hope I’ll see you at DAC in The City in July.


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Advanced CTS – Azuro’s Campaign


The folks at Azuro are committed to clock-tree synthesis [CTS]. They say their company – founded in the U.K., but now headquartered in Silicon Valley – is pursuing a “fresh and different” approach.


Per Mark Swinnen, director of product marketing: “We’re the only company focused on clock-tree synthesis. No one else has been dealing with the problem, even though the clock is the most important aspect of timing for power in design; 30-to-50 percent is taken up by the clock net alone. It’s baffling that the industry has spent so little time on it, so this is Azuro’s opportunity. While all place-and-route tools have a freebie module for CTS, the industry overall has significantly under-invested in clock design for many years.


“Perhaps that’s not surprising, because the clock problem has crept up on us. Wires need buffers to distribute the signals around, but buffers mean that one transistor sees the signal sooner than others. As chips got bigger, balancing to compensate got more and more complicated. Everybody continued to think it was just about the wires, but the clocks got more complicated, as well. Designs [emerged] with over 100 clocks, highly interleaved with multiplexors to balance things as the clock signals diverged, converged, and re-diverged. As a result, today’s high-end chips have this horribly complicated spaghetti of clock design, with most clocks bumbling along as if you
still just need wires to provide the buffers.


“So traditional clock gating continues, down at the RTL where clock gates are put in based on simple pattern recognition. If a block is not being used – for instance, the video circuitry in a cell phone – you place a switch on that clock net, so nothing moves. It’s an effective technique in particular cases, used ubiquitously in the industry, but it’s simplistic – replacing feedback multiplexors with clock gates, with no idea about placement, timing, or power. But, it only works if you don’t push it too far up the clock tree. At Azuro, we’re saying, Hang on there!


“Our PowerCentric tool inserts the clock tree farther up because it works at the gate level, a better level than RTL. Ours is a more sophisticated gating strategy, advanced clock gating, and is not just about pattern swapping in RTL. PowerCentric has full power analysis and a timing engine built in, allowing you to see the impact of timing, power, and area on the full chip because tool works after placement. Where traditional clock gating is established at RTL, a very restricted view, we provide full detail about the chip, including placement and global routing. Some would argue that our strategy costs power by putting in
additional clock gates, but it actually saves power. We see 25-to-40 percent savings over traditional clock gating.


“Meanwhile, we’re aware that designers all use place-and-route tools that include a CTS module, yet they’re still stuck with 10-to-12 weeks of balancing the clock tree by hand, an intense amount of manual labor. That’s why they are willing to pay for our tool, despite the free CTS module they already have. It’s easy to use and integrates with their place-and-route tools – taking Verilog, LEF and DEF in, and spitting Verilog, LEF and DEF out.


“The integration with those tools is simple and effective, so much so that we’re in the latest TSMC 9.0 reference flow. Think about it. Even though the TSMC flow is based on implementation, analysis and verification tools from all of the large EDA vendors, still we’re in the flow for CTS. That illustrates how important the design of the clock has become – a completely fundamental shift in the industry. It’s no longer enough to just work with ideal clocks and simple wire models, as in earlier generations of design tools. There are too many on-chip variations, and the logic path is too small in comparison to the clock path.


“At Azuro, we’ve solved the problem. People can still use logic synthesis tools that include with ideal timing models, but our customers can use PowerCentric for CTS to get higher performance, lower power, and lower area in their final design. And now, they can expand on that technology with our newly announced Rubix product, which includes a superset of PowerCentric’s features.


“Rubix is a physical optimization tool that optimizes the clock and the logic at the same time. It’s like a puzzle that’s taming these two things at the same time. The beauty of the tool is that it doesn’t require any changes at the front-end or at signoff. Of course, if you’re using Rubix, you don’t need PowerCentric, but we’ll continue to support both products. Gary Smith [Gary Smith EDA] has talked with us and says what we’re doing makes sense, that it’s obviously the right way to go. [Not surprisingly], we’ve already had our first tapeout at 40 nanometers.


In the next few years, we expect all of the tool vendors in the industry will move in this direction, to clock-concurrent optimization. For now, Azuro will continue to make a good business with our CTS tools. It’s a new idea that’s definitely catching on.”


[Editor’s Note: You can learn more about the Azuro technology by reading their 
White Paper]


*************************************


Coming soon to a theater near you


* The Open SystemC Initiative (OSCI) is offering a free, online video tutorial titled “TLM-2.0 in Action: An Example-based Approach to Transaction-level Modeling and the New World of Model Interoperability.”


* Electronic Components & Technology Conference – The event is taking place May 27-28 in San Diego.


* Synopsys Web Seminar – The Lynx Design System will be discussed online on June 3.


* Synopsys is also offering three free online tutorials: “Leveraging Constraint Solver Technology in VCS” and “The VCS Discovery Visualization Environment “ and “New IC Validator: In-Design Physical Verification for Faster Time-to-Tapeout”


* Mentor Graphics User2User – The conference is free to attendees and takes place June 9 in Silicon Valley. The program includes technical sessions and discussion of the company’s technical roadmap.


* Berkeley Symposium on Energy Efficient Electronic Systems – The premier event will take place June 11-12 at UC Berkeley. Speakers will include Jan Rabaey and Chenming Hu from U.C. Berkeley, and Mark Horowitz from Stanford.


* IEEE ICC 2009 - The International Conference on Communication takes places June 14-18 in Dresden


* Denali MemCon – “Beacons of Innovation“ is taking place June 22-24 in Silicon Valley. Speakers include Numonyx CTO Ed Doller, Denali CTO Mark Gogolewski, Samsung VP Jim Elliot, Freescale VP & Sr. Fellow Ken Hansen.


* IEEE IEDM 2009 – The deadline for submission of abstracts for the December 7-9 meeting in Baltimore is June 26.


* EDAC and IEEE CEDA announced nominations will be accepted until June 30 for this year’s recipient of the Phil Kaufman Award for Distinguished Contributions to Electronic Design Automation. The award will be presented at a dinner on November 5 in Silicon Valley.


* ASQED’09 – the first Asia Symposium on Quality Electronic Design will take place July 15-16 in Kuala Lumpur. Keynote speakers will include Synopsys President & COO Chi-Foon Chan, Cadence SVP & CSO Charlie Huang, NXP VP & Head of Research
Hans Rijns, Verdant Electronics President Joseph Fjelstatd, and University of Tokyo Professor Takashi Tomita.


* DAC 2009 – The 46th annual Design Automation Conference will be held in San Francisco the week of July 26-31. Keynote speakers include Synopsys CEO Aart de Geus, Mentor Graphics CEO Wally Rhines, Cadence CEO Lip-Bu Tan, TSMC VP Fu-Chieh Hsu, and
NVIDIA Chief Scientist William Dally. An enhanced User Track has been added to the conference program.


* Hot Chips 21 – The 21st annual symposium takes place August 23-25 on the Stanford Campus.


*************************************


Business buzz


* Artisan Software Tools announced a new sales office in France, with Olivier Casse named Territory Channel Manager for France and the Benelux countries. Previously Olivier was at Monditech, Embelec, LiveDevices, and I-Logix.


* Cadence announced Americo Dias and Daniel Oliveira, students at the University of Porto, Portugal, have won the company’s EMEA design contest. EMEA students are from Europe, the Middle East, and Africa.


* Cayenne Communication announced three new clients: Pickering Laboratories, Triad Semiconductor and ViASIC.


* congatec AG announced the company will add to its design activities in the Czech Republic with a design team acquired from a major competitor.


* DAFCA announced Dennis Shepard has been named CEO. Previously, he was EVP for Talyst, President & CEO of Activate.net, COO for Mercata, and worked for many years at Wan Labs. Shepard studied EE at Lowell Tech Institute, and attended Harvard’s Executive Management Program.


* DAFCA announced a licensing agreement with Per Enge, Sherman Lo, and David De Lorenzo at Stanford’s GPS Research Laboratory. Enge will also join DAFCA’s science advisory board.


* D2S Inc. announced a $9 million second round of funding, led by Benchmark Capital, DAC Ventures, Advantest, and Cadence Design Systems. Per the Press Release, “The company will use the funding for its design-for-e-beam technology … In conjunction with this new round of funding, Nick Pianim, managing director of DAG Ventures,
has joined the D2S board of directors.


* U.C. Berkeley’s Ernest Kuh is being honored by the IEEE with the 2009 Gustav Robert Kirchoff Award for outstanding contributions to the theory and practice in circuits and systems, and for pioneering work in electronic design automation. Paraphrasing the Press Release: With a research and teaching career spanning over 50 years, Kuh’s pioneering contributions have shaped both circuit theory and computer-aided analysis and design of large-scale integrated circuits and systems. His work has included circuit theory and analysis, network analysis, nonlinear and time-varying networks, the lumped parameter delay-line synthesis method, the state space method, and the creation of state equations for nonlinear circuits. Kuh’s work in EDA included fundamental research that led to software for systematic placement of components, developing routers for the connection of pins on early ICs, and the “Building Block Layout” which presented a graphical theoretical method for place and route, which was later refined to include circuit floor-planning and pin-placement
capabilities. His work has led to many start-ups in EDA. Kuh is an IEEE Life Fellow and 1998 recipient of the EDAC’s Phil Kaufman Award.


* EMA Design Automation announced it has acquired DesignAdvance and all of its intellectual property. EMA has hired “the key people responsible for creating and enhancing the DesignAdvance products, including Chandan Aladahalli, cofounder of DesignAdvance. EMA [will] continue development of the DesignAdvance products – CircuitSpace, CircuitProbe, and CircuitPlan.”


EMA President and CEO Manny Marcano is quoted in the Press Release: “The patented technology jointly developed by DesignAdvance and Carnegie Mellon University offers significant productivity enhancements for our PCB design customers.” DesignAdvance President Ed Pupa is also quoted: “EMA is very focused on the PCB design flow, and their close relationship with Cadence Design Systems will allow the team to work within that flow and offer better integration.”


* IEEE CANDE announced UT Austin’s David Pan has been elected President, Stanford’s Subhasish Mitra is Secretary, University of Utah’s Priyank Kalla is Treasurer, UC Santa Barbara’s Forrest Brewer is Past Chair, Cadence’s Lou Scheffer is Publicity Chair, and Rice University’s Farinaz
Koushanfar is Workshop Chair. The CANDE Workshop is held each year in conjunction with ICCAD in Silicon Valley.


* IMEC announced 2008 revenue was 270.16 million euros, of which 44.17 million euros was granted by the Flanders Government. Headcount increased 5% increase over 2007, 1103 fulltime employees, 329 industrial residents, and 189 PhD students, while more than 1,500 conference contributions and publications were produced at IMEC in 2008.


* IPextreme announced its Constellations program, which the company says “provides the business level infrastructure for enabling an open community of independent semiconductor IP companies to collaborate at the sales level by sharing sales intelligence and market wisdom to provide a virtual world-wide sales footprint. Constellations is aimed at solving a problem that has long troubled the semiconductor IP community
– small companies with good technology lack the global sales footprint to compete against larger competitors and are therefore at a structural disadvantage that results in an oligarchic industry structure that rewards the large players at the expense of the small ones.”


* Mentor Graphics Corp. and LogicVision, Inc. announced the two companies have signed a definitive merger agreement pursuant to which Mentor Graphics will acquire LogicVision. Under the terms of the agreement, which was approved by the boards of directors of both companies, LogicVision stockholders will receive 0.2006 of a share of Mentor Graphics common stock for each share of LogicVision, for aggregate
consideration of approximately $13 million dollars. LogicVision President and CEO Jim Healy is quoted: “We are excited about the proposed combination with a successful company like Mentor, and believe that the transaction will allow our stockholders to continue to participate in the potential of the combined entity,”


* Mixel announced it is celebrating the company’s 10th anniversary. The company is a privately held IP provider, and says it has been profitable since it first opened its doors for business.


* MIPS Technologies announced Art Swift has been named Vice President of Marketing. Previously, Swift was president and CEO of Unidym, president, CEO and senior vice president of marketing at Transmeta, COO at Lynuxworks, and vice president and general manager of several divisions of Cirrus Logic. He also held various positions at Summit Microelectronics, Sun Microsystems, Digital Equipment, Bipolar
Integrated Technology, and Fairchild Semiconductor. Swift has a BSEE from Pennsylvania State University, and is co-inventor of three U.S. patents relating to programmable logic architectures.


* MunEDA and NTHU (National Tsing Hua University) of Taiwan announced a strategic partnership and cooperation agreement within MunEDA´s worldwide University Program. MunEDA will provide its DFY software tools to the NTHU EE Department.


* Octasic Inc. announced that Robert Blake has been appointed CEO. Previously, Blake served as vice president at Altera. Prior to Altera, he developed ASIC technology at LSI Logic and Fairchild. Blake has an MBA and a BS in microelectronics from the University of Durham.


* Pyxis Technology announced a $3 million round of financing. Investors include Austin Ventures, CMEA Ventures, Formative Ventures, and KT Venture Group. Pyxis board member Jim Solomon, Pyxcis CEO Phil Bishop, and SpringSoft USA President Scott Sandler are all quoted in the press release and agree Pyxis shows strong
potential for growth.


* Real Intent and Verific Design Automation are both celebrating 10-year anniversaries and a long-term partnership that has spanned the last eight years. Carol Hallett, vice president of World Wide Sales and Marketing at Real Intent, is quoted: “Real Intent congratulates Verific on its 10th anniversary and knows first hand why Verific has had long-term success. We have had a winning
collaboration with Verific over a long period of time and knew where to go when we needed to upgrade to SystemVerilog.” Rob Dekker, Verific’s founder and president, is also quoted: “Real Intent has passed the 10-year mark with breakthrough formal verification software. We are delighted to have played a role in this achievement.”


* Real Intent also announced Katsuhiko Sakano has been named General Manager of Japan. Previously, he served as a Senior Sales Manager at SpringSoft, Encirq and NovaFlow. Sakano also has experience at Cadence, Pacific Design, Actel, Xilinx, LSI Logic, and System Design.


* Silicon Frontline Technology announced its arrival as a new EDA venture, founded in 2005 and funded in 2007. The company was launched by CEO Yuri Feinberg and VP of Engineering Andrei Tcherniaev, who previously co-founded NASSDA (acquired by Synopsys in 2005) and were the original developers of HSIM, the EDA industry's first hierarchical circuit simulator. Feinberg is quoted in the Press
Release: "We founded Silicon Frontline with the goal of moving post-layout verification technology to the next level. We want EDA users to experience what hasn't been possible until now – guaranteed accuracy.”


* Synopsys announced 2Q09 revenue of $336.8 million, a 3.8% increase over 2Q08. The company projected 3Q09 revenue of $342 million to $350 million.


* Synopsys also announced it has acquired the Analog Business Group of MIPS Technologies for $22 million in cash. The companies say the acquisition “expands Synopsys' DesignWare IP portfolio with a new family of analog IP such as A/D converters, D/A converters, audio codecs and power management. It will also add HDMI TX and RX protocols to Synopsys' existing interface IP solution.”


* Tanner EDA announced Greg Lebsack has been named President. Previously Lebsack served as CEO of ASP Global Services, and held management positions at Sprint. Lebsack is a member of the Board of the Technology Council of Southern California.


* Tanner EDA also announced its 20th anniversary, and says the company “has shipped 25,000 licenses of its PC-based electronic design software to 4,000 customers in 67 countries.”


*************************************


Tools & Technology



* Agilent Technologies announced that TSMC certified Agilent’s GoldenGate RFIC circuit simulator for baseband designs targeting TSMC’s 65LP nanometer and 40LP nanometer processes.


* ANSYS and Clemson University announced an agreement under which ANSYS software will be used for engineering simulations at the University’s Computational Center for Mobility Systems, helping “to foster commercial innovation in automotive and other mobility industries, such as aviation/aerospace and energy.”


* ANSYS also announced a coupling of the company’s products with those from Ansoft for multiphysics simulations involving electromagnetic applications. Per the Press Release: “In performing several case studies, ANSYS engineers deployed the electromagnetic effects determined by Ansoft software directly in ANSYS thermal and structural simulation.”


* ANSYS also announced the ANSYS 12.0 software suite for “fast product design and validation in a complete, highly usable virtual environment that captures complex and coupled physical phenomena … while reducing the time and money invested in physical prototype development and testing.


* Apache Design announced Totem, a new analog design tool the company describes as the “first integrated noise integrity (NI) platform ... Totem is a comprehensive platform that incorporates transistor-level noise injection, parasitics extraction, package modeling, dynamic analysis, and design debug in a single-flow environment … It provides cross-probing of analysis results with industry standard circuit
design tools for efficient debugging, fixing, and optimization.”


* Apache also announced that the Computers Division of NEC Corp is using Apache’s RedHawk for SoC design analysis and optimization.


* ASSET InterTech announced its ScanWorks platform for embedded instrumentation was used for signal integrity design validation and circuit board test for Intel’s Xeon processor 5500 series (codenamed Nehalem) and the 5520 chipset.


* Azuro announced the first customer tapeout using its Rubix clock concurrent optimization tool.


* Azuro also announced that Newport Media is using Azuro’s PowerCenter tool for clock implementation on all IC designs at 65 nanometers and below.


* Berkeley Design Automation announced release 2009_05 of its Analog FastSPICE tool. The new release includes: the Mega-Solver matrix solver, Multi-Core capability for up to 4 cores, enhanced Monte Carlo analysis, 64-bit WaveCrave waveform processing, and new licensing features.


* Berkeley Design Automation also announced Panasonic is using BDA’s Analog FastSPICE platform for verification of mixed-signal ICs.


* Berkeley Design Automation also announced that Alvand Technologies is using BDA's Analog FastSPICE Nano SPICE simulator for analog and mixed-signal IP characterization.


* Berkeley Design Automation also announced that Summit Microelectronics\ has selected the Analog FastSPICE Nano SPICE simulator for block-level characterization of its programmable power management ICs.


* Berkeley Design Automation also announced that SiTime Corp. is using Analog FastSPICE unified verification platform, including the AFS Nano SPICE simulator, for verifying advanced timing circuits.


* Cadence announced the Cadence OrCAD and Allegro FPGA System Planner, a tool for designing FPGAs onto PCB systems. The new product was developed by Taray, Inc. and is being sold to Cadence customers through an OEM agreement with Taray. Harris Corp.’s Roberto Cordero is quoted: “Taray’s FGPA I/O synthesis technology … allows us to enter our design intent at the
system level, then … automates the pin assignment over multiple FPGAs all at once.”


* Cadence also announced a collaboration with Virtutech, whereby Cadence Incisive Software Extensions will be integrated with the Virtutech Simics high-speed system-level virtual platform. Per the companies: “The integration will also enable application of the Open Verification Methodology Multi-Language to hardware/software co-verification earlier in the project development cycle.”


* Cadence also announced a system-level verification tool the company says supports the OSCI TLM 2.0 standard: “The new solution natively recognizes TLM 2.0 constructs to automate debugging and analysis, and enables Save/Restart/Reset for managing long runtime test cases.”


* Cadence also announced that PLDA used Cadence Incisive USB 3.0 (SuperSpeed USB) verification IP in its commercial USB 3.0 design IP.


* Cadence also announced that NXP Semiconductors used the Encounter Digital Implementation System, for production of the NXP 45-nanometer PNX85500 TV processor chip.


* Cadence also announced that SANYO Semiconductor Co., Ltd. is using Virtuoso IC 6.1 and the Virtuoso Digital Implementation system to help design analog and mixed-signal products.


* Cadence also announced that BroadLight has standardized on the Encounter Digital Implementation System for design of its Gigabit Passive Optical Network (GPON) semiconductor product. Per the Press Release: “Through rigorous benchmarking and stress-testing, Encounter Digital Implementation System proved the most capable RTL-to-GDSII digital design and signoff solution for BroadLight's highly
integrated GPON devices.”


* Cadence also announced that DiBcom implemented a methodology that led to the tapeout of a “revolutionary programmable platform” called "Octopus," which offers manufacturers a flexible and powerful solution to the problem of multiple standards worldwide for fixed and mobile TV. Cadence says its Low-Power Solutions and Mixed-Signal Solution models were important parts of the strategy.


* CEVA announced fully-functional silicon for the CEVA-TeakLite-III DSP core. The company says initial chips were produced on SMIC’s 90-nanometer process and exceeded 600MHz. Additionally, “the dual-MAC, 32-bit processing architecture enables the core to reach operating speeds higher than 700 MHz in 65-nanometer process.”


* ChipStart announced it will distribute PDTi's SpectaReg on-chip register automation tool which uses a Software-as-a-Service (SaaS) model. Per the Press Release: “With a growing number of point EDA tools becoming available, the need to reform the traditional EDA business model becomes necessary to ensure companies can continue to adopt these point tools without getting buried in hosting support costs
and license management issues. By using a SaaS model, engineering teams can now realize the same benefits for their EDA point tools as other departments in the company do through their business systems engagements.”


* congatec AG announced the Qseven Mobility Starter Kit, a rapid prototyping package for battery-powered, embedded systems. Per the Press Release: “The compact size and low power consumption of Qseven embedded computer modules makes them ideally suited for almost all ultra-mobile, embedded PC applications.”


* CoWare and Renesas Technology announced a collaboration “aimed at delivering better development tools to Renesas’ SH core-based software development community using virtual platforms.” The companies say they will “focus initially on enabling the next-generation multi-Core EXREAL, SH-Navi and SH-Mobile platforms.”


* CoWare also announced a strategic partnership with Carbon Design Systems “to deliver implementation-accurate models of ARM IP targeted for CoWare’s SystemC-based design solutions … The complete portfolio of Carbonized models and model kits for the CoWare environment will be exclusively distributed and supported as part of the CoWare IPO Model Library.”


* Carbon Design Systems also announced it is shipping implementation-accurate models for all variations of the ARM Cortex-A9 MPCore multicore processor and PrimeCells, including the AMBA 3 Interconnect (PL301) matrix.


* DAFCA has extended its ClearBlue line with two new products “to address the broader needs of the SoC and FPGA markets. ClearBlueXpress is a set of tools that automate the process of validating complex SoC/ASIC designs. ClearBlueFPGA is specifically architected to enable systems designers, software engineers and hardware engineers producing complex FPGA designs, ASIC prototyping systems and designs that span multiple
FPGAs to realize the same productivity gains and cost reduction benefits as ClearBlue users.”


* D&R announced an online mechanism that directs qualified leads found through the lead service of the D&R public web portal to a private platform. Per the Press Release: “This platform offers an efficient pre-sales environment for NDA-controlled IP evaluation. Should an actual sale be concluded, the platform assists further in profiling and packaging the client IP configuration, delivering it online through a
secure protocol that conforms to the sales agreement.”


* DOCEA Power announced ACEplorer, “the first ESL software tool that allows designers to model, simulate and optimize the dynamic power and thermal behavior of whole complex systems, either on-chip, on-board or with multiple boards.”


* eASIC Corp. announced the eDV9200. The new product has a “fully programmable ITU-T compliant high definition baseline H.264 CODEC that supports all resolutions including 1080p, 720p, VGA, HVGA, QVGA, CIF and QCIF and variable bit rate (or constant bit rate capabilities.”


* Embedded Alley announced an extension to its Android mobile applications platform to support MIPS processor architecture. Per the Press Release: “The Embedded Alley project enables Android on devices built with the Alchemy Processor family from RMI.”


* eSilicon Corp. announced that it provided ASIC design services, and custom design flow and manufacturing for Creative’s new PCI-Express Sound Blaster X-Fi Titanium Series of Accelerated Audio Processors. The companies say, “For this specific application, eSilicon performed the actual design, package layout and tailored a custom and flexible ASIC design flow to work with Creative’s
existing design and CAD tools flow.”


* EVE announced enhanced hardware debugging capabilities for its ZeBu emulation systems with additional support for SystemVerilog assertions, flexible probes, and access to all combinational signals at run-time.


* EVE also announced it has integrated the latest version of the Xilinx ISE Design Suite 11.1 to its ZeBu emulation platforms, testing the results on large SoC and ASIC designs.


* Extreme DA announced a U.S. Patent No. 7,487,486 which “covers technology used for improvement of design performance and reduction in power consumption and die-size of digital IC designs produced in 65nm processes and below.”


* Fujitsu Microelectronics and TSMC announced an agreement an agreement whereby Fujitsu will expand its 40-nanometer generation logic IC business with production at TSMC's fabs.


* The IEEE and Accellera announced the IEEE has approved the IEEE 1801 "Standard for Design and Verification of Low Power Integrated Circuits." Also known as Unified Power Format (UPF) 2.0, it was first developed by Accellera and is currently supported by multiple vendors worldwide.


* IMEC announced functional 22-nanometer CMOS SRAM cells made using EUV lithography. The 0.099µm² density is a 47% area reduction from the 0.186µm² of IMEC's 32-nanometer cell reported in 2008.


* IMEC also announced the transfer of MemoryVAM (Memory Variability Aware Modeling) – “the first EDA tool for statistical memory analysis” – to Samsung Electronics. IMEC says the tool predicts yield loss of SRAMs caused by DSM process variations.


* IMEC also announced a suite of tools and methods to optimize the mapping of applications on embedded MPSoC platforms. Per the Press Release: “The tools are intended for companies that design multicore platforms for tomorrow's nomadic and multimedia applications. They are offered under a technology transfer or license agreement.”


* Impulse Accelerated Technologies announced its CoValidator tool, which generates FGPA testbenches from C. The new product, in combination with the company’s CoDeveloper tool, “allows FPGA system designers to write, refactor, optimize and synthesize FPGA software and hardware with ANSI C.”


* Jasper Design Automation has recently announced 5 new patents: U.S. Patent No. 7,506,288 for “interactive analysis and debugging of a circuit design during functional verification of the circuit design;” No. 7,437,694 for “identification of certain RTL load signals and values, with their contribution to the proof target;” No. 7,421,668 for “meaningful visualization of properties independent
of circuit design under various conditions;” No. 7,418,678 with “methods for simplifying counters in a circuit design while preserving important implications;” and No. 7,412,674 which “applies the concept of analysis regions to analyze the properties and requirements for a design.”


* Jasper also announced three new proof accelerators have been added to the JasperGold Verification System: Formal Scoreboard to prove the integrity of data transfers across a design, Model RAM to make memories tractable, and Model Multiplier which provided a “formal safe” method for modeling multipliers.


* Jasper also announced that ARM has adopted the JasperGold Verification System, and JasperGold will be placed in all AMD design centers


* LogicVision, in the process of being acquired by Mentor Graphics, announced a “power-aware” version of its ETMemory BIST tool. Per the Press Release: “On-chip memory test and repair is now fully compatible with the … power management approach of using voltage islands to minimize power during functional operation.” LogicVision says the new feature will be available in
June’09.


* Magillem Design Services announced MRV, which helps IC designers manage registers through synchronization and hierarchical description features. Per the Press Release: “MRV visualizes and edits the full project hierarchy … and [can] handle more than 500 different XML files containing memory map fragments.”


* Magma Design Automation announced that the FineSim SPICE tool has been certified by the TSMC SPICE Tool Qualification Program. Per the Press Release: “Designers can now use FineSim SPICE with the TSMC Model Interface (TMI) on any design targeted at TSMC N40 nanometer processes with a higher level of confidence in achieving first-time silicon success.”


* Magma also announced that the Talus IC implementation system has been enhanced to support the Common Power Format (CPF). Per the Press Release: “With the addition of CPF, Talus becomes the first RTL-to-GDSII flow to support both the CPF and the Unified Power Format (UPF). Both formats enable better, faster, low-power IC implementation by allowing specifications to
be captured just once and used consistently throughout the flow. By supporting both formats, Magma offers designers the flexibility to choose the low-power format that best suits their design while also providing advanced low-power design capabilities that minimize power consumption, maximize quality of results and reduce iterations.”


* Magma also announced its Quartz DRC and Quartz LVS 2009.05 physical verification tools. The company says the new releases “increase designer productivity and include functionality improvements for advanced process nodes, including 45/40 and 32/28 nanometer, through optimizations specifically targeted for standard multi-core, multi-CPU computers. The [new version] offers improved compatibility with third-party legacy
physical verification tools.”


* Magma also announced the “Liberate Me” program, which allows customers to test drive Quartz DRC and Quartz LVS at no charge for 60 days.


* Magma also announced that PDF Solutions used Magma's Quartz DRC Physical Verification system to develop a Characterization Vehicle test chip for a “leading semiconductor manufacturer.”


* The MathWorks announced Simulink Design Optimization, which the company says “gives modeling and control engineers the ability to automatically optimize Simulink model parameters. Together, Simulink Design Optimization, Simulink, Simscape, and Simulink Control Design provide a powerful modeling and control design environment that enables engineers to create plant models, calibrate these models with test data, and
use them to design, simulate, and optimize control systems.”


* The MathWorks also announced that Argonne National Laboratory reduced the simulation time of models built with the Powertrain System Analysis Toolkit (PSAT) by using Parallel Computing Toolbox and MATLAB Distributed Computing Server. Per the Press Release: “This project requires large amounts of simulation for nearly 2,000 vehicles in order to prioritize and allocate grants for companies to develop
more fuel-efficient cars.”


* Mentor Graphics announced a new verification platform targeted at HDTV products. The new release includes HDMI and DisplayPort interfaces


* Mentor Graphics also announced Volcano Vehicle Systems Architect (VSA) for AUTOSAR-based vehicle system design flow from architectural exploration to implementation. Per the Press Release: “VSA improves quality, reliability, time to market, and cost advantages by facilitating the use of standard interfaces and components based on AUTOSAR.”


* Mentor Graphics also announced the VeSys electrical/wire harness design tool for harness makers and off-road and specialty vehicle manufacturers. The VeSys 2.0 suite is data-centric. All information is stored within an integrated database rather than individual files, allowing “VeSys 2.0 suite to be more readily adapted to different organizational and IT requirements.”


* Mentor Graphics also announced the Olympus-SoC platform, which includes “a flexible architecture for automated multi-voltage design flows, advanced techniques for power reduction in complex clock trees, and concurrent optimization of leakage and dynamic power, timing and signal integrity across multi-corner multi-mode (MCMM) scenarios.”


* MIPS Technologies announced Cavium Networks used the MIPS MIPS64 architecture in the its OCTEON II Internet Application Processors.


* MIPS Technologies also announced that Mavrix Technology licensed the MIPS32 4KEc synthesizable processor core for its next-generation media processor designs.


* MIPS Technologies also announced “it is the first company to certify a multi-core system on EEMBC MultiBench benchmark software. MIPS certified its MIPS32 1004K Coherent Processing System.”


* MontaVista Software announced MontaVista Linux 6 for embedded Linux development. The new release includes Market Specific Distributions, based on a common framework and optimized for hardware platforms, MontaVista Integration Platform, built on open source technology, MontaVista Zone Content Server, and MontaVista DevRocket 6, an Eclipse-based IDE.


* The MOSIS Service announced multi-project wafer (MPW) runs using IBM’s 0.18 micron high voltage process. Per the Press Release: “MPW runs are ideal for organizations wishing to quickly trial a design without incurring the high costs of a fully engineered process run.”


* R3Logic announced US Patent No. 7,526,739 for “Methods and systems for computer aided design of 3D integrated circuits”. Per the Press Release: “The patented invention comprises both the method of defining a 3D technology file that can incorporate one or more 2D wafer technologies corresponding to different tiers in a 3D stack, and that of defining a 3D hierarchical structure for functional blocks within
a 3D system.


* Panasas and Ansys announced performance enhancements in ANSYS 12.0 when combined with Panasas’ ActiveStor Series 7, 8 and 9. The combined toolset from the two companies “enables the use of a parallel file system for I/O of simulation data files [and] overcomes performance bottlenecks related to conventional network attached storage … Customer field testing has demonstrated improvements
in turnaround time of more than 200%.”


* Real Intent announced Ascent 2.2.1 and Meridian CDC 2.5, updated versions of the company’s products. The Ascent verification” tool has lint and sequential formal analysis features, and now includes performance improvements, local scope analysis, and inline pragma support. The Meridian CDC clock-domain crossing verification tool for ASIC and FGPA design, now includes shell model support for hierarchical
analysis, improved structural and formal reporting, and enhanced GUI debug features.


* S2C Inc. announced TAI Player Pro software version 3.1, which includes the Multi-FPGA Internal Logic Analyzer (ILA) to increase design productivity through simultaneous debugging of designs partitioned to multiple FPGAs. Per the Press Release: “TAI Player Pro software enables users to compile SoC designs … on FPGA prototypes from RTL, debug the mapped designs on FPGA, and link the prototypes to ESL models in
simulation.”


* Samsung Electronics announced a memorandum of understanding with IMEC to collaborate on technologies for green radios. Research topics will include cognitive reconfigurable radio baseband and millimeter-wave wireless communications technologies.


* Satin IP Technologies announced QIP metrics for on-the-fly design quality monitoring. The company says it has been working with the Quality of Electronic and Software Intellectual Property (QIP) Metric standard working group of the IEEE Design Automation Standards Committee (DASC) since the standard was donated to the IEEE by VSIA.


* Silicon Frontline Technology announced two new products: F3D (Fast 3D) for fast 3D extraction and R3D (Resistive 3D) for 3D extraction and analysis of large resistive structures like power devices. Per the Press Release: “The products incorporate patent-pending 3D technology to deliver a Guaranteed Accurate solution for full-chip, post-layout verification. They work in industry standard flows allowing simpler
adoption and quicker closure, with guaranteed accuracy, of the post-layout verification loop.”


* SilTerra Malaysia and South Sea Semiconductor Ltd. announced joint development of V-Tr FET technology for low RDS(on) Power MOSFET devices. Per the Press Release: “V-Tr FET technology features a narrow trench gate electrode with a cell density of 488 million per inch square. The technology is realized using existing production ready 0.16 micron tool set.”


* The SPIRIT Consortium announced approval of the SystemRDL language “for design and delivery of registers to be used in IP blocks within electronic designs. SystemRDL semantics support the entire life-cycle of registers from specification, model generation, and design verification to maintenance and documentation.” Ralph von Vignau, SPIRIT President, is quoted: “The SPIRIT Consortium
gratefully acknowledges the contribution of SystemRDL to The Consortium by Denali. This contribution provides the industry with a language to comprehensively describe registers and has extended the IP-XACT register descriptions extensively.”


* SpringSoft announced comprehensive SystemVerilog Testbench (SVTB) debug support in the new release of Verdi Automated Debug System, which the company says includes a “new structured message-based method for automating SVTB debug so engineers can quickly comprehend complex testbench behavior … The system also provides an interactive simulation mode that can be used to pinpoint issues that are not revealed
through logging.”


* SpringSoft also announced its Laker process design kit (PDK) has been certified for UMC’s 65-nanometer manufacturing technologies.


* Super Talent Technology announced the MasterDrive RX family of Solid State Drives (SSDs) with capacities up to 512GB.


* Synfora announced that Olympus Digital System Design Corp. has selected Synfora’s PICO Extreme to develop advanced image processing SoCs.


* Synopsys also announced new multicore technology within the VCS functional verification tool. Per the Press Release: “VCS multicore technology delivers a 2x improvement in verification performance by … distributing time-consuming activities across multiple cores. VCS multicore technology combines the speed-up from parallel computation with the industry-leading Native Testbench (NTB) compiler.”


* Synopsys also announced its CustomSim circuit simulation tool. Per the Press Release: “The simulation technologies of NanoSim, HSIM and XA have been unified into a single circuit simulation solution with added multicore capabilities delivering up to 4x performance improvement for large analog and mixed-signal circuits.”


* Synopsys also announced, in conjunction with the previous news items, the latest release of its Discovery Verification Platform, with features for enhanced “verification productivity, new multicore simulation technologies, native design checks, and comprehensive low power verification capabilities.”


* Synopsys also announced that the Solar Energy Research Institute of Singapore has adopted Synopsys' Sentaurus TCAD to support its solar cell research and development programs.


* Synopsys also announced the IC Validator DRC/LVS tool for in-design physical verification and signoff for designs at 45 nanometers and below. Per the Press Release: “Architected to deliver the high accuracy necessary for leading-edge process nodes, superior scalability for efficient utilization of available hardware, and ease-of-use, IC Validator provides a step up in physical designer productivity … through
in-design verification, stream-out reduction, incremental processing, automatic error detection and fixing, and near-linear scalability across multiple CPU cores. IC Validator has been included by TSMC in the company's EDA qualification program of DRC/LVS starting from 28 nanometers.


* Synopsys also announced that NVIDIA has adopted Synopsys' IC Validator physical verification tool. Per the Press Release: “By achieving near-linear scalability, such as the 20x speedup observed by NVIDIA using 25 CPUs, IC Validator provides accelerated time to tapeout.”


* Synopsys also announced that MediaTek is using the PrimeTime SI tool for static timing analysis on 65-nanometer designs.


* Synopsys also announced that Toshiba has signed a multi-year business agreement naming Synopsys as its “key EDA partner” across the Toshiba semiconductor design flow. But what does that really mean? Inquiring minds really want to know.


* Synopsys also announced 175 semiconductor companies are using PrimeTime PX for dynamic and leakage power analysis.


* Takumi Technology Corp. announced a patent issued by the U.S. Patent and Trademark Office for effective proximity effect correction methodology, and a corresponding patent by the State Intellectual Property Office of the People’s Republic of China. The US patent, #7,458,056, covers technology in improving the quality and accuracy of OPC.


* Tanner EDA announced Version 14 of Tanner Tools Pro and HiPer Silicon, which the company says takes advantage of 64-bit Windows platforms version and runs up to 25% faster than the 32-bit version.


* Tanner EDA also announced that Proteus Biomedical is using Tanner’s EDA tools for CMOS and MEMS design applications.


* Teklatech announced FloorDirector 2.0, which “bridges the gap between analog and digital design optimization. [Targeted at] wireless design, noise sensitive digital ICs, automotive and aerospace chips with strict EMI/EMC compliance requirements. [The new] technology makes it possible to optimize the dynamic content of digital ASIC power grid currents in an automated flow and immediately view results in the frequency
domain. This makes a range of optimization targets accessible to designers.”


* Toshiba announced a new laptop with a 512G solid state drive (SSD) using Multi Level Cell NAND flash memory technology. The computer weights 2.4 pounds and is less than an inch thick. The company says it has “increased SSD capacities on laptops from 32GB to 512GB in just 2 years.”


* TSMC announced that it has qualified a 0.18-micron embedded flash (embFlash) process technology family, which includes a baseline 1.8-to-5 volt standard process, an ultra-low leakage process, and specific automotive-qualified embedded Flash IP.


* Virage Logic announced its AEON non-volatile memory tool has been qualified on TSMC’s 65-nanometer LP process. The company says AEON “enables IC manufacturers to embed NVM … and design a truly multi-programmable product.”


* Virtutech announced that Freescale Semiconductor signed an “extended license” for the Virtutech’s Simics simulation platform; Freescale’s Networking Systems Division says Virtutech is its “preferred simulation partner” for the Freescale QorIQ processors.


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A new Cold War DAC versus DATE


Thanks to John Cooley, an ugly Cold War has flared up between DAC and DATE. Now the suggestion is floating around out there that between these two conferences, DATE must go so DAC can stay.


Although John Cooley himself has never been to DATE, it appears important to him that the European conference be ridiculed. He’s published several blistering posts about the conference this year – one in the run-up to DATE’09 and one after the conference ended in April. Clearly Cooley & Co. are convinced that DATE is done.


And how do Cooley & Co. feel about DAC? Will they be publishing nay-sayer posts in advance of DAC, hints that attendance will be down, that no one cares about DAC anymore? Will nay-sayer comments be published after the conference has ended, as well? If not, Cold War conspiracists will conclude that DATE must die, so DAC can survive.


Currently, the various DAC Committees are working overtime to complete plans for DAC’09, set for San Francisco in late July. Just as hard as the various DATE Committees were working earlier this year to complete plans for DATE’09 in Nice in April. No doubt, the DATE Committees are already working on DATE’10, just as the DAC Committees will start working on DAC’10 the day after DAC’09 concludes.


The DAC and DATE Committees are busy year round. They may consider themselves too busy to respond to Cooley‘s War, but they really should. Because there’s a simple and honorable way to put the conspiracy theories to rest. If the organizers of the two conferences are sincere in supporting each other, they should issue a joint statement of commitment to both DAC and DATE. So far they have not.


Instead, the public silence from the two camps is a roaring confirmation that the acrimony between the European DA community and North American DA community is alive and growing. Perhaps we should thank Mr. Cooley & Co. for simply making it clear.


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-- Peggy Aycinena, EDACafe.com Contributing Editor.


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