February 02, 2009
You Can Never Have Too Much Performance
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor


by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


Introduction


The old adage says “You can never have too much of a good thing”. Of course as Midas learned, this is not always true. However, when it comes to improved computer performance, the adage is clearly true. When I was in college, students would keypunch a deck of cards, leave them at a window and come back the next day to see the results of their computer run. If they made a simple keypunch error or a coding error, they lost a day. This made them check their work very carefully. Today, most computer programs, certainly word processing and spreadsheets, are highly interactive. Many programs that were once batch programs that ran over night now run in a matter of minutes if not
seconds. In the mechanical CAD world, solid modeling that was once characterized by long batch runs has been interactive for more than two decades. Knowing that one can get results almost instantaneously influences behavior. Users are probably less careful and more likely to try investigating alternatives.


As we know, in the EDA world there are still critical programs that run for hours or for days, even when the program is run on the largest computers or on a compute farm. Making matters worse, these programs need to be rerun again and again as changes are made in the data. The collective time spent waiting for computer results is considerable impacting costs and time-to-market.


There are many ways to improve performance. Most software programmers believe that you should be able to improve performance of almost any code at least by a factor of two by simply rewriting portions of it. Faster computers with more memory certainly improve performance. Special purpose processors and co-processors contribute to faster turn-around time as does sharing the workload over multiple cores in a single computer or over a number of computers.


One area that continues to draw the attention of vendors and users alike is simulation. Improvements of two or three x while welcomed are insufficient to convince users to switch tools or change methodologies. By the time they switch over their design flow and carry out all the testing that the change entails, the old system will likely have improved by the same amount. Quantum leaps are what are desired.


At CDN!Live last April Cadence announced immediate availability of advanced "turbo" technologies within the Virtuoso Spectre Circuit Simulator, its analog SPICE circuit simulator with comprehensive foundry support. The turbo technology boosts performance while ensuring silicon accuracy, enabling designers to verify their complex large analog designs, such as phase-locked loops, analog-to-digital converters, transceivers, clock data recovery circuits and power supply circuits. Virtuoso Spectre Circuit Simulator is part of Virtuoso Multi-Mode Simulation, the company’s complete solution for circuit simulation. The press release included favorable comments from early users at Renesas
Technology and Maxim Integrated Products. This was followed up by release of Spectre RF Turbo Technology in the third quarter and by the announcement of Virtuso Accelerated Parallel Simulator in December.


I had an opportunity to discuss the Cadence solutions with Nebabie Kebebew, product marketing manager.


I like to start these interviews with a brief biography.

Sure! I have been with Cadence now for almost three years as a product marketing manager covering right now our SPICE line simulation products. Today we are talking about the Accelerated Parallel Simulator (APS), our latest release. I have been in EDA for quite some time, over 10 years, working on various tools not just custom simulation tools but tools for digital implementation, test and so forth.


Where were you before Cadence?

Synopsys. I have touched the Big 3 as people in this industry refer to Mentor, Cadence and Synopsys. I was at Synopsys for ten years and prior to that with Mentor.


Were you always on the marketing side or did you start on the development side.

I started out as an application engineer. Then I held a management role for application engineering at corporate on the product development side. I have a lot of experience on the product development aspects of it. Eventually, I went into marketing. Prior to that, I was a design engineer. That’s where all the design background comes for ASICs.


These days you are in the SPICE simulation area. What is the set of end user problems or challenges that these products are trying to address?

Customers want the ability to get their verification of transistor level design of SOC designs done within their verification budget. So they can meet their time-to-market. Particularly with analog design, accuracy is the number one when users are dealing with analog blocks and IP. When you go to full chip, it is more a case of verifying the functionality of the circuit, EMI analysis, device checking; those types tf things. Fast SPICE technology meets those requirements. For SPICE simulation of analog blocks and IP accuracy is extremely important along with getting as much performance as possible to meet the time-to-market. This is becoming more and more challenging because designs are
more complex. They are packing more capabilities into the analog blocks and IP. There is also the fact that we are dealing with smaller geometries. There are also a lot more parasitic devices that have to be taken into account to make sure that it meets the accuracy requirement. That exasperates the simulation particularly the transient simulation. Performance and accuracy have been the requirements from our customs, without of course compromising silicon quality.


As I understand Cadence offers what it calls Multimode simulation, a collection of different simulators.

Cadence has been very active in this market for many years with SPECTRE which has significant customer usage, particularly in analog based design that delivers the accuracy that customers require. As we go into more complex designs, complex analog designs, the need for more performance without sacrificing accuracy increases. What we have done over the last year, 2008, is really address this requirement by first starting off with Spectre with Turbo technology. We have taken the same use model and basically put a performance boost into Spectre. Moving forward we have continued our investment in performance improvements. That’s where APS comes into play. Again, customers want to be able to leverage the multicore computer platforms that are becoming available to analog designers. Leveraging that is very much what customers want to do. That’s where we have introduced our new product with a completely new simulation engine. We have taken key parts of Spectre technology combined with proprietary parallelization and developed and released a product into the marketplace in December. The other aspect of parallel simulation is being able to handle post layout design. I touched on this earlier when I mentioned parasitics. Post layout design means that there is going to be a huge amount of design data, particularly from the Rs and Cs. Not only handling the transistor level design but transistors with this amount of parasitics is a must have. Accelerated Parallel Simulator, ASP for short, is able to tackle that on multicore compute platforms without sacrificing accuracy and still maintain the same use model. As you know, whenever a new product is introduced, the concern is how much of a disruption will it be to my existing deign flow. There is always that adoption barrier. One of the key things we focused in addition to adding no compromises on accuracy was to make sure we maintained the customer use model so that they are able to just plug it in and insert their design netlist and see performance improvement. We have worked with several key partners to validate the
technology on many, many designs. Customers have seen significant performance boosts. Internally we have gotten many, many customers deigns to validate the technology.




Last year Cadence introduced the Turbo technology. What does that involve?

We have taken the Spectre simulator from an accuracy point of view and enhanced the numerical algorithm to improve performance, the transient analysis portion of the simulation. In addition to that we also added RC reduction capability that takes a large network of Rs and Cs and reduces it to improve performance. That is on top of the turbo technology. Again, the same use model. What we have done is to enhance the different settings that we have to improve performance versus accuracy underneath the covers so that customers see a performance boost compared to Spectre. With our suite of simulators (Spectre, Spectre with Turbo and APS) we are
addressing the different analog design segments. For the smaller analog designs, users continue to use Spectre. As their designs get larger and more complex, turbo technology comes into play. For large, high end designs, that’s where APS comes in.


1 | 2 | 3 | 4  Next Page »


You can find the full EDACafe event calendar here.


To read more news, click here.



-- Jack Horgan, EDACafe.com Contributing Editor.




Review Article Be the first to review this article


Editorial
Peggy AycinenaIP Showcase
by Peggy Aycinena
IoT: the A-to-Z of TechTalk at ARM TechCon
More Editorial  
Jobs
Sr. Field Applications Eng. - San Diego or Sunnyvale, CA for Real Intent at Sunnyvale, or San Diego, CA
SW Developer Physical space for EDA Careers at San Jose, CA
Sr. R&D Engineer for Real Intent at Sunnyvale, CA
Sr Memberand MTS for EDA Careers at San Jose, CA
Technical Writer (synthesis, place and route) for Mentor Graphics at Wilsonville, OR
Sr Software Development Engineer for E-System Design, Inc. at San Jose, CA
Upcoming Events
Virtualize! at 1333 Bayshore Highway Burlingame CA - Oct 30, 2014
LA/OC Expo and Tech Forum at The Grand Event Center 4101 E Willow Street Long Beach CA - Nov 6, 2014
3D ASIP Conference at The Hyatt Regency San Francisco Airport 1333 Bayshore Highway Burlingame CA - Dec 10 - 12, 2014
2015 European 3D TSV Summit January 19-21, 2015 Grenoble (France) at MINATEC innovation campus 3 parvis Louis Néel Grenoble France - Jan 19 - 21, 2015



Click here for Internet Business Systems © 2014 Internet Business Systems, Inc.
595 Millich Dr., Suite 210, Campbell, CA 95008
+1 (408) 850-9202 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and EngineeringTechJobsCafe - Technical Jobs and ResumesGISCafe - Geographical Information Services	MCADCafe - Mechanical Design and EngineeringShareCG  - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy