February 02, 2009
You Can Never Have Too Much Performance
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| by Jack Horgan - Contributing Editor
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The old adage says “You can never have too much of a good thing”. Of course as Midas learned, this is not always true. However, when it comes to improved computer performance, the adage is clearly true. When I was in college, students would keypunch a deck of cards, leave them at a window and come back the next day to see the results of their computer run. If they made a simple keypunch error or a coding error, they lost a day. This made them check their work very carefully. Today, most computer programs, certainly word processing and spreadsheets, are highly interactive. Many programs that were once batch programs that ran over night now run in a matter of minutes if not
seconds. In the mechanical CAD world, solid modeling that was once characterized by long batch runs has been interactive for more than two decades. Knowing that one can get results almost instantaneously influences behavior. Users are probably less careful and more likely to try investigating alternatives.
As we know, in the EDA world there are still critical programs that run for hours or for days, even when the program is run on the largest computers or on a compute farm. Making matters worse, these programs need to be rerun again and again as changes are made in the data. The collective time spent waiting for computer results is considerable impacting costs and time-to-market.
There are many ways to improve performance. Most software programmers believe that you should be able to improve performance of almost any code at least by a factor of two by simply rewriting portions of it. Faster computers with more memory certainly improve performance. Special purpose processors and co-processors contribute to faster turn-around time as does sharing the workload over multiple cores in a single computer or over a number of computers.
One area that continues to draw the attention of vendors and users alike is simulation. Improvements of two or three x while welcomed are insufficient to convince users to switch tools or change methodologies. By the time they switch over their design flow and carry out all the testing that the change entails, the old system will likely have improved by the same amount. Quantum leaps are what are desired.
At CDN!Live last April Cadence announced immediate availability of advanced "turbo" technologies within the Virtuoso Spectre Circuit Simulator, its analog SPICE circuit simulator with comprehensive foundry support. The turbo technology boosts performance while ensuring silicon accuracy, enabling designers to verify their complex large analog designs, such as phase-locked loops, analog-to-digital converters, transceivers, clock data recovery circuits and power supply circuits. Virtuoso Spectre Circuit Simulator is part of Virtuoso Multi-Mode Simulation, the company’s complete solution for circuit simulation. The press release included favorable comments from early users at Renesas
Technology and Maxim Integrated Products. This was followed up by release of Spectre RF Turbo Technology in the third quarter and by the announcement of Virtuso Accelerated Parallel Simulator in December.
I had an opportunity to discuss the Cadence solutions with Nebabie Kebebew, product marketing manager.
I like to start these interviews with a brief biography.
Sure! I have been with Cadence now for almost three years as a product marketing manager covering right now our SPICE line simulation products. Today we are talking about the Accelerated Parallel Simulator (APS), our latest release. I have been in EDA for quite some time, over 10 years, working on various tools not just custom simulation tools but tools for digital implementation, test and so forth.
Where were you before Cadence?
Synopsys. I have touched the Big 3 as people in this industry refer to Mentor, Cadence and Synopsys. I was at Synopsys for ten years and prior to that with Mentor.
Were you always on the marketing side or did you start on the development side.
I started out as an application engineer. Then I held a management role for application engineering at corporate on the product development side. I have a lot of experience on the product development aspects of it. Eventually, I went into marketing. Prior to that, I was a design engineer. That’s where all the design background comes for ASICs.
These days you are in the SPICE simulation area. What is the set of end user problems or challenges that these products are trying to address?
Customers want the ability to get their verification of transistor level design of SOC designs done within their verification budget. So they can meet their time-to-market. Particularly with analog design, accuracy is the number one when users are dealing with analog blocks and IP. When you go to full chip, it is more a case of verifying the functionality of the circuit, EMI analysis, device checking; those types tf things. Fast SPICE technology meets those requirements. For SPICE simulation of analog blocks and IP accuracy is extremely important along with getting as much performance as possible to meet the time-to-market. This is becoming more and more challenging because designs
are more complex. They are packing more capabilities into the analog blocks and IP. There is also the fact that we are dealing with smaller geometries. There are also a lot more parasitic devices that have to be taken into account to make sure that it meets the accuracy requirement. That exasperates the simulation particularly the transient simulation. Performance and accuracy have been the requirements from our customs, without of course compromising silicon quality.
As I understand Cadence offers what it calls Multimode simulation, a collection of different simulators.
Cadence has been very active in this market for many years with SPECTRE which has significant customer usage, particularly in analog based design that delivers the accuracy that customers require. As we go into more complex designs, complex analog designs, the need for more performance without sacrificing accuracy increases. What we have done over the last year, 2008, is really address this requirement by first starting off with Spectre with Turbo technology. We have taken the same use model and basically put a performance boost into Spectre. Moving forward we have continued our investment in performance improvements. That’s where APS comes into play. Again, customers want to be
able to leverage the multicore computer platforms that are becoming available to analog designers. Leveraging that is very much what customers want to do. That’s where we have introduced our new product with a completely new simulation engine. We have taken key parts of Spectre technology combined with proprietary parallelization and developed and released a product into the marketplace in December. The other aspect of parallel simulation is being able to handle post layout design. I touched on this earlier when I mentioned parasitics. Post layout design means that there is going to be a huge amount of design data, particularly from the Rs and Cs. Not only handling the transistor level
design but transistors with this amount of parasitics is a must have. Accelerated Parallel Simulator, ASP for short, is able to tackle that on multicore compute platforms without sacrificing accuracy and still maintain the same use model. As you know, whenever a new product is introduced, the concern is how much of a disruption will it be to my existing deign flow. There is always that adoption barrier. One of the key things we focused in addition to adding no compromises on accuracy was to make sure we maintained the customer use model so that they are able to just plug it in and insert their design netlist and see performance improvement. We have worked with several key partners to
validate the technology on many, many designs. Customers have seen significant performance boosts. Internally we have gotten many, many customers deigns to validate the technology.
Last year Cadence introduced the Turbo technology. What does that involve?
We have taken the Spectre simulator from an accuracy point of view and enhanced the numerical algorithm to improve performance, the transient analysis portion of the simulation. In addition to that we also added RC reduction capability that takes a large network of Rs and Cs and reduces it to improve performance. That is on top of the turbo technology. Again, the same use model. What we have done is to enhance the different settings that we have to improve performance versus accuracy underneath the covers so that customers see a performance boost compared to Spectre. With our suite of simulators (Spectre, Spectre with Turbo and APS) we are addressing the different analog design
segments. For the smaller analog designs, users continue to use Spectre. As their designs get larger and more complex, turbo technology comes into play. For large, high end designs, that’s where APS comes in.
Is the parallelization technology for a single computer with multiple cores, for multiple computers, for multiple computers each with multiple cores, or all of the above?
We are taking a phased approach. We started off with Turbo technology and now we have APS. The first phase of APS addresses the ability to run and improve performance on a single machine with multiple cores. That is an easier problem to solve right away. We looked at that because computers with multiple cores are more cost effective. Now, moving forward, we are also looking at what people in the industry call distributed performance, distributed processor performance where we are going to introduce technology that enables our customers to run their simulation on multiple computers with multiple cores. That is a little bit more of a difficult problem to solve. There is latency between
the machines. You want to take that into account and make sure that the added performance is significant enough compared to the latency between the machines, the handshaking that goes on among the machines. The APS product we introduced in December is for a single machine with multiple cores. Currently, it runs up to 8 cores. Sixteen cores was something we were targeting but because if some hardware limitations, sixteen cores are not fine tuned as of yet. We are now delivering only up to eight cores. The next phase is going to be distributed processing.
Do you have a timeframe on that?
That’s something we are working on. We have not set a particular timeframe yet, but we are looking at 2009.
As you increase the number of cores, does the performance go up linearly?
In theory we would like it to be linear.
The release of 7.1 is where we introduced ASP. We launched it in December and released it on January 14th. Spectre is the SPICE solution for analog blocks and analog IPO. All this is under the umbrella of AMS Design Analog and Mixed Signal. All these technologies share the same infrastructure and the same device models and serve the RF, Mixed Signal and Analog markets.
The phased approach of introducing performance improvements started with Spectre Turbo for Analog Design, then Spectre Turbo for RF Design and now APS. APS delivers parallelization, basically multithreaded. It is scalable. So, the question you asked earlier was “Is the performance linear with the number of cores?” In theory we expect it to be linear but there is always some latency involved with multicore. Our customers have seen significant performance improvement versus single core and linearity depending upon the design and the machine they are using. It runs anywhere from three to five times across the cores when executing on 2, 4 and 8 cores. Just to give you a
perspective in the kind of performance we are seeing; for an ADC (analog to digital converter) at 65 nm, customers have seen a factor of twenty-nine speed up. I should say that we have seen internally on a customer design this type of performance compared to Virtuoso Spectre. We just put out a press release where customers saw a significant performance improvement using this technology. In fact in one case, they were able to catch errors that would have required a silicon respin.
APS serves customer for post layout verification. There is no change in use model, the same accuracy. Now they are able to these large designs with large amounts of Rs and Cs and simulate them.
Multithreading. You may have heard the term out in the industry in reference to many types of simulation capabilities. Full parallelization is the key. What this means is that it is not just parallelizing the device analysis which is a significant portion of the circuit. It is also parallelizing the solution of the circuit. That is what we refer to as complete multithreading which is parallelizing about 90% of the simulation operation. In particular as design get larger, the matrix of the circuit gets larger. The need to parallelize the portion of simulation is huge with respect to improving performance.
From your standpoint working in this industry, what are the key challenges that you hear for custom simulation?
For any type of simulation, it is accuracy, time and cost and as you have said the ability to fit into an existing design flow with minimum disruption.
Exactly! Without disruption! Adoption barriers are very important. Particularly, if they are working on one version of their design flow, they do not want the disruption that changing to a new tool or new solution will likely entail. So being able to take a solution and being able to plug it in is very important. That is one of the reasons we have made sure that for Spectre Turbo, Analog and RF we have maintained the same use model for the customers. All that is involved is really just invoking that tool but with the same settings, same netlist, same device models and so forth.
Is APS targeted more at Analog, RF or Mixed Signal?
It is targeted at analog and RF functions. When we are talking about what kind of designs, it is analog and RF blocks, IP and subsystems because one of the key benefits is the capacity if being able to simulate large block designs that customers were not able to simulate before within a certain timeframe. In terms of the types of designs, it ranges anywhere from PLL (Phased Lock Loops), data converters, memory IP, power managing circuits, high speed IOs, transceivers.
Is the license for the product node locked or floating?
We should not be talking about node lock or floating. It is really how the customers access this technology. The new product is within our Multi-mode Simulation (MMSIM) solution with token licensing. Customers that have the tokens are able to check out the technology and run it. A token based scheme.
Is there a price point for this product?
We have a price list available to our customers.
Is it available to me and my readers?
No. It is a two dimensional price based upon device count as well as the number of cores.
Can you give me a price range?
We can not give out any dollar figures. It is available to customers through our account teams.
Who does Cadence see as its competition in this arena?
Good question. There are a lot of big companies out there that tout parallelization. Most of these are partial rather than complete parallelization. Then there are some firms that are emerging that also tout parallelization. There are a whole set of EDA companies that are out there.
Do you have a sense of what market share Cadence has in this area?
In analog, in custom simulation, in …? The APS serves the analog simulation market.
In that market segment then.
The market breaks down in two analog simulation aspect and characterization. We have over 45% market share.
Does that make you number one?
Who is number two and three?
I think Synopsys is next followed by Mentor Graphics.
Do you have any sense for the dollar figure for this market?
I can not comment at this time.
Any closing remarks for my readership?
Cadence is committed to the SPICE simulation in general mixed signal SPCIE simulation. 2008 was the first phase with Turbo and APS. We are continuing to invest significantly in this area not just in the SPICE simulation but in mixed signal verification. We will be rolling out some key pieces of technology to enable customers to their deign and verification
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TI reports financial results for 4Q08 and 2008
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TI also announced it is making reductions in employment because demand has continued to weaken with the slowing economy. Employment will be reduced 12 percent through 1800 layoffs and 1600 voluntary retirements and departures. Charges for these employment reductions will be about $300 million. Annualized savings from these reductions, plus those announced in October for the restructuring of the company's Wireless business, will be about $700 million after all reductions are complete in the third quarter of 2009.
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Mentor Graphics Extends High Level Synthesis Leadership with Acquisition of Agility Design Solutions Inc. C Synthesis Suite
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ATopTech Closes Successful 2008, Reaches Revenue Milestone
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-- Jack Horgan, EDACafe.com Contributing Editor.