January 12, 2009
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
| by Jack Horgan - Contributing Editor
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Before we begin with the usual interview, a few words are in order about 2008. A detailed analysis will be forthcoming in our Quarterly report after the firms release their financial results for the last quarter. Unlike the Frank Sinatra song, 2008 was not a very good year for EDA or for that matter for few other sectors of the economy. As is well known, as the Big Three go, so goes EDA. Without the financial results for the last quarter, perhaps the best way to characterize the industry is by their stock prices.
Synopsys stock price followed the NASDAQ closely. Mentor Graphics’ stock price rose dramatically when Cadence made an offer to acquire them on June 17th at a 30% premium over the closing price the day before. And, of course, the price dropped back down when the proposal was withdrawn on August 15th. At the end of January Cadence stock dipped after the company missed Wall Street's fourth-quarter revenue expectations and guided the Street lower for 2008. On October 15th several top executives at Cadence including CEI Mike Fister resigned. On October 22nd Cadence announced review of revenue recognition which was completed by December 12th. These events had significant impact on
Cadence’s stock price. More details appeared in our Third Quarter Review currently seen on this website.
The Big 3 have significantly different views on the upcoming quarter. Cadence is forecasting a 50% drop in revenue next quarter compared to the first quarter in 2008 and a drop of around 17% for next year versus the current year. Mentor Graphics sees a 5% drop in revenue in the next quarter versus the year ago quarter. For fiscal 2009, Mentor Graphics expects full year revenues of approximately $815 million, less than the $879 million in the previous fiscal year. Synopsys, the most bullish of the three, forecasts a 6.7% year-over-year increase for the next quarter.
The economy is impacting every one. If sale of consumer goods (cell phones, TVs, cameras, computers ..) are down and they are, this will impact many EDA end user companies, who will likely downsize. For example, on January 7th Intel made a preliminary announcement that its fourth quarter revenue would be 23% below the fourth quarter last year, 20% below the previous quarter and $500 million below its forecast as a result of further weakness in end demand and inventory reductions by its customers in the global PC supply chain. Similarly on December 4th, AMD announced that it expects revenue from continuing operations for the fourth quarter to be approximately 25 percent lower than
third quarter 2008 revenue of $1.585 billion, not including process technology license revenue. They stated that the decrease was due to weaker than expected demand across all geographies and businesses, particularly in the consumer market. In addition to reduced demand for their product, end user firms may have suffered considerable losses in their investment portfolios.
One can argue that this is precisely the time for end users to acquire more tools aimed at driving productivity. But if the end users already have all-you-can-eat contacts with the ability to mix and match product licenses, that opportunity may already be built in.
In November Calypto Design Systems Inc. announced that the latest
version of SLEC™ supports fixed-point datatypes and system-level memory interfaces commonly used in wireless, video and image processing SoC designs. Product lines SLEC for functional verification and PowerPro for power optimization are based upon based on Calypto’s patented sequential analysis technology. I had an opportunity to discuss the products, technology and the market with Calypto CEO Tom Sandoval
Would you provide us with a brief bio?
Sure! My background is mainly in semiconductors. I started out as a designer myself. I moved into sales and marketing. I also ran LSI’s worldwide engineering organization. I actually spent 10 years at LSI Logic prior to coming here to Calypto. My background is in digital design as well as support and development of methodology in digital design.
Would you tell us about the formation of Calypto?
The original thesis of the company was developed with the founders and venture capital. The idea was to take sequential analysis capability and see if there was a way to take that to a useful product. Originally, there was certainly the idea that sequential analysis could be taken in a number of different directions to support digital design. The folks decided to initially concentrate their efforts on using sequential analysis for formal verification of digital circuits at the system level. Our original SLEC product was able to take a system level model written in C, C++ or SystemC and verify that the model is in fact equivalent to an RTL implementation. There were many naysayers
early on that thought that the technology would not be able to scale in terms of the size of the functions. The reason for that is, of course, as you start increasing the state-space, it becomes a bigger and bigger problem and it becomes difficult to constrain the memory size that you have to address. With the technology we have in place here, we have been able to do that.
The second thing the company did was we took that sequential analysis technology and applied it to power. We can analyze, in this case, an RTL model using our sequential analysis technology and determine where we can instantiate clock gating within the design. We have basically two product lines: our verification product line that I was describing earlier and our power product line.
If I have my dates right, the company was founded in 2005 and you joined them in 2006. What attracted you to Calyoto?
The company was originally founded in December 2002.
Like I said, 2002.
When I joined the company in January 2005, they were just moving from the state of being involved in technology development to actually having product that was being sold and marketed into potential customer base. What attracted me to Calypto was the fact that they were doing something very different from other EDA companies. If you are going to get into the EDA market, your products have to be in a space that does not compete with the Big Three. I felt that because the approach was unique and because they were going off to tackle a problem that had not tackled before that it would be an interesting challenge and I also found that the technology was solving real problems that needed
to be solved.
You have been at Calypto for a few years now. Were there any major surprises?
Let’s see. I guess coming from a semiconductor environment and going into EDA, one of the biggest surprises was the lack of openness that certain companies are willing to expose adopting new technology. In some cases market leaders that you would expect would be open to new technologies being absolutely closed to looking at new things and continuing to do things as they always had.
Is that because they have their own internal tools?
I think some companies have an inherent personality for things different, always pushing to ensure that their designers are in fact always working with the latest and greatest tools as opposed to companies that are so concerned with cost and with risk that they tend not to be that interested or that open to adopting new ways of doing things.
The risk-reward ratio is not favorable for their business model?
Or it could be favorable to their business model but some of them still sit pat. They have a nice share of the market and they are more concerned about maintaining that share of the market than growing it.
What do you see as your biggest challenge now at Calypto?
I think the challenge for all of us in EDA is twofold. First of all, the business model that has been developing over the last several years really driven by the Big 3 has made it increasingly difficult for small companies that are technology driven to justify a spend based upon a value proposition as opposed to a business proposition. In other words when the Big 3 go off and try to cut deals, they are cutting deals based upon putting together a good business proposal as opposed to pushing a particular technology that can make a difference to the customer. The second challenge I think for our business is actually the economic climate we are facing. Are companies going to be willing to
spend additional money to adopt new technologies that could make a dramatic difference in how they are designing while at the same time being concerned about keeping their costs down and maintaining their employee base?
Going back to your comment on the business model, is the business proposition where the vendor has ten different products but if the customer makes a major commitment, then the customer can mix and match over the term of the agreement to meets his changing needs?
Yeah. This idea rather than emphasizing a value proposition associated with each product and the technical advantages of each product, you are dealing more with the business aspects as you described where we are going to give you everything in our portfolio that will allow you (as you said) to mix and match according to your needs and requirements. This pretty much dilutes the value proposition associated with each technology and each product. Whereas as a startup when I am off talking to customers, what I am trying to do is convince them that the specific technology I am delivering has a need and we can satisfy that need with the technology.
How do you convince or persuade prospects that your products do what you claim they do?
Again, I think one of the things that drew me to Calypto was the sheer fact that we are driving methodology and introducing products that do not fit into the same slot as the products that perhaps other guys are driving to the market. Out SLEC product is able to verify a system level model versus an RTL model. No other company in the world offers that capability. We are very unique in that way and our customers recognize that. As a matter of fact, if you look at the high level synthesis world where we are providing verification for the likes of Cadence, Forte and Mentor, customers really see us as the de facto standard formal verification tool. When it comes to power, again we deliver
a very unique value proposition in that we are the company that can take in a customer’s RTL and produce power reduced RTL that looks identical to the original RTL with the inclusion of additional logic to reduce power. By delivering a unique capability we are able to avoid any competition with the big deals or situations, where customers are focused more on business aspects rather than technical aspects. At some companies it is interesting that the CAD organizations are focused on the business aspects of EDA. Perhaps our biggest challenge is dealing with companies who look at the larger companies to potentially develop the same sort of things we have and get it for free.
How big a company is Calypto?
We have about 70 employees?
What about your revenue stream?
We do not publish anything in terms of our revenue. We are still a private company.
How do you demonstrate to a prospect or how does a prospect convince himself that your products do what you say they do?
There are a number of ways. On the verification side, we have some customers who actually put bugs in their design. We have to basically find those bugs. In some cases, the customer will tell us in fact here is the RTL and here is the system level model, please verify it without knowing that there is a bug in it. That’s one way. Another way is we simply find a bug. The customer looks at it and thinks there is no problem between the system level model and the RTL and just wants to see that it runs through our tool. In fact that happened just last week with a major high level systems company. On the power side, it is a little bit easier to demonstrate the value proposition. The
customer provides us with RTL. We run it through our product and we use power analysis to verify how much power we actually save.
Is that verification performed using commercially available 3rd party tools?
Exactly! In the case of power, we do not have a power analysis capability today. So we want to make sure that there is a power analysis tool out there that is saying the same thing, that in fact we are reducing power. So we use generalized third party tools, for that matter we do not do the analysis, the customer actually does it.
Calypto has two sets of tools. Does one account for a greater percentage of revenue than the other?
The two sets of products are the SLEC and PowerPro families of products. Today, because SLEC has been in the market longer, SLEC is the dominant product from a revenue perspective. But we think that PowerPro actually serves a larger market. PowerPro serves essentially the RTL market. Anybody designing RTL is potentially a customer for PowerPro. So we think eventually PowerPro will be a higher revenue base for us. Both product, however, are very important. The PowerPro product use power reduction to create new RTL. We also use our SLEC products to verify that PowerPro has not in fact changed the functionality of the RTL.
Does Calypto sell direct or through distributors?
We do both. Across North America we have direct sales as well as in Europe, central Europe. We have distributors in Israel, Taiwan, and the Nordic region of Europe.
What about Japan and China?
Japan is direct. We have A KK in Japan. Currently we don’t sell or actively market our products in China.
Is that just a matter of time and resources?
I think it is a matter of time. The rest of the world offers enough opportunity to keep us busy. I think we will allow the company to grow at the pace it needs to grow.
Would you give us an expanded view of the two product lines? I believe there are multiple modules in each one.
Our SLEC System product can essentially verify that a system level model is in fact equivalent to another system level model where the second model is perhaps refined in some way from the original model. That refinement is reasonably common and is done when customers have high level synthesis flow. You have the original C model and then you create a new C of system model that incorporates some of the data types and some of the requirements to actually get the best QoR out of high level synthesis. That is the first place where SLEC Systems plays. The SLEC System product contains a C level model, I should really say a system level model (C, C++ or SystemC), and compares it to an RTL
model that is generated from a high level synthesis product. Doing that, we effectively create the bridge between the original model and RTL and thereby eliminate the need for customers to re-run all of their system level simulation at the RTL level.
Our SLEC RTL product allows customers to verify that two RTL model are equivalent. The uniqueness of SLEC RTL is that those two models that we can verify can in fact have sequential differences. One model can have additional pipeline stages instantiated. Or it could have re-timing done at the RTL level. It could have a new finite state machine or be a new micro architecture, where you want to verify at the pin level of the model of the block that the models are equivalent. We can verify that those two models in fact have the same functionality. It is very different from other formal verification products in the market, where you are relying on a one-to-one mapping of registers between
the two models. We do not rely on that.
Our third SLEC product is called SLEC PG. What it is able to do is verify that the input to PowerPro product and the output of our PowerPro PG product are equivalent. What PowerPro CC does is essentially take in an RTL model. It does a sequential analysis of that RTL and generates new RTL that has new constructs instantiated in the RTL that downstream tools convert to clock gates, thereby reducing dynamic power. PowerPro does that without increasing area and in any way impacting performance. The new RTL looks identical to the original RTL with the new constructs that are very clearly delineated in the new RTL. If you look at the product lines, what we are essentially doing is using
sequential analysis to a) create a whole new generation of verification products and b) attack power in a very different way then it has been attacked before. That is by looking at the sequential operation of a design and figuring out where you can shut off parts of that design to reduce dynamic power.
You said you tried to position these products so that you do not compete with the Big 3. Are there any other companies out there that compete with either SLEC or PowerPro?
In the verification space there are other companies. There are no potential competitors large or small. In the power space there are companies that will make suggestions on changes that you can make in the RTL. But they mainly base that on doing pattern matching or based on looking at simulation traces. What we do is a functional analysis, a sequential functional analysis and actually make changes to the RTL to reduce the power. Nobody else has that capability.
Calypto has third party relationships with companies such as Forte. Would you comment on these relationships?
Yes. With Forte, we essentially provide the formal verification for their high level synthesis product. They take in a SystemC model that incorporates all of the data types and structures that are required for the Forte tool. We take in all that information and essentially verify that the SystemC model and the generated RTL that comes out of the Forte tool are functionally equivalent. That relationship is a few years old now. It is a very close relationship. I think that we and Forte have both pushed the high level synthesis capabilities into the Japanese market, in particular. Almost without exception every large electronics company in Japan designing complex SoCs today are using our
solution for high level synthesis.
We also have a relationship with Mentor Graphics, virtually along the same lines. Catapult is their high level synthesis product that takes in C or C++ models and produces RTL. Again, they have certain requirements, data types and certain things that customers need to have in their C models in order to obtain the maximum QoR. We take in the C model and resulting RTL model and verify that they are equivalent.
We also have a relationship with Cadence in two areas. In the high level synthesis area, Cadence has a product called C-to-Silicon. It can take in a SystemC model and product an RTL model. We provide the verification for that product. We are also partnered with Cadence in the RTL synthesis area where PowerPro and RTL Compiler have a seamless interface and allow the two tools to ensure that we work the PowerPro and produce a power reduced RTL and then take that RTL through the RTL Compiler. If there are any enables that might impact timing that RTL, then it can take care of that timing issue. That could occur with high performance design. What we have done is to invent a flow with
Cadence that assures companies that are designing high performance circuits that PowerPro will deliver a low power solution without impacting any kind of critical path that they might have.
All of these relationships have been beneficial to us as well as to our partners.
What are the prices points of these products?
PowerPro has a list price of $295K. SLEC System has a list price of $250K and SLEC System HLS is a $50K add-on to the System SLEC price.
For those prices you get one node lock license, a one year time based license. It is generally not node locked. It is for a specific area of use. So a floating license for a specific area of use.
Do these product run on a single CPU or on a compute farm?
The tool runs on a specific machine. They could run on any machine in a computer farm. One CPU.
Calypto has recently announced some new functionality.
Yes the recent SLEC2 announcement is really an announcement associated with further expanding the types of designs that SLEC can handle. In particular, we can now support six point data types and system level memory interface. Those types of constructs are increasingly common in wireless and image process design. What this essentially does is that it expands our ability to support customers using high level synthesis. Some examples are things like Fast Fourier transforms, Solomon decoders and the support of a couple of other functions like AC window s and external memories. These are particular interesting to folks design video type applications or products that go into video type
In general where (type of company, geography, type of application) is the suite spot for Calypto?
High level synthesis is used across a number of different applications. It is used in wireless, in video imaging and in processing applications. Anyone using high level synthesis today would be a potential customer for us. Our power product is really ubiquitous requirement across any SoC being designed today. As far as PowerPro is concerned, we have customers designing networking products, wireless products, and consumer products. Really, across the whole gambit of electronics. So anybody using a SoC or designing a SoC, is a potential PowerPro customer. SLEC, as I said, is mainly focused on the high level synthesis.
When people use PowerPro, they also use SLEC for verification of the PowerPro output. SLEC CG would be that product.
High level synthesis is used by firms taking an ESL approach to design and architecture.
Yes. As I mentioned earlier, the methodology is becoming the methodology of choice across really every major Japanese electronics company. There is some adoption, growing adoption, occurring today here in the US. Europe also has really embraced high level synthesis and ESL flow.
That was going to be my question. Have you seen growth in ESL adoption over the last several years?
Most definitely! It has been tough getting the right movement going in some companies. Some of that is because of you look at the transition from gate level design to RTL design, companies had sort of essential CAD organizations that took on the responsibility of helping to change methodology across the company. With the push for efficiency in companies designing SoCs, those organizations have been reduced dramatically. So what we find is that some companies that still have some sort of central CAD function are more open and in fact adopt high level synthesis or ESL approaches much more quickly and effectively than companies that don’t. We run across companies where a particular
design group is interested in high level synthesis but they have the pressures of actually getting the product out that competes directly with their ability to change their methodology and sort of move the ball forward in terms of efficiency and capability.
Some industry analysts have been predicting for several years that this year will be the year for ESL.
The marketing pitch for ESL is very attractive. The question is “How real is ESL? Is it ready for prime time production?”
There have been enough tapeouts, over 100 tapeouts, using high level synthesis tools, ESL methodology. It has been borne out that ESL is a better way to go. I think one of the things slowing it down is that ability to drive verification solution that added to the benefits off simply using high synthesis. That’s where we come in. We have some studies that show and some customers that say that if the efficiency improvement using high level synthesis over just straight RTL design is X, but then if you introduce a formal verification solution, you can see 4X to 10X improvement.
I am sure you recognize and the industry recognizes that although design is resource intensive, verification is even more resource intensive. If you can do something not only to help the design side but also the verification side, then you have a real winner. That’s where ESL is moving to.
Where is Calypto moving to?
On the verification side, we are going to continue to improve the capabilities of SLEC in order to be able to take on and take in larger and larger and more complex models from a system perspective and from an RTL perspective. On the power side, we still have a number of different things that we can do to improve power in a design. Because we use sequential analysis and essentially build within our tool a database that represent the function very interesting things to improve power for our customer. We have a long ways to go before we reach the end of the capability.
I have no more questions. Do you wish to add anything?
From a company perspective what is important in EDA is not to be a company that can do something, have a product that can do something, 10x faster or improve QoR by so much. What you really want is a product and the basis for a product that changes the game and does something different. If you look at what we are doing here, we are creating product that do something differently and that complement products that are coming out of the larger EDA firms. For example, having a SLEC type capability for high level synthesis, creates another or an expanded value proposition for the customer to adopt high level synthesis. On the PowerPro side by doing the things we do to RTL, it raises the
attention to power in our customers and also it is complementary to the downstream tools people have and our competitors have. In fact, it drives the further use of these products. Beyond not competing, having products that are complementary to the big guys is also very critical.
The top articles over the last two weeks as determined by the number of readers were:
gEDA Project and Linux Fund partner to boost gEDA/PCB usability The gEDA Project is pleased to announce that it has partnered with Linux Fund in a fundraising effort targeted to expedite development of gEDA's flagship PCB layout program "PCB". Within this partnership, expert gEDA/PCB developer DJ Delorie has agreed to implement a set of enhancements designed to upgrade PCB's usability and utility for electronics designers, making it an attractive open source alternative to commercial PCB design tools. With this project, gEDA/PCB joins the VectorSection DWG interpreter project as part of
Linux Fund's growing open engineering and hardware initiative.
NXP Announces Appointment of Richard L. Clemmer as CEO
NXP Semiconductors, the independent semiconductor company founded by Philips, announced the appointment of Richard L. Clemmer as President and CEO. Mr. Clemmer succeeds Frans van Houten who is leaving NXP. Mr. Clemmer, 56, currently a member of NXP’s Supervisory Board, was most recently CEO of Agere Systems, the former semiconductor company of Lucent. At Agere he implemented a strategic and operational turnaround that ultimately resulted in an $8 billion merger of equals with LSI.
Prior to Agere, he served as chief financial officer of Quantum Corporation where he led the implementation of the first Silicon Valley tracking stock and the $2 billion merger with Maxtor Corporation.
Dolphin Integration announces four times faster VHDL-AMS simulation with SMASH™
DOLPHIN Integration announced the immediate availability of an update to SMASH 5.11 which delivers up to a four-fold acceleration of VHDL-AMS simulation speed compared to previous releases for complex models using vectors and matrices. SMASH was already up to 10x faster than alternative solutions.
Atrenta CEO to Deliver Keynote Address at the 22nd International Conference on VLSI Design
224 Ajoy Bose, chairman, president and CEO of Atrenta Inc., , will deliver a keynote address at the VLSI conference on January 7, 2009. The VLSI conference is a forum for researchers and designers to present and discuss various aspects of VLSI design, electronic design automation, enabling technologies, and embedded systems.
AWR Boosts Asia Pacific Sales Reach
AWR, expanded its relationship with Rohde & Schwarz, one of the world’s leading test equipment manufacturers, to provide expanded sales channels for AWR products such as Microwave Office® in China, Taiwan, Singapore, and Malaysia. The expanded sales distribution partnership will boost AWR’s presence and the use of its software in the Asia Pacific region, and takes effect immediately.
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-- Jack Horgan, EDACafe.com Contributing Editor.