September 29, 2008
SiP or System-in-Package
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| by Jack Horgan - Contributing Editor
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For several years I have been writing about the alphabet soup (SoC, FPGA, PCB and IP) that is the EDA arena. This time I decided to look at SiP or System-in-Package, which some see as an alternative To SoC and some see as a complement to SoC. I had a chance to discuss SiP and IC packaging in general with Keith Felton who describes himself as “the product marketing person at Cadence with the enviable job of being responsible for IC Packaging and System-in-Package technology.” We talked about what SiP is, who uses it, what challenges it address and what the benefits are.
Would you provide us with a brief biography?
I’ve been with Cadence for 10 years in a product marketing role. Initially I was focused on PCB but for the last 7 years I focused solely on IC packaging and then System-in-Package as we brought out our first SiP solution a couple of years ago. Before that I worked at Viewlogic for a couple of years, where I worked on their high speed PCB solution. At the time it was called ISIS. Prior to that, I spent 8 years in Europe working for a company known as Racal-Radac. They later got bought by Zuken. When I was at Redac-Zuken for those 8 years, I was responsible for their PCB product, known as Visula. Before I got into EDA, I was a design engineer for a wireline telecom company in the UK
that got acquired by Northern Telecom.
Would you give us an overview of IC packaging and SiP and how they related to SoCs, PCBs, …?
First of all, you have the traditional IC packaging. Typically in IC packaging you are taking a finished chip that has been fabricated, the wafer has already been sliced and diced. You are literally putting it into the package. You are designing the package as a physical layer entity. You obviously have to capture the layer connectivity between the correct pins on the chip and the correct balls, bumps, pins on the package. Then it is pretty much a straight constraint driven place and rout environment. That is where Cadence has been for quite a number of years. It is an Alegro package design solution. It has been pretty much focused on package layout construction for what I call
backend chip whether those are analog, RF, SoCs, ASICs or maybe even memory chips. It is a matter of taking one or maybe more chips and assembling them together in usually the lowest cost package with the smallest form factor, bearing in mind such things as signal integrity.
When system-in-package came around, it differentiated itself in that what you are doing is actually mixing not just the chips but also discrete components together in a package usually to form some sort of subsystem. Let’s call it a chip set within a single package rather than have individual packages on a PC. Typically early SiPs were very common in the wireless communication space, where, for example, you want the complete CDMA solution. If you were Apple building the next iPhone, you do not want to have to construct a CDMA front end out of multiple chips because that is not your area of expertise. You want to buy a single package that is in fact the wireless front end for a cell
phone and just have that in a single package, connected by the appropriate connections to the package and presto, you now have a cell phone. The wireless space, predominantly battery powered technology handsets or some other forms of wireless devices, has by far the largest influence on the SiP. This is the market, where the IC company needs to provide the largest value add to its customers. And of course they want to sell all of their chips. They do not want you to buy different baseband chips or different power amplifiers. If they can combine all of the functionalities for a wireless device in a single chip, then it is not only easy for their customers, the system companies, to consume
that function but also it means they sell basically all their chips in one package. So they maximize their ASP. The reason they do it as a SiP rather than a SoC is that, first of all, SoCs have a long engineering timeline and they need significant volume to recoup NRE. That is always a challenge in the wireless market where technology standards are changing so often that silicon really does not have a long lifetime. They are always changing some part of the system. That is one of the reasons why people are turning to system-in-package, a combination of multiple chips together with discrete as oppose to a SoC implementations. The other area which tends to be more predominant is that when
you do a SoC, you have to pick one process to do that SoC in. When you are talking about analog, RF and wireless, you are talking about multiple processes and multiple process nodes. If you are doing a power amplifier, for example, you might want to be silicon germanium or gallium arsenide rather than CMOS. It is hard to try and develop a mixed single SoC when you have to pick one technology to implement. Of course, it is always a compromise for the other areas. You have the problem with that. That hinders size, performance, cost and other factors. As I have said, technology is changing so rapidly that the lifecycles of products is pretty short. You are always updating one of the chips. In
the wireless front end system there are new carrier standards like 3G coming. You want to add the latest in streaming video, voice features or something like that. Most companies look at system-in-package as a really effective way of integrating multiple functional pieces of silicon together in a very cost effective and efficient space. That does bring about some challenges. One of them is co-design. If you need to integrate multiple chips in the same package, you really need to affect the layout of each chip so that they can interconnect and interoperate together optimally. You can not just take a handful of disparate chips and throw them together in one package and expect them to have an
efficient implementation. You have to do what would be co-design, which, in a nutshell, is to edit the IO tag ring of each die in the package so that they can connect together in the most efficient fashion. So co-design is almost a mandatory requirement for anyone doing system-in-package.
In addition to cell phones, what other applications would likely use SiPs?
Another very common area for SiP is in memory. When you look, for example, inside your SanDisk compact flash card in your camera, you will find SiPs all stacked together. That is including the memory controller. You will find a number of discrete components down on the substrata of that package. Unbelievably that is all in something as thing as an SD memory card. There are four to five dies on that little guy and that includes the microSD memory card. They still fit four to five dies inside of those. Another area is things like the world of multimedia processors, where you are looking at something in an HD set-top box and where you have the actual ASIC itself for processing the
digital input and converting it to HDMI for the output; you know something like 7.1 Dolby. Often because of the amount of power required, they will use a system-in-package or a package-on-package which you would call a derivative of SiP. That is where you take a set of memory chips and stack them together in a package. Let’s say that there is a center package and you set that directly on top of another package with direct package-to-package interconnect. Then you have what is called a package-on-package. The reason they do that is, as you know, the memory market is a commodity market. You can never tell exactly in what form factor your memory chip will be supplied. Memory suppliers are
always changing processes to optimize yield and reduce cost. As I said, it is a commodity market. If you try to design a memory chip directly on top of your processor, there is a high degree of likelihood that the footprint of the memory chip is going to changing slightly depending on who is supplying you. Let us say it is a Samsung. Samsung could change production to a new technique halfway through the production. They still supply you with your 2G memory chip but it has slightly different pin-out or form factor. So trying to design what is a commodity and changes rapidly is difficult. So what they try to do is ask Samsung to send them packaged memory chips. Let Samsung worry about the
changing form factor but put it into a standard JDEC package. Then the company will integrate the package on top of their own package using standard JDEC footprint. They know that the pins and signal names are going to be in the same location.
Then you have areas such as medical where people are using SiPs. It is a pretty common methodology for getting the level of technology required. I am thinking about implementing biomedical devices such as pacemakers and defibrillators. As you can imagine, they are fairly small. Often they are not much bigger than a small matchbook. Yet they need to have a high degree of functionality, operate on a very low power and, of course, if you mount chips together inside a package, then the interconnect distances between those chips are very small. We are talking about a few tens of micros when you have chips together inside a SiP and where the interconnections between the chips are almost
completely contained inside the SiP with very few external interfaces. Obviously the external interfaces are like the sensors connected to the heart for defibrillator and cabling that goes to the battery unit that powers the device. But other than that, most of the functionality is going on in the SiP and because the chips are so close to each other, you can use low power drivers and receivers.
So you could end up with a very efficient solution not only for power consumption but also it generates very little em, very little electromagnetic interference, because you are really running at such low voltages. In the medical device area, most every type of biomedical implant you have has multiple chip sets in that solution. Plus, of course, having all of the chips together in a SiP means that once the SiP is tested, it is a pretty robust unit. All of the silicon is there inside a hermetically sealed package. It is nice and robust.
You referred to JDEC.
That is a standard body that defines the physical characteristics such as shape, size and pin locations of packages. Every IC package that you commonly use today goes back to a JDEC standard.
In addition to rapidly changing technology what else is going on that makes the design of chips more complex or challenging today as opposed to say 18 months ago?
One thing, of course, is low power. Preliminarily, it is due to the fact that, if you have a handheld unit, your want maximum battery life. But that aside, as you might have heard, a lot of people today have green initiatives. Companies want to leverage the fact that their products use less power than the competitors’ products. Therefore, there is less of an imprint on the environment, carbon dioxide emission for example. If you are going to start designing for low power, then the problem you have to tackle is concerned with the power delivery network. How do you get the power from the source efficiently to the chip so that you minimize the amount of lost power due to inefficient
delivery methodology or due to the fact that you are delivering the power at the wrong impedance and therefore you are going to have to deliver more power because a lot of it is going to be wasted? Low power is another big challenge and that brings about the need to think about designing your power delivery supply system within the package. The PCB that the package sits on is also part of it. You need to design your power delivery network so that, first of all, you can provide sufficient power (of course, you can say that this is easy, as you can always crank it up) but secondarily and apart from sufficient power, you have to supply if efficiently. Do not oversupply and no do not
undersupply. Make sure you can provide just the right amount of power that the chip requires. Next you have to look at stability, which happens to be the killer, because stability is keeping the power supply at a steady state voltage within a tolerance, that’s a ripple level, as the chip switch. So as the chip functions not everything in the chip is on at the same time. Different sections are switching on and off as different current demands for the package and the PCB. The trick is to develop your power delivery network structure in the package so that you supply the chip with the power that it requires, no more than it requires and no less and do that in an efficient manner so that the
size of the package is as small as possible. That is one of the really big tricks because historically, when people build a package, they quite often over engineer their power delivery network so that the packages ends up bigger than it needs to be. The problem is that you have a lot of wasted power. The chip is fine, it functions great but you are over delivering the power. The problem is that you are wasting the power. There is a lot of leakage in the package. In today’s world of battery powered devices, people go shopping the look for EnergyStar efficient TV’s and refrigerators. The same holds for electronic subsystems. Companies are advertising that their network router that you
plug into you home actually consumes less power than the competitors’ router. The whole notion of being power friendly or green so to speak is another important aspect that is different to a world of three or four years ago.
You asked about other ones. The other one is high speed. If you look at the speed in which we are able to send data around in a system, two or three years ago we were talking about PCI Express Generation 1 at 3 1/8 Gigabits/sec. Now we are talking about 6+ Gigabits/sec as being fairly common. People are introducing things like 10 Gigabit Ethernet. When we have got this exponential rise in speed of signals that brings a whole new set of problems in terms of being able to design efficiently for bit error rates, to make sure that you meet various standard protocols that are required in these sorts of systems. Now almost all high speed interfaces are serial interfaces or SERDES devices.
PCI Express is a very good one. There are other very common ones out there like SATA. The big challenge there, of course, is in maintaining the integrity of those signals, to get a bit error rate that is within the specification of the interface. If you look at PCI Express Gen 1 or Gen 2, they will tell you that between the transceivers you need to be able to pass data with no more that a certain number of dropped bits per million bits. So you need to be able to design and simulate that as you are constructing the package, to be able to look at eye diagrams, to be able to document and validate that you are actually meeting the PCI Express spec. The reason for that is that when you plug
into a system, where you are talking to another transceiver that is PCI Express compliant, you will know that the system will function because you have designed your parts of the system to meet that detailed spec. That puts a lot of strain on the designer because we are caught in a plug-and-play world today. The whole idea of having these well designed interfaces is so that you can plug product from vendor A into a backplane from vendor B and providing they both claim that they meet the spec that is well documented, the system should function. That is a big challenge for the design engineer because he has to do simulation at the physical level, which means extracting interconnect models
and performing detailed SPICE level functional simulation to actually prove that he is meeting the spec.
Are the people who work with SiPs package designers or just designers that happen to choose SiP to implement a given design?
It is both. You have two kinds of camps. You have the IC company who is deciding how they are going to bring their technology to market. So very often the company will make the decision about how they want to package their silicon from whatever constraints they have, whether it is time-to-market, performance, cost. Then you have what is called packaging foundries and test companies that specialize in doing package construction. Here we are talking about people like Amkore Techncology, ASE Inc, and Stats, companies who have been for many years manufacturing the packages and doing the assembly and test of the packages. Think of a fabless model. People will come to these companies and
say “I’ve got these chips. I want to put then into a package. These are my goals, what do you suggest.” The package company would say “Given your goals and boundary conditions (TTM,. cost, volume, etc.), we would recommend an implantation like this.” It could be a SiP, a package-on-package, or many different things. Then you get the other side of the spectrum, the IC companies, the bigger companies; we are taking about STMicroelectronics, Texas Instruments, Qualcomm, and so forth. These guys have a lot of experience in packaging. They know that the packaging can influence their ability to win a certain market. They decide themselves how they want to do the package and
often design most of the package. Then they hand the package over to the assembly and test company and say “This is my design. This is how I want it. I have looked at it from a signal integrity and power point of view. It meets my specs. What I need you guys to do now is optimize it for yield. Go in there and do whatever you need to do to improve the yield. The basic blueprint has been set by me.”
In the ever difficult to define typical case, is package design a one person effort, a small team, a large team?
Good question. Compared to a chip team you are talking about a totally different kind of resource model. Where you might have 50 engineers working on the chip that go into a SiP, you are likely to have 3 or 4 people doing the SiP itself, doing the actual SiP implementation. You are talking on average about between a 5 to 1 and a 10 to 1 difference between the size of the chip design team and the SiP design team.
What does Cadence offer to those customers who want to design SiPs?
We offer technology. We have a full suite of tools not just for what I call traditional packaging design but also two solutions specifically for System-in-Package. We have a solution for those companies wanting to do large ASIC based SiPs where the focus is really about co-design. We also have a solution for analog/mixed-signal/RF SiPs, which is predominantly in the space for wireless multimedia headsets. There the focus is not so much on co-design but functional integration and simulation of those chips together with the discretes. You can actually build a true wireless front end in a package. So we offer two solutions there. Then for companies that are trying to do this for the
first time, we have a services offering through a group we call VCAD, which stands for Virtual CAD. They are a team of very experienced design engineers, who go into companies that are new to this area and help them build a reference flow and methodology and help them with a pilot project to take their first design through. We can offer the traditional EDA vendor approach of tools and technology or we can actually come, define a project, define some objectives and build a custom methodology plus train your engineers to put that flow in place. Basically hold your hand through your first project so that you can be successful.
Is more of Cadence business in this area on the ASIC side or the RF/mixed-signal side?
It is split pretty much 50/50. If you are on the wireless mixed-signal side, you really do not have an alternative with that market. People want so much technology in such small form factors, and at such a low price (think of the iPhone, Blackberry and other handheld PDA devices), that you have got to do a SiP. We have a huge user base there. On the digital side, I would say that there are companies that are fairly well established in doing SiPs but there are a lot of new companies coming on line, waking up to the advantages of combining silicon together on the digital side, predominantly memory; putting memory directly in there with any form of ASSP processor to improve the overall
performance and reduce power between processor and memory. A lot of the traditional suspect players out there, who produce these large graphics processor chips as well as chips that go with your XBOX and PlayStation, where you are talking about a lot of digital power crunching going on. They are pretty well aware of the value of a SiP over the discrete packaging of the past. Our business is pretty well split. In the mixed-signal space, the guys are pushing the envelope but they are not only putting chips together, they are also putting discrete passive structures like antenna structure, passive filter networks, and tuning circuits. They are actually putting them down in the package level
and using them to affect the performance of the chip. They are doing very sophisticated chips. The digital guys are more creative and artistic in the ways they are leveraging the extra packaging real estate they get by doing a SiP.
How big is Cadence’s IC packaging and SiP business?
I am not allowed to give out any numbers in terms of any other area of Cadence business or a dollar amount. But if we talk about in relationship to our packaging business, Cadence is one, if not the largest supplier of SiP technology in the market. You talk about our SiP business being 30% to 40% of that packaging business. What is happening out there is that the packaging business is going through a change. The packaging business is basically moving up the food chain. We are seeing our traditional packaging customers starting to adopt SiP, primarily because their customers are demanding it. It is a new market for them to leverage extra value compared to their previous market of just
taking a chip and literally placing it inside a package. Now they are able to add value by integrating multiple pieces of silicon in a package. That’s a more valuable proposition to the market. Therefore, they can get more revenue that way. So they are going up the food chain at the same time. That’s why we are starting to see out overall packaging business number one in growth and adoption but also SiP because our traditional market is migrating to doing more SiP than standard fixed packaging.
Who is Cadence’s competition in this arena?
Who is the principal competition for us? There are really two companies. One is global. That company is called Sigrity. Then there is one company that is very specific to the Japanese market. That is called Zuken. There are lots of very small niche players, firms that are 100 times smaller in terms of revenue.
Have there been any recent product introductions by Cadence in this area?
We just announced our latest release of IC Packaging and SiP tools. We just released SPB 16.2. We announced that two weeks ago.
What were the highlights of that release?
Two big areas! First of all, we introduced our first package power delivery network solution. We talked earlier that one of the big challenges of SiP is power delivery networks, to provide power efficiently to low power chips. We announced our first true power delivery design solution for SiP. There were two other areas in that release. One was true constraint driven support for high density interconnect design, HDI. HDI, also know as microvia, is a manufacturing methodology for integrating chips and devices together at extremely small pin pitches. I am talking about 65 millimeter of pitch between the pins and smaller. That is the way you get true miniaturization. That is why going to
65 nm and 45 nm is allowed. At that scale of extremely small pin pitches, you can mount your silicon in the smallest possible space. But, of course, that puts some very interesting manufacturing constraints on the packaging team. They have to adopt what is known as high density interconnect buildup methodology in order to accommodate these micro pin pitch devices. What we have done is to introduce rules and constraint driven design approach dealing with HDI so that designers can focus on design rather than focus on doing all these manufacturing DFM checks to make sure that the design is in fact compliant with the HDI requirements. What we have introduced is very substantial.
Last of all, we did a partnership with a company called Kulicke-Soffa, also known as K&S, an American company. They are the world’s number one provider of hardware for packaging assembly. They provide the equipment that assembles the chip into the package. As we get into these complex SiPs, the need to be able to understand real manufacturing DFM data and take that into account is really important. If you do not do it, you either under-design because you have to apply very large tolerances for the manufacturing processes or you can sometimes get designs that are not manufacturable or have very poor yield.
A designer’s 3D view of a wirebond design using Kulicke and Soffa-supplied wire loop profiles, which enable DFM-driven design.
What we did with K&S is to partner with them to develop a library of wirebond profiles. For most stacked chips, stacked multiple dies on a chip, you use wire bonding to connect chips down to the bottom of the package. You do that using a gold wire and a machine called the wire bonder. It kind of looks like a sewing machine and it stitches these chips down. As you stitch these chips down, you need to be able to accurately model the 3D shape and curvature of the wire to make sure that the wires do not touch, which could cause a short circuit or that the wires do not come too close to another object like another chip, because you cause the machinery to clip the actual chip that would cause a
breakage and therefore you would get a really bad drop in yield. One of the things we did, which was driven by our customers, specifically the assembly and test customers, was to provide their customer with a library of these profiles that were fully validated and approved by the machine maker, the hardware assembly machine maker. When designers do design and start combining chips together in complex chips, they should understand exactly what wire profile the machine can use. They can go in and validate the actual design to see if it is manufacturable during the design aspect phase. They do not want to wait until they have completed the design to learn “Oh, by the way, you can not
really assemble this guy. You can’t do want you are asking for”. They want to be able to give the designers that knowledge up front. So what we did was partner with K&S. They have provided us with a validated library of wire profiles included in our latest release of SiP tools. So the design engineer is now DFM aware right from the very get-go. We think that is going to help people improve the yield and quality of their SiPs and at the same time give them the ability to minimize the overall form factor. They are able to accurately design from the manufacturing point of view. Those were the major sound bits of our latest releases.
What is Cadence’s competitive advantage?
There is one big obvious difference which is Cadence is the only vendor that can provide an integrated chip design, packaging design and PCB design flow. We provide all three parts of that design flow. The second reason is because Cadence has IC design as part of our portfolio, we actually understand the whole need for co-design. In fact we were the first EDA company to introduce the idea of co-design between the IC team and the packaging team. We introduced that with our first SiP solution a couple of years ago. We were also the first to introduce a truly focused solution. We are the only one that supplies you chip design, packaging design and PCB design.
Also, the fact that we have such strong customer portfolio of IC companies, packaging foundries and system companies gives us an advantage of being ahead of where the market is going and where technology is going, so that we can provide solutions faster than anybody else.
Anything else to add?
People ask SoC versus SiP. It is not one or the other. They are complementary. They are time when you want to integrate functionality together a system-on-a-chip but there are also times when you want to add peripheral functionality that may change within a very short period of time like memory. That’s were SiP comes. Often you put a SoC into a SiP to complement the SoC with supporting silicon. It is not an either or proposition.
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-- Jack Horgan, EDACafe.com Contributing Editor.