[ Back ]   [ More News ]   [ Home ]
June 09, 2008
Elastix Clocks Reduce Margins. Landing in Barcelona.
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor


by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


Introduction


Elastix is an early-stage EDA company developing innovative technologies to enable variability-aware designs and optimize power-performance trade-offs for 65nm and beyond technologies. Their technology of elastic clocks enables designers to reduce performance and power margins. The technology comes out of the Barcelona area which has an innovative incubator program. I had an opportunity to talk about the technology, the company and the Landing program with CEO Vigyan Singhai and Engineing VP Emre Tuncer.


Would you provide us with a brief biography?

My name is Vigyan Singhai. I am CEO of Elastix. Along with Emre (Emre Tuncer VP of Engineering) and Jordi (Jordi Cortadella, Chief Scientist) I founded the company. I got my Ph.D. degree in logic synthesis and verification at UC Berkley under the guidance of Professor After that I joined Cadence for a few years. After Cadence I founded Jasper Design Automation where I was CEO for the first three years until the day of the second round financing. I stayed at Jasper for a few more years. I left to start a design verification and IC company called Oski Technology. In 2006 I was introduced to the idea of elastic clocks by Jordi Cortadella who is our CTO and Luciano Lavagno. These two guys are
the inventors of the technology. The idea was very intriguing to me. It promised a lot of performance and power gains. I did a lot of due diligence, tried to understand the potential of the technology as well as the market opportunity by talking to a few potential customers. Once I was convinced I left my business to jump into this full time at the end of 2006.


A brief biography from you also, Emre.

I started my professional career in EDA in southern California. After finishing my Ph.D. at the University of Texas at Austin I moved to Camarillo and joined Quad Design. At the time it was a subsidiary of View Logic. I was there for two years, mostly on signal integrity. We developed a prototype of our own chip signal integrity tools and for the customers too. About two years later I moved to the Bay Area to Monterey Design Systems. At the end of 2002 I left Monterey and went to Magma. My first responsibility at Magma was for engineering. In the subsequent years I held VP of Engineering and Chief Technologist positions. About a year ago I joined Elastix. I have been working on the product
ever since.


Emre: What caused you to leave Magma which has been doing very well to join a new startup?

I got the startup fever when I joined Monterey. I was one of the initial people there. Then I joined Magma. I saw Magma growing up from when I joined it was around 100 to 200 people to over 800 people when I left. What I wanted to do was take a new idea, a new technology, from scratch and bring it to the user domain and make it a product. I met with Vigyan. After numerous discussions I realized that this was the right technology. It is the right technology in the sense that it is not disruptive but the benefits it provides are much higher than the things you need to adopt the technology.


How did you (Vigyan) learn about the technology?

I was introduced to this by Luciano Lavagno who I have worked with for many, many years. He got his Ph.D. at UC Berkley, was at Cadence and is also Professor at Polytechnico de Torino… right now. He was one of the inventors of this technology. He introduced this idea to me a couple of years ago. Since then I have been working on this. These guys have been working on this technology for about 10 years now.


Where were they working?

At universities. Luciano Professor at Politecnico de Torino in Italy and Jordi Professor at Barcelona. They also had a couple of other researchers. One guy was from Cadence and worked at Philips.


Did you bankroll the company or did you get outside funding?

Initially we funded the company on sweat labor. Then we got a big investment from an angle investor last year. Today we are raising additional funds.



If I understand correctly Elastix has one foot in Silicon Valley and one foot in Barcelona.

The city of Barcelona had adopted a lot of initiatives to bring in new companies. There is a section inside Barcelona, called the 22nd district, which is a vision of creating a compact city where one can live, work and play. It is kind of like a sub-city inside Barcelona. They have the Landing Program which provides an infrastructure to get a firm up to speed in all the issues such as legal, accounting, employment, and getting office space. We had no experience before in starting and building a business in Barcelona. The partnership with that program has been extremely kind and fruitful for us because without their help for us to go there and start this business would have been
very difficult. It is an ideal environment to have from the perspective of a foreign company which is landing in Barcelona. The district itself envisions itself becoming a business landing zone for international companies. It pretty much represents what Elastix is. We are in Barcelona because Jordi has been there for many years. He has a lot of contacts, academic contacts; his ex-students, resource into a pool of people we can tap into. But we did not have the business contacts. For that the Landing Program has been extremely helpful.


Are there any other EDA or semiconductor companies in Barcelona?

That is the interesting thing about Barcelona. The economy is strong there in a lot of industries like telecommunications, oil and gas, finance, electronics and high tech. There has not been a concentration of large companies but new companies are coming up. There are semiconductor companies like DS2 which is a well funded company. Barcelona Design Systems was named because the founder was from the city of Barcelona but it had no operations there. We can take advantage of the talent right in the city itself.

Editor: Dr. Mar Hershenson was a founder of Barcelona Design. More recently she was CEO of Sabio Labs which was recently acquired by Magma.


What was the problem that the technology was trying to solve?

The way I look at it, we had a vision of building a large complex chip without sacrificing significant performance and power margins. What has been happening for many, many years is that we were throwing away large margins because the only way we knew to do design was to do worse case design, sacrificing significant variations in margins from the typical design points. Today in the face of increasing low power requirements we are forced to deal with variability. With our technology we embrace variability and let the design run at their natural power and performance which is significantly lower than how chips are designed and manufactured today. That’s the opportunity. People
are doing all sorts of things to manage power, control power, minimize power requirements both in the design of blocks as well as in the design of interconnect. There is a rise in adoption of aggressive voltage scaling techniques. That is prompting people to think about variation, off chip variation, timing analysis and physical design. It was the right time for the technology to come about. It was a natural and easy answer to a lot of those issues.


What is the source of this variability?

Variability in design is there. Some people say it is increasing, others say it is the same. The sources are different. There are the obvious manufacturing sources. Different devices on the same chip may have variations for manufacturing reasons. On the same wafer they may have different performance. Of course different wafers form the same fab or from different fabs, even with exactly the same design and process and so on. Similarly there are environmental variations because of changes in supply voltage, temperature. In addition to all that there are also data variations. Under different logical input conditions the same design or the same block may run in different amounts of
time. We can take advantage of all those variations. You do not have to worse-case all the variations all of the time and sacrifice or throw away significant timing or power.


What is the approach that Elastix is using?

Our technology is based upon the concept of elastic clocks. We implement the global clocking network in the design so that the clocks become elastic and flexible in that it tracks the performance of the design. If the data path happens to be fast because the temperature is low, if it happens to be slow because it is on the slow part of the chip or because the voltage is low for some period, then the clock automatically tracks the data path. The clock is slow or fast depending upon the data path. By virtue of the clock tracking the data path, I do not have to make the clock slower than the worst the data can ever be.


So it is dynamically doing this?

It is happening live, dynamically. The advantage of all of this is that you can take any average block in the design, change the voltage of that block or any portion of that block. The design is still guaranteed to work but the performance is going to resonate with how you play with the voltage for example. All this is happening dynamically.


When you are verifying the chip, how do you know that this is in fact what is going to happen?

Good question. There are various verification aspects. One is verifying the design itself, that the design works and is correct. The nice thing about our approach is that it fits into existing design flows. We use the same standard RTL to GDSII flows, the same place and route, the same timing and functional verification. It is exactly the same RTL verification. That has not been touched. There is a problem of functional verification. We have altered the design. We have introduced some new circuit elements into the design. You have to verify that. The original circuit is a thing of the past. You use functional verification and certain tools from companies like Cadence and Synopsys.
The results from timing verification is to verify that indeed at the corners the design still works and provides the performance you want. That is verified through sign-off, multicorner sign-off using standard timing verification tools, signoffs tools from Synopsys for example. The signoff is done at all the corners of the process, voltage and temperature.


Does the design get to some point of verification and then does your technology enter the picture? Is it a sequential process? The designer does some design or some design block, verifies that design, arrives at some comfort level and then brings in your technology (elastic clocks) and re-verifies.

Yeah, kind of. You have some design in your mind, some conceptual level, some system level. At some point you write the RTL for that design. You go through standard verification using whatever simulator you have. We do not come in until later. Then you synthesize the design using Cadence, Synopsys or Magma tools. Once the design is synthesized and is at the gate level, you are inserting the clock tree. That is where we come in. You apply the Elastix transformation. After applying that you get back into the standard design flow, physical synthesis and routing. You can do the verification immediately after applying the Elastic transformation as well as at all the subsequent stages.


We start from a pre-verified design and then we make any changes through our tools. We re-verify the impact of those changes though timing and functional verification.


Do you have any customers or beta sites for this technology?

Yes there are customers. We are working with some strategic customers who are checking out their designs. I am not in a position to disclose their names but we are working with several customers.


Have you set a potential price point for the product?

No. Actually we have not released the details of our product except to some customers. This will come in a few months.


Is there a particular set of end user applications for which this technology would have maximum benefit?

First it works for all designs but the sweet spot for this technology are designs which are system-on-chip where potentially you will be putting together blocks from different sources, from inside the company or from third parties. A lot of the time the devices are working for multiple applications. The chip that is in your cell phone is sometimes used for videos, sometimes for email and some times for simply talking on the phone. So you have different workload requirements. There are different voltage requirements under different workloads. Different blocks scale and perform differently. You need to be able to support different power and voltage requirements when blocks behave differently.
So that is the perfect sweet spot for elastic clocks.


Another sweet spot is multicore applications where people are building multiple ports putting them together on the same chip whether it is a graphics chip, a simple process or router chip. They are putting many different ports onto the same chip and connecting them together. Any applications where you are putting multiple blocks together designed under different conditions and requirements and having to talk with each other and be interconnected and you have some flexibility in the connect in terms of the work requirements and variation. So low power applications.


How large a company is Elastix today?

We are about 10 people.


Do you envision selling directly or through distributors?

It depends upon the market. Initially we will be selling directly but as we go to Asia we will work with distributors.


Do you have a time frame for releasing the product?

In a few months.


Possibly at DAC?

No. We will not release before DAC. We are working with customers who have our product and are using it on their designs. We do not have an availability date at this time.


To your knowledge is there any other firm out there doing something similar?

There has been a lot of research in voltage scaling as well as making clocks flexible or less rigid. In terms of voltage scaling techniques there are a lot of in-house solutions in different places. They have to do with adaptive voltage scaling as well as dynamic voltage or frequency scaling where they are changing the voltage as the frequency of the block changes. But all of them are in the context of rigid clocks. Then in terms of changing clocks, there have been a lot of work in different segments. In the context of synchronicity and rigid clocks there have been efforts in implementing useful skew. There have been efforts in taking into account of on chip variation also called OCV. Then
what we are doing is making the clock even more flexible than all of that. There are other companies that have taken radically different approaches like Handshake Solutions. Our approach is significantly different than that.


Why is your approach more effective than the more popular or traditional voltage scaling approach?

It is not that we are competing with any of the voltage scaling approaches. The issue is that we are able to exploit the voltage scaling. We can make voltage scaling as flexible as you want. You can make it at as fine a granularity as you want to make it. With voltage scaling today you are limited to scaling the voltage and scaling the frequency and doing some tight synchronization between the two steps but in doing that you are losing a lot of margin and you have to go back to voltage specific areas. In our technology you can scale voltage independently on any portion of the design or any sub-block you choose to. It is the most flexible way of voltage scaling.


Is it conceivable that a design could be so poor that you could not make it work, close timing even with elastic clocks?

I can not think of something like that. Are you saying that the design can not be made to work even in a synchronized rigid clock world?


Let me rephrase the question. Is it a prerequisite to using your technology that a design works first in a rigid clock world?

Yeah. It depends on what you mean. You can have designs with rigid clocks that do not meet your timing or power requirements and by using our technology you can get the design to meet those requirements. So a design that was not working in some sense is now working. If you had a design that was working, it will always work because with elastic clocks you can get additional benefits. You have to use the tool and get the results from the tool and the clocks become elastic. But if the design was working, it will always work at least at the same speed and power as before but typically much faster and at lower power than before.


Anything else to add?

Why are we doing this? Power has become the number one design issue today. People are doing designs with more modes of operations, voltage scaling and so on. We have an opportunity to make these designs as flexible and as of as low power as possible. That’s the opportunity we have. We are excited about ding this.


The most significant thing is to make all of this work in the different existing design flows, with the existing sign-off tools, timing analysis and functional verification. That is something different in what we are doing as opposed to previous solutions in the same space. We are excited about working with our strategic customers and making this happen.


By the virtue of clocks being elastic, the designs run faster, and for power-sensitive applications, the same performance can be achieved by running the design at lower voltages, thereby saving both dynamic and static power. A qualitative illustration is shown below.


Editor: Barcelona’s Landing is a high value strategic program that grants knowledge-intensive and technological business initiatives the access to a network of platforms in different Innovation Systems making their internationalization easier and quicker.


Landing offers a privileged platform: an international incubator at Barcelona’s Innovation pole, one of the biggest European metropolises which is also the economic, cultural and administrative capital of Catalonia, the region located at the northeast of Spain, in the Mediterranean sea.


22@Barcelona is a project that is transforming two hundred hectares of industrial land of Poblenou into an innovative district offering modern spaces for the strategic concentration of intensive knowledge-based activities. The project is being designed to become a ‘compact city’. Having the Triple Helix as a model, it creates an environment and culture propitious to development and innovation relating The Government, University and Industry, where, each of the actors will both bring value to the Program and at the same time be the direct, priority recipient of the value proposition offered by the Landing Program. Finally, 22@Barcelona is fostering the development of technology
clusters within the district, specifically ICT, MEDIA, MEDTECH and ENERGY. The infrastructure is being deployed, organizations and agents with research capabilities are settling in the district, and if territorial innovative capacity is displayed, as a virtuous circle, entrepreneurship and talent will be called and attracted.




Univeristat Politecnia de Catalunya (UPC)



Another Andy Rooney minute:

My name is Jack. Actually my legal name is John. When I was a kid, I did not like the name Jack because all the nursery rhymes had Jacks; Jack in the Bean Stalk, Jack and Jill, Little Jack Horner, Jack Sprat, Jack be nimble... My father also John liked the name Jack as more informal and more masculine. My son, John III, is called Jay.


In the US it is common for people to be called by nicknames by their friends and relatives. For example


Joe for Joseph

Bill for William

Bob for Robert

Jim for James

Stan for Stanley

Ted for Theodore

Kev for Kevin

Don for Donald

Ron for Ronald

Dick for Richard

Ed for Edward

and so and so forth.


Women also often get nicknames like Meg for Margaret, Cindy for Cynthia, Amy for Amanda, Abby for Abigail and Pat for Patricia.


Sometimes a diminutive form of the name or nickname is used such as Joey, Bobby, Billy, Jimmy, Donny, Ronny, Eddie or Dickie. Most people recognize Bill, Bob, Joe, Dick and so forth as common nicknames. However, this is not the case for Jack since not all or even most Johns are Jack and not all Jacks are Johns. Further unlike most nicknames Jack is not shorter than John. This situation has caused me considerable confusion and generated lots of questions. I have to make sure my paycheck, travel documents and so forth have my legal name rather than my nickname. I have often received checks and plane tickets from well meaning people who know me as Jack with the name Jack rather than John.


Even US presidents have nicknames; Abe Lincoln, Harry Truman, Jimmy Carter, Dick Nixon, Ron Reagan, and Bill Clinton. Fortunately one US president had the same problem I have, namely, John Fitzgerald Kennedy aka Jack Kennedy. I always refer to him when trying to explain the Jack versus John situation. I did this at the Frankfurt airport when my ticket said Jack and my passport said John by saying "You know the US President John Kennedy, Jack Kennedy ‘Ich bin ein Berliner’. The person behind the counter was too young to remember the speech or the man. Fortunately, this was before 911. It would not work today.


If you sending me money, remember to use John not Jack.


See you at DAC in Anaheim.


The top articles over the last two weeks as determined by the number of readers were:


Incentia's TimeCraft Adds Multi-thread and SSTA Incentia Design Systems, Incannounced the availability of new features in its next generation timing analysis tool. Incentia's TimeCraft™, the world's fastest and sign-off proven static timing analyzer (STA), is now enhanced with multi-thread capability to greatly cut down analysis runtime for big designs. It also adds statistical STA (SSTA) to effectively address the process variations for designs using technologies at 45 nm and below.


ReyesSoft Adds SystemC 2.2 and other major Open Source EDA Software Applications to its OpenEDA 1.1 Toolkit ReyesSoft now includes the emerging IEEE 1666 open source EDA standard, SystemC 2.2 in its OpenEDA 1.1 Toolkit. Along with SystemC 2.2, the OpenEDA 1.1 Toolkit now includes design and verification libraries such as Trusster ‘s Teal and Truss, Kicad, Magic, Toped, Irsim, Xcircuit, and other major open source EDA software applications.


Altium Solves 25 Years of Electronics Design Pain: Designers in Both Worlds Can Now Link and Review Designs Dynamically Altium has introduced technology that, for the first time, lets electronics designers fit their boards into enclosures in real time, in 3D, without guesswork. They can eliminate the numerous costly, trial-and-error, "wait-and-see" ECAD-MCAD iterations that, until now, have delayed bringing a product to market. It is now possible to link to external STEP models from within Altium Designer to bring, for example, the model of the casing into the PCB design
environment. By using the non-proprietary STEP 3D file format as a mechanism, Altium allows ECAD-MCAD collaboration without forcing organizations to purchase costly integration add-ons or use a specific mechanical CAD package.


Synopsys Releases Proven VMM Methodology Standard Library and Applications Under Apache Open Source License Synopsys has released the source code for its complete implementation of the proven VMM verification methodology for SystemVerilog, including the VMM Standard Library and VMM Applications, under the popular Apache 2.0 open source license. Synopsys' implementation of the VMM methodology, originally defined in the Verification Methodology Manual for SystemVerilog, was recently donated to the Accellera standards organization to speed development of verification interoperability
standards.



Other EDA News


•        
Extreme DA Announces GoldTime MXO for True Optimization of Complex Digital SOC Designs

•        
Altium Provides Way Forward for Cadence(C) Allegro(C) Users

•        
EVE to Demonstrate to DAC Attendees How to "Break the Billion-Cycle Barrier"

•        
TSMC's Reference Flow 9.0 Includes Azuro Clock Tree Synthesis

•        
Pyxis Technology: Targeting 45nm Design Closure at the 2008 Design Automation Conference

•        
Silicon Image Announces SteelVine Storage Processor Support for Intel's Latest PC Chipsets

•        
ASUSTeK Introduces P5Q Series Motherboards Featuring Silicon Image's SteelVine Storage Processor and ASUSTeK Drive Xpert Utility Management Software

•        
LYNGUENT(R), INC. to Exhibit at the 45th Design Automation Conference (DAC 2008), June 8-13, 2008, at Booth 2562

•        
Tensilica and SPIRIT DSP Form Strategic Partnership and Deliver Mobile Multimedia Audio and Voice for Xtensa HiFi 2 Audio Engine

•        
Onespin Announces Industry's First SVA Solution for Gap-Free Verification

•        
ClioSoft to Demonstrate Enterprise Edition of Design Data Management System at DAC 2008

•        
Calypto Partners with HD Lab to Enable System Level Design Flows in Japan
CLK Design Automation Expands Amber Family with Industry's Highest Accuracy Transistor-Level SSTA Solution

•        
SoC Solutions Builds FPGA System in Record Time Using Synopsys' ReadyIP Flow and CAST IP Cores

•        
Synopsys Delivers Comprehensive Design Support for TSMC 40-Nanometer Process

•        
Cadence CDNLive! European User Conference Tackled Today's Design Automation Challenges

•        
Magma Talus and Quartz Software Qualified for 40-Nanometer Process Technology in TSMC Reference Flow 9.0 (Magma)

•        
Freescale Delivers Virtual Platforms to Continental Using CoWare ESL 2.0 Solutions
SynTest Hybrid Solution Enhances Design Quality and Pattern Compactness

•        
CoWare and Doulos Expand Collaboration

•        
TSMC Reference Flow 9.0 Covers Extreme GoldTime Sign-off Timing Analysis

•        
EDA Careers hires Kris Donate as Director of EDA Placement Services

•        
Interra Systems to Exhibit Products during Design Automation Conference

•        
DAFCA and Denali Software Announce Collaboration to Expand FlashPoint Platform Integration Features [03 Jun 2008]

•        
SpringSoft Global Debuts At 45th DAC [03 Jun 2008]

•        
Aldec Releases Riviera-PRO(TM)2008.06 HDL Simulator

•        
Altos' Cell Characterization Tools Used for TSMC's 40nm Libraries

•        
Design Automation Conference Announces Winners of 2008 DAC/ISSCC Student Design Contest

•        
Global Industry Survey Results Reflect Strong Interest in SOI for low Power at Mainstream Technology Nodes

•        
The MathWorks Real-Time Workshop Embedded Coder Validated by TUV Rheinland

•        
NetEffect Uses Breker's Trek to Verify Advanced Network Processor

•        
NetEffect Uses Breker's Trek to Verify Advanced Network Processor

•        
Virage Logic Supports TSMC's Power Trim Service(TM) for Advanced Process Nodes

•        
Liga Systems Announces Availability of NitroSIM(TM) v1.0 Delivering 10X Acceleration of Digital Logic Simulation Plus 4-State Accuracy

•        
Micro Magic Announces MAX-View -- Free OpenAccess Viewer

•        
New TSMC Reference Flow 9.0 Supports 40nm Process Technology

•        
Timesys Announces Strategic Alliance With Tensilica

•        
Tela Innovations Showcases Innovative On-Grid, Straight-Line Approach to Chip Design at Industry Events

•        
Javelin Design Automation Unveils j360(TM) With TrueFit(TM), TruePlan(TM) and TruePro(TM) - The First Specification-Driven Floorplanning and Prototyping Platform for Early Design Feasibility and Superior QoR

•        
Free 45nm Open Source Digital Cell Library from Nangate Released in its Second Edition

•        
eSilicon Presents Value Chain Producer (VCP) Model at DAC

•        
AMCC and Silicon Image Announce Their Strategic Alliance on Network Attached Storage Solutions Based on AMCC Power Architecture Processors

•        
Apache Design Solutions Offers Hands-On Tutorial on IP Validation for Macro and Embedded SoC at 45th Design Automation Conference

•        
Bluespec Demonstrates FPGA-based Models and Testbenches at DAC

•        
Teklatech’s FloorDirector™ floorplanning EDA tool exclusively selected by Think Silicon

•        
MEDIA ADVISORY: Meet With Leading IP Suppliers at IP Talks! at DAC

•        
Holly Stump Joins Envis as VP Marketing

•        
Daybreak OC's Pete Weitzner to Tackle Elections and Politics at Design Automation Conference June 10 in Anaheim

•        
Avery Design Realizes Insight For Formal Bug Hunting and Coverage Closure

•        
ESL Design Symposium With SystemC Co-Located With DAC 2008

•        
ARM, Renesas Technology and Synopsys Define Industry's First Low-Power Verification Methodology

•        
MediaTek Achieves Faster Time-to-Tapeout Utilizing Smart Hierarchical Modeling in Synopsys IC Compiler

•        
Satin IP Technologies to deliver first public demonstrations of VIP Lane in the US

•        
The International Conference on Computer Aided Design (ICCAD)

•        
Alert: Synopsys at Freescale Technology Forum

•        
Mentor Graphics Chairman and CEO to Moderate 6th Annual ESL Symposium Panel at DAC 2008

•        
Takumi Technology Joins Si2's Design-For-Manufacturability Coalition

•        
Extreme DA GoldTime Delivers First-Pass Silicon Success for Coherent Logix

•        
Certess Offers Hands-on Tutorial at the Design Automation Conference: Elevating Confidence in Design IP through Mutation-based Analysis Technology

•        
EVE Appoints Koji Iwagami General Manager of EVE K.K.

•        
Virage Logic Delivers Open RTL to Test Floor Embedded Memory Test and Repair Subsystem

•        
President of the MathWorks to Deliver Keynote At DAC 2008

•        
Ciranova Releases Industry's First Automated Analog Layout Solution Delivering Production-Quality Results

•        
Virage Logic Speeds Time-to-Market with an All-Digital, High-Performance DDR2/3 PHY+DLL Solution

•        
Ansoft Corporation Revenue Increases Nearly 20%

•        
Solido Design to Give Seminar and Tutorial on Variation Robustness for Analog/Mixed-Signal Design at DAC 2008

•        
Calypto Delivers Optimized Power Flow with Cadence Design Systems

•        
Arithmatica's Datapath Synthesis Used by Solarflare Communications for New 10GBASE-T PHY Design

•        
Embedded Alley Adds Embedded Linux Support for Tensilica's Processor Cores

•        
Verific Design Automation Gives Nod to Synopsys' VMM Open Source Release

•        
Pyxis Technology: Targeting 45nm Design Closure at the 2008 Design Automation Conference

•        
Tensilica Announces New Open Source Linux Emphasis, Broadens Processor Core Ecosystem With New Linux Partners TimeSys and Embedded Alley

•        
Zensys Selects Berkeley Design Automation Analog FastSPICE(TM) for Wireless Transceiver Verification

•        
Oticon Tapes Out Innovative Hearing-Aid DSP Using Synopsys IC Compiler

•        
Logic and Texas Instruments offer Zoom™ Medical OMAP35x Development Kit and System on Modules (SOM) for medical innovations

•        
SAME 2008 Forum

•        
Si2 Announces Member Demonstrations at the Design Automation Conference

•        
First Book Published on the Open Verification Methodology

•        
Mentor Graphics Qualifies Calibre Model-based Planarity Flow for TSMC's 65 and 40 nanometer IC Manufacturing Processes

•        
eASIC Turns 100


Other IP & SoC News


•        
Xilinx Completes Functional Reorganization

•        
QP Semiconductor Announces Qualified Replacements for ATV2500 Family

•        
Globetech Solutions' Verification IP for Latest IEEE Test and Debug Standard Selected by STMicroelectronics

•        
Apache Design Solutions to Host Methodology Presentations by Designers from Leading Semiconductor Companies

•        
BroadLight Secures Patent for High-Speed Internal Bus Architecture in GPON Semiconductors

•        
Dataram Reports Fiscal 2008 Fourth Quarter and Fiscal Year Financial Results

•        
Ultra-Low-Power MCU technology highlighted at TI's sixth annual MSP430 Advanced Technical Conference

•        
TI introduces flexible, dual-speed SerDes device for EPON optical line terminals

•        
Sarnoff Expands License in ESD Solution for Toshiba

•        
Renesas Technology Releases Low-Priced E100 Emulator for Engineers Developing Embedded Systems With 8- to 32-Bit CISC Microcontrollers

•        
CEVA and ARM Partner to Enhance Development Support of CEVA DSP + ARM Multiprocessor SoCs

•        
AMD Announces its Highest-performance Mobile Graphics Chip Ever for HD Visual Computing on the Go

•        
Altera Updates Second Quarter Guidance

•        
Vitesse G-RocX(TM) SoC Enables CyberTAN to Deliver Industry's First Production-Level Home-Gateways for the Fiber-to-the-Home (FTTH) Market

•        
Catalyst Semiconductor Launches Lower Power 8-Bit I2C/SMBus I/O Expander

•        
Forte's Cynthesizer SystemC Behavioral Synthesis Selected for Fujitsu Microelectronics' ASIC Reference Flow

•        
Hynix Adopts Apache's Dynamic Power Integrity Solution for DRAM Designs

•        
TerraTec Electronic Selects XC5000 Smart Silicon Tuner to Power New TV Sticks

•        
SMSC Announces Retirement Plans of Chief Executive Officer

•        
TOA Technologies Raises $13 million From Intel Capital and Additional Investors

•        
STMicroelectronics' New Voltage Supervisors Ensure System Integrity in Multi-Voltage Systems

•        
Dongbu HiTek Launches Industry's First 0.18-micron BCDMOS Process

•        
Toshiba Announces Space-Saving 6-Pin Photocoupler Optimally Suited for Direct Gate Driving of IGBTs and Power MOSFETs

•        
New Cypress Online Training Website Gives Designers Easy Access to Resources for PSoC(R) and Other Programmable Solutions

•        
Spansion MirrorBit(R) NOR Flash Memory Solutions Expand Options for Xilinx(R) Spartan(R)-3A Customers

•        
NVIDIA Optimizes Notebook PCs With New Lineup of GPUs

•        
Tundra Semiconductor Terminates Product Acquisition and License Agreements with IBM 

•        
MEDIA ADVISORY: Meet With Leading IP Suppliers at IP Talks! at DAC
Skyworks Introduces Industry's First BAW Filters to Enable WiMAX and WLAN Co-Existence

•        
Conexant Expands Video Surveillance Semiconductor Portfolio

•        
Microchip Technology Enhances Popular 16- and 32-bit Development Platform with Application-Specific Expansion Hardware

•        
NetLogic Microsystems Announces the Industry's First Quad-Port 10 Gigabit Ethernet PHY for 10GBASE-LRM SFP+ and 10GBASE-KR Backplane Applications

•        
AMD Launches New Quad-Core AMD Opteron(TM) Processors for One-Socket Servers and Workstations

•        
Broadcom's Media PC Technology Enhances the Multimedia Performance of UMPCs and MIDs

•        
Broadcom Delivers Industry's First Single-Chip 802.11n USB Solution to Bring Low Cost, Dual-Band Performance to Wi-Fi(R) USB Adapters

•        
Broadcom Announces Groundbreaking 65 Nanometer Single-Chip Bluetooth(R) 2.1 + EDR Solution for Mobile Handsets

•       
Marvell Shiva Embedded CPU Technology Set to Drive Next Generation of Consumer, Mobile and Enterprise Applications 

•        
Marvell Introduces SoCs to Boost Digital Home Gateway and PC Performance

•        
GCT Semiconductor Announces Industry's First Mobile WiMAX IEEE 802.16e Wave 2 Compliant 3.5 GHz Monolithic Single-Chip Solution

•        
Ralink Introduces RT3052 and RT3050, the World's First 802.11n Single Chip Access Point/Router SoC with Integrated Ethernet Switch and PHY

•        
ROHM's High-Efficiency Isolated Driver Modules Optimized for High-Intensity LEDs

•        
Avnet Launches EXP High-Speed, High-Performance SerDes Module From National Semiconductor

•        
Xceive Launches XC800 COFDM Digital Demodulator with Exclusive Digital Tuner Interface

•        
Gartner Says Worldwide Semiconductor Market on Pace to Grow 4.6 Percent in 2008

•        
Tundra PCI Express Bridge and Alogics PCI One Chip Decoder Selected by I-View Communication for High Performance Video Surveillance Capture Card

•        
Leadis Technology Announces a New Family of Inductorless 200 mA, Dual Output LED Flash/Lamp Drivers

•        
Cypress's OvationONS(TM) II Laser Navigation System-on-Chip Selected by Sunrex for Trackball Applications

•        
Cypress Introduces World's First Programmable Single-Chip Laser Navigation System, Simplifying Mouse Design and Manufacturing

•        
SiliconBlue Pioneers New FPGA Technology for Handheld, Ultra-Low Power Applications

•        
ARM Multiprocessing Technology Powers Groundbreaking NVIDIA Tegra Mobile Computer-on-a-Chip

•        
STMicroelectronics Introduces Highly-Integrated Step-Up DC/DC Converter to Address Blue-Laser Applications

•        
Media Alert: See Sidense at DAC to Prevent Memory Loss

•        
ASM International N.V. to Host Interconnect Technology Seminar

•        
ChipX Introduces Synthesizable 32-Bit CPU With Best-in-Class Code Density for Embedded and Consumer Applications

•        
Freescale Symphony(TM) DSP audio family first to implement Multi-Channel Dolby(R) Volume for consistent volume levels from multiple audio sources

•        
AMCC Introduces 802.11n Enterprise WLAN Access Point Reference Design Based on Its PowerPC 405EX Processor 

•        
XAVi Designs BroadLight's BL2348 System-on-Chip Into High-Performance GPON CPE Devices

•        
AMCC Unveils Advanced PowerPC 460SX Storage Processor for High Throughput RAID Acceleration

•        
April Semiconductor Sales Up 6 Percent Year-on-Year

•        
IDT Introduces New Search Accelerators, Providing Increased Search Performance, Lower Power and Higher Density

•        
Freescale Launches World's First 50-Volt LDMOS Power Transistors for L-Band Radar Applications

•        
Obopay Implements SafeNet Hardware Security Module to Enhance Mobile Payments Security

•        
Vitesse Stackable Ethernet Switch and PHY ICs Selected by Napera Networks 

•        
ARM Mali-400 MP Technology Brings High-End Graphics Performance to All Consumer Devices

•        
Ozmo Devices Unveils the First Wi-Fi PAN Technology for Low-Power Applications 

•        
Avago Technologies Announces Second Quarter Fiscal Year 2008 Financial Results



You can find the full EDACafe event calendar here.


To read more news, click here.



-- Jack Horgan, EDACafe.com Contributing Editor.


Rating: