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May 19, 2008
Buzz@DAC & Kuhl@CAL
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

This column’s a two’fer …

A visit to the Cadence Berkeley Labs overlooking the legendary Cal campus, plus a visit to DAC overlooking a different kind of legendary campus – Disneyland USA.


EDA in Anaheim …

Admit it. The EDA industry is just a bunch of human beings running around trying to optimize a whole lot of stuff – a host of algorithms, a boatload of code, a microdot of real estate, a handful of business models, a passelful of marketing messages, a fistful of dollars, a little bit of power, and a whole lot of glory.

When this wacky group of Optimistic Optimizers gathers together in the Happiest Place on Earth between June 8th and the 13th, they’ll be optimizing one more thing – the Design Automation Conference.

The thing about DAC is that there’s pretty much room for everybody – the researcher and the raconteur, the manager and the marketeer, the CTO and the CEO, the AE and the EE, the MBA and the CPA, the JD and the PhD, the BA and the BS (lots of that last one), the programmer and the product guy, the student and the scholar, the talent and the tap dancer, the VC and the visionary, the PR and the R&D, the fathead and the faint of heart, the truth teller of all that is (on and off the record) and those who foresee the truth of all that might be.

Yep, they’ll all be in Anaheim in June and they hope you will be, too. If you click on print article up there on the right, you can scan through this column and a feisty sampling of why they hope you’ll be there. But if you want to savor DAC’s full offering, you’ll have to join us all in June to experience the real thing. The Magic Kingdom awaits …

We’ll see you there!



It’s a shame that Cadence ain’t coming to DAC this year, because one of the Kuhlest Guys on Earth won’t be in the Happiest Place on Earth in the second week of June.

Instead, he’ll be in the Hippest Place on Earth, enjoying his way-cool office, his to-die-for views, and one of the slickest gaming rooms in all of High-Tech-dom.

If you’ve guessed I’m talking about Andreas Kuhlmann and the Cadence Berkeley Labs, you’d be spot-on right. But if you think the Buzz is gone from DAC because Cadence ain’t coming, you’d be spot-on wrong. Andreas is definitely one Kuhl Kat, but DAC is one Cool Conference, and I think it’s a shame that Kuhl and Cool won’t be sharing Tomorrow Land, the Teacups, or Mr. Toad’s Wild Ride with all the rest of us in Anaheim from June 8th to the 13th.

But I digress …

Andreas Kuhlmann started out life in Germany, earned a PhD in electrical engineering at the University of Technology at Ilmenau, did a stint at the Fraunhofer Institute of Microelectronic Circuits and Systems, spent 10 years at IBM’s T.J. Watson Research Center in New York working in logic synthesis and verification, and then came to Berkeley one day for a visit and never left.

He joined the Cadence Research Labs in 2000, became an adjunct professor at Cal in 2002 to doubly defend his decision to stay in Berkeley, and by 2003 was Director of the Cadence Labs.

Things have only gotten better since then, however, because in September 2007 Kuhlmann and the entire gaggle of 25± over-achievers associated with the lab have been housed in one of the snappiest offices in town.

Perched up on the 10th floor of some distinctly A+ real estate at the corner of Shattuck and Center, these folks have a view to the East that takes in the Campanile and most of the trees of the picturesque U.C. Berkeley campus, and a view to the West that’s even better. If you stand at the windows adjacent to Kuhlmann’s desk, or in the conference room next door, you look right over the rooftops of the city and out to the Blue of the San Francisco Bay and the Gold of the Golden Gate Bridge beyond. Does it get any better than this?

Yeah probably, because Kuhlmann et al don’t have to dwell on the view to get their kicks. They’re such gluttons for intellectual punishment, they’re just as happy hunkered down over their computers, cranking out obtuse algorithms, and coding stuff that only a rocket scientist would understand. Clearly, their idea of fun is learning that Moore’s Law has pushed them into even darker, smaller geometries and presented them with even more hellishly difficult design, optimization, and verification challenges.

These guys are the ultimate uber-nerds, but Kuhlmann speaks highly of the life they lead nonetheless. The motivation for everybody at the lab, per Kuhlmann, is the opportunity to meet one’s own personal challenges in the research, as well as to see how the research plays out in a commercial setting.

“Whether in academics competing for a Best Paper Award, or in a commercial setting, you always want to be first,” he says. “When you combine that attitude with a culture of success, and insert it into the laboratory, it’s inevitable that your work will make an impact on a company.

“In my role as someone who runs a research lab, I’m like a catalyst exposing people to problems in need of a solution, and helping in the conversation – especially for the younger researchers – about how you structure the relationship between research and the product group who benefits from that research.”

Kuhlmann says the Cadence Berkeley Labs were chartered from the get-go to examine a host of technologies – systems, verification, implementation, modeling and simulation, and DFM – and to keep the boundaries between those technologies fluid.

“At a company like Cadence, we’re probably the only ones who can do that,” he says. “Here at the lab, we come from a range of backgrounds and have [among us] some of the best minds in the world across all of areas of interest. Our formal verification guys talks to our circuit simulation guys, and so on, which results in a lot of interdisciplinary progress being made. A good research team must always be interdisciplinary – you need people with strengths in many areas. That’s where the synergy to produce great research comes from.

“That’s also why our role within Cadence is bigger than just supporting any one particular product group,” he adds. “We provide support across all product groups, helping to define strategies, and where things should be heading in the short and the long run.”

Kuhlmann points out that he enjoyed a similar kind of experience when he worked at the T.J. Watson Research Center: “I learned a lot while I was at IBM. What I liked best about working there was, it was always a combination of research and applications. No matter what we were doing, it was always driven all the way to the designers and focused on delivering solutions to their desktops.”

Kuhlmann says that’s how things work at Cadence, as well: “Here at the lab, we act as a service organization to both the Cadence developers and their customers. Cadence product people, of course, hear from their customers, but we have the latitude to deal directly with the customers, as well. We don’t always know how our work will be commercialized – we’re more research oriented than product oriented – but we’re structured so we can enjoy the short, mid, and long-term view of things simultaneously.”

Located just a few steps from the U.C. Berkeley School of Engineering undoubtedly reinforces that outlook. Kuhlmann agrees, but adds a caveat: “Sometimes we do have visiting academics from Cal or other universities, but they are only visitors because if they stay longer we need to make our arrangements with them very clear – who owns the research work, and so on. We have a lot of trust between all of us, but for legal reasons we always need to maintain a clear framework under all circumstances about the intellectual property.”

“Of course, we also fund a lot of external research from here, as well,” he says. “Things like individual grants to a grad student or a particular program at a university.”

And how does a company know it’s getting its money’s worth when they provide that kind of funding?

Kuhlmann answers candidly, “There are certain types of research that can only be done by a few people in the world. The work’s so difficult, only a few people are smart enough to do it. The algorithms are very advanced and extremely challenging intellectually. We try to slice the problems in a way that makes the algorithms more manageable, but the classes of complexity are very difficult.

“Ultimately, all engineering is about math, so thinking in a mathematical way is critical. People who don’t have a strong math background don’t succeed in any kind of engineering, and certainly can’t do this work.

“In the end,” Kuhlmann notes, “I believe being a good engineer is in your genes. You’re either born with it or you’re not. I was lucky growing up – I had a place in the basement at home where [I could tinker with things.] My parents never fully understood what I was doing down there, but [they were always supportive]. I was a total nerd, self-trained in electronics, but also a little arrogant.

“One day, the physics teacher yelled at me: ‘Don’t think you know everything!’”

Kuhlmann said that experience was a good one for him, and caused him to apply himself with greater intensity to his studies. The physics teacher wasn’t completely accurate in Kuhlmann’s own evaluation of his intellectual abilities, however.

“I was very dumb in languages!” he says with a laugh.

Yeah, a very Kuhl Kat …



First, a word from the General Chair …

* This year, DAC attendees will see many new developments at the conference – many more than I can cover here. One example is the new DAC Exhibitor Forum, which will provide convenient summary presentations by exhibitors. Attendees will also be able to vote in the inaugural Best of DAC awards, which will recognize exhibitors with awards in several categories, including Best New Product and Best Booth Giveaway. See you all in Anaheim!

Limor Fix

45th DAC Chair

Associate Lab Director

Intel Research Pittsburgh

Next, a brief look ahead …

* IEDM 2008 will be happening in San Francisco in December, with two Short Courses preceding the conference on Sunday, December 14th. The committee for the IEEE International Electron Devices Meeting has issued a call for papers with the deadline for receipt of abstracts being June 27, 2008.

Gary Dagastine

co-PR Director

IEDM 2008

* DATE 09 will be happening next April in Nice. The five-day event will consist of a conference with invited plenary papers, regular papers, panels, hot-topic sessions, tutorials, workshops, two Special Focus days and an Executive Track. The main areas of interest at DATE 09 will be: embedded systems, design methodologies, CAD languages, algorithms and tools, testing of electronic circuits and systems, embedded software, applications design, and industrial design experiences. Please note that all papers have to be submitted electronically before September 7, 2008.

Luca Benini

University of Bologna

General Chair


Then, news that several previous DAC exhibitors may go missing in 2008 …

* Mentor Graphics has acquired the assets of Ponte Solutions. Terms of the transaction were not disclosed, but we do know Joe Sawicki, VP and GM for the Design-to-Silicon division is pleased: “We are pleased to have the Ponte team joining Mentor Graphics’ design-to-silicon business unit where they will contribute to future generations of Mentor solutions,” Alex Alexanian, President and CEO at Ponte, says it makes sense: “While Ponte was providing a solution for today’s requirements, it makes complete sense for Ponte to align with Mentor Graphics to deliver complete DFM technology on
the market-leading Calibre platform going forward.”

* Synopsys has completed its acquisition of Synplicity. The terms of this event were disclosed; $8 cash per share, with a gross transaction of approximately $223 million. As a result of the acquisition, Synopsys has now formed a Synplicity Business Group with Synplicity President & CEO Gary Meyers as its GM. Synplicity Co-Founder & CTO Ken McElvain has also joined the group, “to help architect Synopsys' system-level solutions.”

* A tip from an anonymous source: “If you look at the DAC Exhibitor List, you will notice the obvious – Novas is not listed and has been replaced by Springsoft. Not so obvious is that also missing from the Exhibitor List this year are Fortelink and Silicon Canvas, who both exhibited last year and were doing decent-to-good sales, respectively.

“Guess where those companies are going to be this year. Yes, also all in the Springsoft booth. They are also acquisitions that I understand are currently in the process of closing, or have maybe even already closed, since they were a little lower profile than Novas. Both of these companies were tied to Springsoft from the early days, which certainly makes Springsoft a significant player and clearly now in the ‘Big Five’ of EDA.

“My guess is that Springsoft will now easily be at the $100+ million level, but since there is only moderately good info on two of the four companies here, it’s not possible to nail the number down more specifically. However, it might be closer to the $120 million range. Then again, the total EDA market numbers are always confusing, since adding in revenues from new companies reporting is not really growth. Meanwhile, the Big Three in EDA still seem to be doing creative deals to make it look like there’s short-term growth in the industry, but at expense of future growth. They just don’t get it, do they!”

Some exhibitors may missing, but at least 25 new exhibitors are taking their place …

* The 45th Design Automation Conference will feature 25 organizations exhibiting at this year’s conference for the first time. The new exhibitors run the gamut from IP providers and packaging technologies, to industry organizations and service providers. Limor Fix, DAC 2008 General Chair, is excited: “These first-time DAC exhibitors are a fresh addition to this year’s already extensive exhibitor list. Their diversity exemplifies the exciting developments happening in the industry, as well as the value of exhibiting at this important venue.”

Meanwhile, DAC invites abound from your favorite standards bodies (some with food!) …

* The IEEE Council on Electronic Design Automation (
CEDA) will host a lunch for Dr. Robert Brayton, winner of the Phil Kaufman Award for Distinguished Contributions to EDA. Honoring the Cadence Distinguished Professor of Electrical Engineering and Computer Science from U.C. Berkeley, the lunch will be held June 10th at noon in Room #303AB. Seating is limited.

Soha Hassoun

Associate Professor

Tufts University

* Accellera has formed a
Verification IP (VIP) committee in addition to its other standards committees: Verilog
UCI, and OCI. Qualcomm and Cisco have joined as Board members. Karen Pieper is the Accellera Technical Chair. Bruce Cory will receive the Accellera Technical Excellence Award. Accellera’s DAC events will include a
breakfast panel panel and a
standards presentation.

Shrenik Mehta

Sun Microsystems

Accellera Chair

* OCP-IP will announce the availability of
OCP 2.2 Rev A
, which now includes consensus profiles, and gives a glimpse into the content of OCP 3.0. At DAC, we'll also be highlighting our Debug Specification and White Paper by sponsoring a Debug Workshop with ECSI, as well as publicizing the availability of Part 1 of our NoC Benchmarking Specification and making announcements on Part 2 of the NoC Specification. In addition, we will be announcing the formation of our new Meta Data Working Group and discussing our work with IP-XACT. Finally, we’ll continue unveiling our
CoreCreator II product, which now includes Synopsys’ DesignWare verification IP.

Ian Mackintosh

President & Chairman


* The Open SystemC Initiative (
OSCI), an independent non-profit organization dedicated to supporting and advancing SystemC as an industry-standard language for electronic system-level (ESL) design, will release the final version of TLM 2.0 at DAC 2008. The TLM standard enables model interoperability and reuse at the transaction level, providing an essential framework for ESL design.

Mike Meredith



* The SPIRIT Consortium’s new
IP-XACT 1.4 specification , a new ESL-based spec, expands the range of IP that can be used in an IP-XACT Design Environment and targets new applications, specifically those dealing with transactional modeling and advanced verification methodologies. By using an IP-XACT Design Environment, designers can automatically create many different expressions of a design in a consistent and correlated way. Attend the SPIRIT
general meeting at DAC to learn about the new features and see IP-XACT demonstrations.

Ralph von Vignau


The SPIRIT Consortium

* Open Virtual Platforms (
OVP) will be demonstrating at the Imperas booth the open source SoC, MPSoC virtual platforms. The platforms are available for free download, and include 'bare iron' for MIPS, ARM, and OpenCores processors, and platforms like MIPS Malta booting Linux, and OR1K booting ucLinux. Also shown will be multicore heterogeneous ARM and MIPS platforms and many-core 24 processor examples.

Simon Davidmann



Of course, some of your favorite publications will also be at DAC …

* EDA Weekly, published by IBSystems will be all over DAC. Jack Horgan and Peggy Aycinena will be zipping around soaking up the scene in Anaheim.

Peggy Aycinena

Contributing Editor

EDA Weekly


* SCDsource, published by Tech Source Media, Inc., is an online news and information site dedicated to helping system and chip design decision makers make better design and purchasing decisions. Built from the minds of engineers (contributors to our Focus Group studies and one-on-one interviews), SCDsource also provides a first-of-its-kind SolutionSource supplier directory and DesignAware parametric search engine.

Francine Bacchini

Founder, CEO & Publisher

Tech Source Media, Inc

Ultimately, however, DAC is about the companies …

* Gauda is the first company to introduce technology that accelerates computation for OPC using GPUs (graphical processing units). The company has developed a new breed of algorithms that accelerate the most computation-intensive EDA applications by utilizing both the GPUs and CPUs commonly found in all computers, without sacrificing accuracy. Gauda technology can significantly reduce time to market and improve yield.

Ahmet Karakas


Gauda, Inc.

* Solido Design Automation will be demonstrating SolidoSTAT, its transistor-level statistical variation design tool for analog/mixed-signal, custom digital and memory IC designers. Integrated into the Cadence Design Systems, Synopsys, and Mentor Graphics analog and custom IC environments, SolidoSTAT analyzes circuit failures caused by statistical variation, identifies design weaknesses, and fixes the design making it robust to statistical variation. Solido Design will also be hosting a technical seminar on Variation Robustness for Analog/Mixed Signal, Custom Digital and Memory designs on Wednesday, June 11th.

Amit Gupta

President & CEO

Solido Design Automation

* Xoomsys provides a distributed-processing-based circuit simulation solution that extends the capabilities of qualified accurate SPICE simulators, offering scalable performance on inexpensive Linux computers. For large complex netlists, where precise analysis is critical, Xoomsys improves verification integrity by simulating – without compromise – circuits too big for SPICE, at accuracies FastSPICE cannot achieve. Visit Xoomsys at our booth at DAC.

Anjaneya Thakar

Vice President of Marketing & Applications


* Carbon Design Systems will demonstrate an enhanced version of Carbon Model Studio at DAC that reduces the time to develop and deploy new system models. Carbon Model Studio, the leading solution for the automatic generation, validation and implementation of hardware-accurate software models, features new capabilities to further reduce the time required to generate system level components.

Bill Neifert

Founder & CTO

Carbon Design Systems

* Forte Design Systems invites you to come and see Cynthesizer, the industry standard for ESL synthesis. You'll see how to increase your productivity by 10x, get better results, and eliminate timing closure problems. Also highlighted is a new integration with Synopsys Power Compiler, providing the best power optimized results. Finally, you'll learn how both control-based and datapath designs can be quickly done with SystemC and Cynthesizer.

Brett Cline

Vice President of Marketing & Sales

Forte Design Systems

* Recently, Kilopass was the first to complete qualifications of its high density embedded non-volatile memory technology, called XPM (X-tra Permanent Memory), at 90 nanometers and 80 nanometers. These qualifications support OTP (one-time programmable) configurations up to 128K bits for CMOS SoC applications. Additionally, in the run up to DAC, XPM has already been taped out by multiple customers at 65 nanometers, and will complete 65-nanometer qualification of its XPM technology soon after DAC in July 2008.

Craig Rawlings

Director of Marketing

Kilopass Technology

* Apache's Chip Power Model (CPM) won the EDN Innovation of the Year award for 2007 in the EDA category. CPM is a compact and accurate Spice compatible model of the IC's power delivery network and is one of the key technologies in the company's Sentinel product line, a chip-package-system co-design and co-analysis solution that we'll be highlighting at this year's DAC. Chip-package-board co-design is becoming a hot topic these days as issues of power and signal integrity are no longer contained or isolated between the IC and package/board. We're hearing from customers like ST, TI, and Toshiba that co-design is one of
the key requirements for improving productivity and lowering cost.

Dave DeMaria

Senior Vice President of Chip-Package-System


* Ciranova is introducing the industry's first automated analog layout solution, called Helix. Helix produces design-rule-correct placement in minutes and enables analog IP migration. It optimizes both circuit and device layout simultaneously, delivering design-rule-correct placement comparable in quality to that produced by an experienced layout designer. Using Ciranova Helix, analog and custom designers can explore multiple layout alternatives in minutes, allowing them to get higher-quality designs to market in a fraction of the time needed by conventional methods.

Dave Millman

Vice President of Marketing


* Denali Software
will be highlighting our selection of industry-leading EDA and high-quality standards-based IP solutions for DDR3 and PCI Express 2.0, support for SystemVerilog-based methodologies and verification IP for all protocols, and our new FlashPoint PCIe NAND Flash platform solution. Schedule a meeting with our experts, or register for the famous Denali Party at DAC!

David Lin

Vice President of Marketing

Denali Software

* Javelin Design Automation unveils the first Specification-Driven floorplanning and prototyping family for early design feasibility from spreadsheet, black-box, ESL, partial and dirty RTL through to netlist. j360 TrueFit, TruePlan, and TruePro enable business users, architects, logic designers and chip integrators to predict, see, fix, and optimize SoCs closeability earlier in the project cycle. High-Performance-Teams use j360 to achieve challenging targets in less time.

Diana Feng Raggett

President & CEO

Javelin Design Automation

* CebaTech develops and markets ESL tools for advanced ASIC, FPGA and SoC design, and uses these tools to create and license high-value IP cores. Visit us in our booth to see demos of our C2R Compiler with both data path and control path dominated designs, and discuss our current and future IP cores for the networking, storage, communication system and server markets.

Elaine Jones

Vice President of Marketing & Business Development

CebaTech Inc.

* IC Manage will demonstrate its design data management, project management, and design IP reuse solutions at DAC. IC Manage offers advanced revision control, hierarchical IP-based configuration management and design IP reuse capabilities, and includes out-of-the-box integrations with EDA environments (including Cadence/Synopsys) and issue management/bug tracking systems (including Bugzilla/JIRA). IC Manage addresses the extreme performance, capacity, scalability, and reliability requirements of globally distributed design enterprise. Visit us in our booth.

Dennis Harmon

Vice President of Business Development

IC Manage

* Gradient Design Automation pioneered accurate, fine-grain IC thermal analysis that produces a 3-dimensional temperature map of a chip. Gradient’s products fit into the standard EDA flows, and help to expose thermally induced circuit failures and performance degradations before tapeout, so that corrective actions can be taken. By adding temperature-awareness to the design flow, Gradient improves circuit simulation accuracy and exposes opportunities to neutralize the temperature effects, as well as improve the chip design.

Ed Cheng

President & CEO

Gradient Design Automation

* ATopTech launched in December 2007, and will be showcasing for the first time at DAC, the company's flagship product, Aprisa. Aprisa is a complete netlist-to-GDSII physical design solution, including floorplanning, placement, clock-tree synthesis and optimization, global and detailed routing, and an extremely fast timing engine to handle complex timing challenges such as OCV and MCMM. Aprisa uses state-of-the-art multi-threading and distributed processing to further speed up the process and avoid the exploding runtime issues with modern nanoscale design. Contact us to set up an appointment.

Eric Thune

Vice President of Sales & Marketing


* Bluespec invites you to come see synthesizable models and testbenches running 35,000 times faster than event-driven simulation, our new development workstation, and Nikhil and Arvind at Sunday's high-level synthesis workshop. Come see atomic transactions for hardware – there's a reason we've picked up six new tier-one customers this year, and why we're the only general-purpose high-level synthesis solution for synthesizable models, testbenches, and control and algorithmic IP.

George Harper

Vice President of Marketing


* Concept Engineering develops and markets innovative visualization and debugging technology for commercial EDA vendors, in-house CAD tool developers, and IC and FPGA designers. We will be showcasing all of our visualization and debugging products at DAC, including: Nlview Widgets - a family of visualization engines for EDA tool developers (Tcl/TK, MFC, Qt, Java, Perl/Tk, wxWidgets), SpiceVision PRO - a customizable debugger for SPICE and DSPF based designs, RTLvision PRO - a graphical debugger for SystemVerilog, Verilog and VHDL based designs and GateVision PRO - a customizable debugger for Verilog, LEF/DEF and EDIF based designs. Stop by and
visit us in our booth.

Gerhard Angst

President & CEO

Concept Engineering

* Esterel EDA Technologies signed corporate deals with Texas Instruments and STMicroelectronics last December. This follows several successful projects with Esterel Studio in 2007 at these two major companies. In term of technology, Esterel Studio 6.0, comes with a performance estimator that guides new users unfamiliar with ESL control synthesis in comparing micro-architecture choices, balance between area and speed, and a check that they have not generated unwanted logic.

Günther Siegel


Esterel EDA Technologies

* Spatial is a first-time exhibitor at this year's DAC. We are a market-leading provider of 3D software components for technical applications, providing 3D software and consulting services to EDA industry leaders like Agilent, Ansoft, CST, Synopsys and Zuken. We will be demonstrating a new, integrated solution tailored specifically for the needs of EDA 3D analysis developers, which enables rapid development of 3D analysis and visualization features within current physical EDA flows. Come see us in our suite at DAC.

Howie Markson

Director of Marketing


* Do you suffer from memory loss? Talk to Sidense at DAC. We’ll show you how SiPROM and our new low-power SLP one-time programmable (OTP) memory IP can enhance your chips in a wide range of digital and analog applications, providing secure, high-density and reliable embedded storage. Hear us talk and meet with us at the ChipEstimate.com booth, and catch the Sidense/ChipEstimate.com breakfast panel Wednesday morning. Our goal: OTP on every chip.

Jim Lipman

Director of Marketing


* At DAC’08, Synopsys will show the many ways you can count on us to be your primary vendor: for Hot Technology (IC Compiler, HSIM XA, Design Compiler Graphical and MVSIM); for Cool Solutions (Eclypse Low Power, Multi-Core Performance, VMM Methodology and Analog Mixed-Signal Verification); and for our commitment to the design community.

John Chilton

Senior Vice President of Marketing & Strategic Development


* Customizable EDA building blocks are changing the way people think about EDA. Instead of relying on one size fit all standard tools, EDA building blocks enables semiconductor companies to have their own customized tools that really address their needs. At DAC, SoftJin will be demonstrating several of its high-performance EDA IPs across domains such as post-layout EDA, FPGA synthesis and routing. These customizable EDA IPs are helping our customers get advanced and proprietary functions in their tools and flows, thus helping create differentiation over their competitors.

Kamal Aggarwal

Vice President of Marketing & Strategy


* SynCiras' fully automated and integrated analog place-plus-route technology changes how layout will be done. Our 2nd generation technology enables your analog circuit designers to synthesize multiple layouts of complex hierarchical analog circuits with thousands of devices at blazing speeds. All layout solutions are 100% constraint compliant, achieving optimized device placement and routing with maximized packing density, with no loss in circuit performance in a single pass, slashing analog circuit layout time from weeks to hours. Now circuit designers have true concurrent circuit and layout development. Also, speed and ease-of-use makes
prototyping and floorplanning quick and communicating layout instructions accurate.

Karl Kobata


SynCira Corp

* Imperas will be showing new products solving embedded software debug, verification, and analysis issues, particularly as these issues occur on multicore platforms. The new multicore debug and MIPS Linux developer workbench will be demonstrated including application debug on SMP Linux. Tools to build virtual platforms using SystemC and SPIRIT IP-XACT will also be shown.

Larry Lapides

Vice President of Sales


* EVE, the leader in hardware/software co-verification, will showcase a library of standard transactors and a new custom transactor development tool at DAC. An AXI Master/Slave transactor and a PCIe Gen 2.0 16x transactor have been added to EVE’s standard protocol library. ZEMI-3, a transaction modelling methodology to create transactors for custom protocols, raises the abstraction level for hardware debugging.

Lauro Rizzatti

General manager


Vice President of Worldwide Marketing

* Agreement grows on the importance of co-design of chips, packages and boards, but the modeling considerations can be confusing for design teams. Model availability, frequency dependent accuracy considerations and abstraction level are just some of the issues. This has led Sigrity to support flows that run the gamut, while continually working to simplify user-level considerations.

Leslie Landers

Vice President of Sales & Marketing

Sigrity Inc.

* DAC’s Wireless theme fits well with Agilent Technologies’ high-frequency background. High-frequency and high-speed design worlds are colliding where designs using multi-Gb/s data rates are seeing effects previously seen only in RF and microwave designs. At DAC, Agilent EEsof EDA is showing how its breadth of high-frequency simulators can be used to analyze the complete serial link.

Lisa Hebert

Customer Communication Manager

EEsof EDA Division

Agilent Technologies

* ViASIC leverages reconfigurable semiconductor fabrics – slashing mask costs up to 95% versus a standard ASIC design approach, and reducing design time and risk in rad-hard, mil/aero and FPGA conversion applications. Visit our booth for a demo of ViaPath, our patented one-mask configurable logic and memory semiconductor technology. It offers the highest system density for embedded SOCs or structured ASIC fabrics.

Mark Goode

President & CEO

ViASIC, Inc.

* Xilinx’ new ISE Design Suite 10.1 provides a unified design environment to help users maximize both design performance and productivity, whether their designs require a flexible embedded processing solution, a specialized flow for DSP development, or optimal high-performance logic. The ISE Design Suite includes PinAhead technology to simplify the complexities of managing FPGA to PCB I/O assignment for all designers.

Mark Goosman

Product Marketing Manager

ISE Design Tools


* Micro Magic has improved our tool flow by adding support for OpenAccess. We have also added PCell interoperability through IPL PyCells. Curious engineers can register for Micro Magic's GDS and OpenAccess viewer – MAX-View – free of charge. Micro Magic has also added features to our unique datapath compiler DPC. This datapath tool provides higher-performance and lower-power for datapath intensive designs.

Mark Mangum

Sales Manager

EDA Tools & Chip Design Services

Micro Magic

* Launched in early 2008, Mentor Graphics' inFact intelligent testbench automation solution is the first to use intelligent algorithms to synthesize meaningful testbench sequences, while allowing the user to set verification goals prior to simulation and determine verification priorities. The inFact algorithms rapidly generate test sequences, data, and checks on-the-fly during simulation, achieving the highest levels of functional coverage and early detection of design bugs.

Mark Olen

Product Marketing Manager for inFact

Mentor Graphics

* Certess, the provider of functional qualification solutions for SoCs and IP blocks, will be showcasing Certitude and Certitude-SV. Certitude provides verification engineers with an objective way to evaluate and improve the completeness of the verification environment, resulting in shorter and more predictable process to integrate SoC designs. Certitude easily complements all existing verification environments. Certess will also be hosting several customer and industry leader presentations in their booth. Space is limited for customer presentations so please register in advance. If there was a bug in your design, could you find it? Visit our
booth at DAC and find out.

Michel Courtoy

President & CEO

Certess, Inc.

* Verific Design Automation is Head and Shoulders above the Rest. We offer SystemVerilog and VHDL front ends for EDA developers. Check out Verific’s Wall of Fame in our DAC booth, and see the 50+ logos of companies that standardize around our parsers and elaborators. Or, walk the show floor and come across several of Verific’s 20-something licensees exhibiting at DAC this year. You’ll agree: Head and shoulders above the Rest!

Michiel Ligthart


Verific Design Automation

* Satin IP Technologies is a first-timer at DAC. We will demo VIP Lane, a Design-for-Reuse Assistant enabling semiconductor companies to deploy their home-made design-for-reuse methodology internally, with maximum adoption rate by the design teams. What makes VIP Lane hot and innovative? It supports proprietary design-for-reuse practices, offers checklist-driven assistance to IP designers, and monitors IP quality closure on-the-fly.

Michel Tabusse

Founder & CEO

Satin IP Technologies

* Atrenta helps customers get their designs right, at RTL and earlier, to speed-up implementation and verification. We call it Early Design Closure. The benefits? Better performance, predictable schedules, and reduced design risks. We'll announce a new architectural-level product before DAC, and pre-packaged methodologies at DAC. A comprehensive tool suite and proven methodologies for easy adoption - Early Design Closure for everyone.

Mike Gianfagna

Vice President of Marketing


* Berkeley Design Automation will be showcasing their Precision Circuit Analysis tools at DAC 2008. Berkeley's Precision Circuit Analysis tools deliver true SPICE accuracy 5x-10x faster and with 5x-10x higher capacity than any other tools for circuit simulation (Analog FastSPICE), device noise analysis (Noise Analysis Option), multi-tone periodic analysis (RF FastSPICE) and phase noise analysis (PLL Noise Analyzer). As the first major breakthrough in analog and RF verification in decades, this technology enables design teams to solve big analog/RF verification problems that would otherwise be impractical or impossible. Visit our website to
sign up for a suite appointment at DAC.

Mick Tegethoff

Director of Technical & Product Marketing

Berkeley Design Automation

* Calypto Design Systems will distribute free copies of its PowerPro-filer that calculates Clock-Gating Efficiency and the percentage of registers clock gated in an RTL design block. Clock-Gating Efficiency measures the percentage of time a register is gated (turned off) for a given set of activity vectors making it a better indicator of dynamic power savings.

Mitch Dale

Director of Product Marketing

Calypto Design Systems

* Pyxis Technology will demonstrate NexusRoute at DAC, and feature a customer video outlining why NexusRoute was named one of EDN’s Hot 100 Products for 2007. Visit our booth or catch the Exhibitor’s Forum on June 11th at 9:15 am to hear about how Pyxis helped customers like Microsoft achieve faster design closure, better performance, and lower power. While you are there, signup for a chance to win your own copy of Guitar Hero III.

Mitch Heins

Vice President of Marketing

Pyxis Technology, Inc.

* Tela Innovations will be showing its solution for the 'sub-wavelength,' low-k1 era – 45 nanometers and beyond. The Tela solution uses gridded, straight-line, one-dimensional layout structures to produce a lithography-optimized layout. It is applicable for use in logic, embedded memory, analog, and I/O functions. The result of using Tela's pre-defined, predictable topologies is significant improvements in variability, performance, leakage and area. The solution is complementary to existing SoC design flows using synthesis and conventional cell-based design methodologies.

Neal Carney

Vice President of Marketing

Tela Innovations

* In April 2008, Envis announced its mission to dramatically reduce power for SoC designs, automatically! Chill, an intelligent, push-button solution for both dynamic and static power reduction, is based on unique, proprietary clock-gating technology. Envis also announced Kelvin, an automatic power pattern generation (APPG) solution. Visit Envis at DAC 2008 and see what’s cool in power reduction!

Paul McLellan



* Unlike coverage-driven RTL verification, OneSpin’s recently-announced GapFreeVerification process ensures error-free digital modules and IP – and considerably reduces verification effort. At DAC 2008, we’ll show visitors how. We’ll also present how our 360 Module Verifier supports formal SystemVerilog assertion-based verification, using both new and legacy assertions. Most important, we’ll be showing our latest, yet-to-be-announced breakthrough in formal RTL verification.

Peter Feist


OneSpin Solutions

* DAFCA will be showing ClearBlue at DAC, which accelerates and automates hardware-software validation. Our on-chip instruments are seamlessly inserted pre-silicon and configured, operated, and controlled post-silicon with a comprehensive set of analysis and stimulation tools. They can also be accessed by system and application software. ClearBlue is used in simulation, emulation, and FPGA-prototype environments – in addition to final silicon – and doesn’t require special pins or cell libraries.

Peter Levin

President & CEO


* Liga Systems will be demonstrating NitroSIM v1.0 – the 1st release of our hybrid simulation technology that accelerates functional Verilog simulation by 10x. The technology has matured in half a dozen beta sites for one-and-a-half years in applications such as graphics processors for video game industry, networking, and broadband digital broadcasting in single chip to multi-chip verification projects. Visit us in our booth at DAC.

Raj Mathur

Director of Technical Marketing

Liga Systems

* Jasper Design Automation delivers Formal Verification Unleashed – an advanced verification methodology for complex designs from architecture to silicon for: designing, exploring and debugging RTL; verification of block-level functionality; comprehensive regression testing; and fast silicon validation and debug. Jasper's high-capacity, high-performance formal verification uniquely delivers benefits across the design flow. Visit Jasper in our booth at DAC.

Rajeev Ranjan


Jasper Design Automation

* Real Intent is showing verification tools powered by formal analysis technology. This includes Ascent all-in-one automatic verification with its new combined LINT and automatic formal analysis, Meridian CDC (Clock Domain Crossing) analysis software, the leading formal powered clock analysis tool for verifying clock domain crossing design and PureTime for verifying Synopsys Design Constraints (SDC) false and multicycle paths with fully sequential accuracy.

Rich Faris

Vice President of Marketing & Business Development

Real Intent

* Please come to the Silicon Canvas booth, to see how our Laker custom IC design solutions make better chips with less effort. Our demos feature Laker’s automated custom layout tools with our drag-and-drop schematic-driven layout flow, as well as constraint-driven custom placers and custom routers, including our new matching device solution. We are also showing Laker interoperability and run-time model integration with OpenAccess.

Rich Morse

Director of Marketing

Silicon Canvas

* Breker Verification Systems knows chip designers are concerned with the outputs derived from circuit functionality. Iterating and tweaking constrained random test case generators to define input transitions is no longer an efficient way to accomplish functional verification goals. One approach that’s gained momentum is “coverage model-driven scenario generation” technology that defines the verification space and automates input stimulus generation based upon design outcomes. A coverage model approach works best and gives the highest percentage coverage when combined with graph-based GUI technology. How does a graph-based GUI work in
functional verification? Come visit us in our booth at DAC and find out.

Rick Nordin

Vice President of Marketing

Breker Verification Systems

* Virage Logic will be featuring its recently introduced 40-nanometer SiWare memory compilers and logic libraries that enable SoCs to run faster, manage power more efficiently, use less area, and achieve higher manufacturing yields. We will also be featuring our Intelli DDR solution, an all-digital implementation including the PHY and DLL that delivers smaller area, lower power, and significantly easier portability to any process node for any foundry. Come visit Virage in our booth at DAC.

Sabina Burns

Vice President of Corporate Marketing

Virage Logic

provides advanced solutions for layout finishing and mask-data preparation. At DAC 2008, XYALIS will release a unique mask-data management flow including support for 1X Masks, Multi-Layer Reticles, and Wafer Plan, as part of our production-proven GTmuch and GTframe tools. XYALIS presents enhancements to its metal-filling solution, GTstyle, to further improve the yield of 90-nanometer, 65-nanometer, and 45-nanometer designs.

Samuel Perraud

Sales Manager


* IMEC advances state-of-the-art technology by joining process technology and design methodologies, housing process and design technology under one roof, and working to bring the industry up-to-speed for designing in the newest technologies. IMEC's technology-aware design research pursues analysis and design solutions for sub-45-nanometer scaling-induced problems that can be compensated at the system level. The focus is on variability- and reliability-aware modeling, as well as ways to cope with their effects at the system level. IMEC's multi-processor system-on-chip research focuses on tools that assist software developers to distribute
applications over multiple processors, whilst handling task-synchronization and inter-task data exchange. IMEC's unique Clean C code style and toolbox increase the efficiency of mapping sequential C on multi- and many-core platforms.

Serge Vernalde

Technical Business Director

Nomadic Embedded Systems Division


* IC designers face extreme challenges with time-to-market pressures, and the need to rapidly reduce cost and re-use as much as possible. Synfora, the premier provider of algorithmic synthesis tools used to design complex SoCs and FPGAs will be highlighting our PICO Extreme solutions at DAC this year. PICO Extreme solutions deliver the best results faster -- including lower power from state-of-the-art algorithms and 20-50 percent reduction in cost, along with low risk step-by-step deployment. Synfora will also be presenting our solutions at various workshops at DAC. Visit our website to explore our presentation schedule.

Simon Napper

President & CEO


* Until now, Design Data Management vendors have offered custom integrations/adaptors for a limited number of design flows such as Cadence Virtuoso. However, there are a number of design tools out there and it is just as important to make sure that ALL design data is managed. ClioSoft will be showcasing the Enterprise Edition of our SOS Data Collaboration Platform at DAC, including our breakthrough 'Universal DM Adaptor' technology that enables management of design data from practically any EDA tool, and therefore "future proofs" your DM needs for any new flows you may adopt.

Srinath Anantharaman

Founder & CEO


* Mentor's Olympus-SoC is a netlist-to-GDSII system that concurrently analyzes and optimizes for variations in process corners, manufacturing, and design modes. Based on patented multi-corner multi-mode technology and an ultra-compact data model, it addresses the performance, capacity, time-to-market, and variability challenges occurring at the leading edge. Product highlights include adaptive variability engine, multi-corner multi-mode Clocktree Synthesis, DFM-driven routing, embedded signoff quality timing engine, multi-corner multi-mode SI, and advanced chip assembly capabilities. It’s been proven with many tapeouts.

Sudhakar Jilla

Director of Marketing

Olympus-SoC Product Line

Mentor Graphics

* ChipVision’s breakthrough ESL power-optimization design tools meet critical power budgets early in the design cycle. 60x faster than lower-level methods, PowerOpt lets designers explore and visualize timing/area/power tradeoffs to create power-optimized RTL code with a 3x power reduction in critical semiconductor blocks. Using P-SAM, architects analyze power consumption in system design alternatives to optimize power management. See demos in our booth at DAC!

Thomas Blaesi

President & CEO


* Time to Market (TTM) will highlight its proven low-power and DFM capabilities for 65-nanometer and below designs in our booth at DAC. TTM offers a cost-effective, reliable and dependable path for taking a design from concept to silicon for large and complex designs in 90- and 65-nanometer silicon, with SERDES high-speed interfaces and flip-chip packaging. Our expertise spans consumer, networking, and communications electronic devices.

Venkata Simhadri

President & CEO

Time to Market

* Nusym Technology is focused on intelligent verification technologies which utilize design insight to enable rapid verification closure, while leveraging existing testbench and language infrastructures. We will be holding suite demonstrations at DAC to share results of early adopter evaluations of this breakthrough technology, demonstrating specifically how it automatically targets "hard to hit" coverage points, testbench tuning for maximum coverage, and accurate coverage analysis.

Venktesh Shukla


Nusym Technology

* Sequence Design’s PowerArtist delivers the industry’s fastest automated RTL power reduction – 10-to-50 percent or more, depending on the design – in just minutes on a million-plus gate block. It cuts power in three key areas: clock, memory, and datapath at RTL, while preserving the original RTL formatting. Users can generate power savings automatically or manually through a powerful new GUI.

Vic Kulkarni

President & CEO

Sequence Design

* CoFluent Design will make a major announcement at DAC about CoFluent Studio V3, the world-first ESL graphical modeling and simulation framework built on Eclipse technologies and leveraging the Eclipse Modeling Framework (EMF). A preview version will be demonstrated in our booth at DAC. Benefits offered by EMF include models imported/exported from different modeling environments, which will be illustrated by a CoFluent-UML model transformation. We will also demonstrate a full C-based ESL-to-implementation flow, combining CoFluent Studio and Mentor Graphics’ Catapult Synthesis, and illustrate how our tools can close the validation loop by
automatically generating test cases for cycle-accurate verification from ESL-use cases validated against a transactional reference model.

Vincent Perrier




See you in Anaheim!



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-- Peggy Aycinena, EDACafe.com Contributing Editor.