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DAC. And yep, the survival of both of these conferences is hanging in the balance. So, have another brezel und bier, and enjoy the world as it morphs before our very eyes.
people complained to me that it was oh-so-quiet this year compared to years past. But they were wrong. There were 4700 people at DATE 08, virtually the identical number of people who attended DATE 07 in Nice.
There were approximately 80 companies exhibiting at DATE in Munich, compared to upwards of 150 in the Before Time. Just under half of the booths were located in the cavernous lobby of the building, while the remaining booths were set up in the front half of Hall B – the back half of Hall B being a bit empty. Clearly, neither that layout nor the number of companies exhibiting actually impacts the progress of technology, but it is a comment on what folks may be thinking about the ROI associated with the costs of conferences.
develop qualified leads in Munich, and were well satisfied with the ROI of exhibiting there.
University, explained the time-tested process that resulted in the 198 papers on the program, chosen from 839 submissions – 50% from Europe, 30% from the U.S., and 20% from Asia, the Middle East, and South America. Peng also noted a 50% increase in submissions in the area of embedded software for this year’s conference. [Not surprising, given that Embedded World in Nürnberg earlier in March showcased 800 exhibitors for 17,000 (!!) attendees.]
Rudy Lauwereins, Herman Beke, Volker Dueppe, Peter
Marwedel, Wolfgang Rosenstiel, and Gabriele Saucier. Lauwereins was also honored with the IEEE Computer Society Outstanding Contribution Award, presented by Yervant Zorian. Zorian presented, as well, the IEEE TTTC medal for Lifetime Contribution to Jack Arabian.
The keynotes during the opening session were delivered up by EPFL’s Professor Giovanni De Micheli, previously of Stanford, and Thales CTO Dominique Vernay. De Micheli gave a wide-ranging talk about the social good that’s to be had by applying a broader view of design automation to emerging micro and nanotechnologies, and system-level design. By defining “audacious goals” for the technology – working to break language barriers, to eliminate energy dependence, to monitor and protect a fragile environment, to implement early warning systems for natural disasters, to further lab-on-chip work, and make progress in synthetic biology
– he argued researchers will be pushed to solve today’s thorny power, manufacturing, and materials problems, which will in turn, attract the best young researchers into the field.
De Micheli suggested the tasks he laid out were not easy, but that complex, multi-variate systems could and should be designed. The results, he said, will “expand our horizons and [increase our] commercial viability. EDA vendors need to keep the faith, look at things from a systems perspective, and realize that most of the potential of the technology is still untapped.”
Following De Micheli’s rousing talk, Dominique Vernay spoke to the history and definitions of embedded systems, their “plurality of realities,” and their market size – doubling every 5 years, with no end in sight: $46 billion in 2004, $88 billion in 2009. He noted what all in the room already knew: 80% of the innovation in newly minted automobiles resides in the embedded systems onboard. Vernay lamented the gap between design and implementation in all classes of embedded systems, and ticked off a laundry list of improvements needed in the technology: more functional value, more data processing capability, more reliability, more spatial integration, more battery
autonomy, and more integration into complex, centralized, wireless information systems.
Vernay invoked Moore’s law, raised the specter of two major hardware challenges – reduced footprint and increased parallel processing – and laid out a 10-year road map for embedded systems. He said further implementation of embedded systems in mission critical applications would depend on adhering to the roadmap, and noted that additional industry standards, as well as correct-by-construction design techniques were also crucial. No one in the audience took issue with his closing message: We must educate under the “Systems” banner and learn to engineer for uncertainty!
* Following the keynotes, I dashed to the Press Room for a brief, informative meeting with Rich Faris from Real Intent. We talked about the proliferation of clock domains on-chip, the problems of structural analysis in hardware design, and the ability among users to apply formal verification in their flows. Faris said, “If static, formal, assertion-based verification is only for PhD's, it’s not useful. As vendors, we need [to make formal useful], to sell to a larger population, and [to insure] that at least 50 out of 100 designers can actually use it.”
Next, I rushed to the EDAC/Synopsys organized panel on ESL. Having moderated a couple of panels in this topic area myself over the last several years, and having attended even more as an observer, I’m beginning to believe quite honestly that this material has been hashed over too many times in a panel venue.
Having said that, Mentor Graphic’s Simon Bloch moderated a lively discussion between Infineon’s Wolfgang Ecker, TU Braunschweig’s Rolf Ernst, Synopsys’ Joachim Kunkel, Ericsson’s Peter Nord, The MathWorks’ Ken Karnofsky, and Altera’s Misha Buric. Bloch asked if there’s a definition for ESL. Kunkel said no, while Karnofsky, Ernst, Buric, Nord, and Ecker all said yes, but with a host of qualifications. My two take-aways from this session: Implement ESL and harvest the benefits; and there’s a Peter Principle in ESL. The
next level above the current level of design abstraction is always the one that should drive the specifications. Oh yeah, two more things: There are more software designers in the world than hardware designers, and the gap’s increasing; and by 2010 there will be 100 million lines of code residing in your average automobile.
I left the ESL panel early to catch the final talk in Session 1.7, presented by Srinivasan Murali, and learned a bit about an EPFL research project: “A method for temperature controlled dynamic frequency scaling of multi-core systems.” Pretty interesting stuff requiring further reading, but the uber-lesson was clear: Multi-core systems dissipate a lot of heat in a non-uniform kind of way, creating hot spots on-chip. Novel, innovative solutions must be developed if such systems are to realize their full potential, particularly in embedded, mobile applications.
* Back in the Press Room, I wolfed down lunch (second chocolate croissant and third cappuccino of the day, courtesy of the Magical Monique who kept things running smoothly there day after day during the conference), scanned the DATE program, regretted that it’s not possible to attend 2 or 3 sessions as once, dashed back out past the many people coming and going from the various, day-long OSCI/European SystemC Users Group meetings across the hall, and was only 5 minutes late to a fascinating 30-minute chat with Rudy Lauwereins in the IMEC booth.
IMEC researchers have developed a set of 28 guidelines and restrictions which C programmers can use to help nudge their code into some sort of parallizable structure. Lauwereins and others believe it will go a long way towards alleviating the daunting challenge of producing C code that can actually take advantage of the multi-core megaliths the hardware world is pumping out.
I asked Rudy if we all wouldn’t be better off working towards realizing a true parallizable language instead. His response: As far back as when he was working on his PhD in the 1980’s, the world has thought to produce such a language. Today, there are as many languages for parallel coding as there are universities, nobody can agree, and yet work still needs to get done in the real world. Let’s use the IMEC C-code guidelines as an excellent, stopgap measure until somebody, somewhere can finally establish a widely used language to more effectively solve this huge, huge problem.
Next, I arrived late for the Rich Wallace (EE Times) moderated panel: “From IDM to Fab-lite: Changes in your EDA Strategy.” As the bulk of the semiconductor companies in Europe have shed their manufacturing capability of late, this discussion had particular currency. NXP’s Barry Dennington said, “A strong affiliation with a foundry partner ecosystem is mandatory, [along with] eliminating duplicated activities such as internal tool development and multiple flows.”
Synopsys’ Antun Domic said, “More money must go into R&D. As the process technology is no longer the differentiator, the design becomes the differentiator instead.” Not surprisingly he also said, “Collaboration with EDA is the key component to success.”
When pressed by Wallace, Dennington replied, however, “Any organization that understands how the tools work together and has the capability of tying together those tools could be a partner to the design house. It could be the foundry, or it could be other companies who manufacture the products, or have a service business and want to step into the design flow.”
Wow. Scary stuff, if you’re an EDA vendor. Or, exhilarating if you’re a TSMC. A question from the floor made the same point: “The center of gravity in the semiconductor business is moving towards the TSMCs of the world, companies that are strongly involved in manufacturing, but also have efficient and complete design flows. Add to that, the fact that there are a bunch of designers coming online just across the Straights of Taiwan. Can you comment?”
Domic replied, insisting that reference flows – TSMC’s 8.0, for example – are not design flows, plus the foundries still rely heavily on the big EDA vendors for input. The Questioner replied, “Yes, but they’re working at 45 nanometers, they’ve already instituted statistical timing analysis, and they’re very advanced.” Domic was unperturbed: “The TSMC flows are based on Synopsys, Cadence, or maybe Magma, and it’s still a non-trivial step from a reference flow to a design flow.”
Dennington said he was “well aligned” with Domic, but added, “It’s a question of who will step up with a solution – the EDA vendors, the design houses, or the foundries. As far as product design is concerned, I don’t see that on the horizon [from TSMC]. We all know how much heritage skill and engineering you need to have competitive products on the market.”
I was pretty sure everybody in the audience understood heritage skills, but nobody was reassured that future consolidations around foci like TSMC were not in the cards. Asia – China, in particular – is in ascendancy in semiconductors in design, manufacturing, and product implementation. Face the reality.
* My final session of the day was a panel moderated by Synopsys’ Tom Williams: “The Perils of 45 nm: A report on the move.” I know I was supposed to come away impressed with the perils, but instead I came away impressed that the move’s going fairly smoothly.
From Cavium Network’s Anil Jain: At 45 nanometers, there are all of the challenges at 90 and 65 nanometers, plus some. There’s mobility variation, local stress variation, poly length variation, and interconnect variation problems all cropping up at 45, but people are going there nonetheless.
IMEC’s Rudy Lauwereins says they’re past 45 nanometers: We’re working on software-designed radio at 32 nanometers, where the longest path delay is in nanoseconds.
From Cadence’s Ted Vucurevich: At 45 nanometers, complex SoC designers are the early adopters. They’re using aggressive low power strategies, laser annealing of gates, a more limited palette to meet manufacturing concerns, less statistical analysis, more design rules, more design reuse, and more software engineers to make the move to 45 nanometers. There are fewer fabs at 45 nanometers because of consolidation of manufacturing, but there’s more partnering, more aggregation of investment, and more people passing on 65 nanometers and going straight to 45.
From Matsushita/Panasonic’s Yoshifumi Okamoto: Shrinking geometries are a source of competitive edge for consumer products. [We were] at 130 nanometers on a 200mm wafer in May 2002. We were at 45 nanometers on a 300mm wafer by 2007, successfully reducing chip area to 19% of the 2002 area.
From STMicro’s Jean-Pierre Geronimi: We’re doing design-flow optimization and silicon validation on a highly integrated 45-nanometer demonstrator SoC with low power features. Compared to forecasts from a few years ago, it’s not really a bad technology node. So far, so good.
* Leaving the 45nm panel, I had a brief chat in the hallway with Professor Daniel Gajski from U.C. Irvine about the Case of the Missing Parallel Programming Language. Gajski proposed that 5 companies come up with $10 million dollars each, to be distributed in $2 million chunks to 25 different universities. After 2 years, each university team would submit their proposed language to a jury of experts. The most worthy candidate language would be selected, and then developed to maturity for implementation across the industry. The other option, per Gajski, is to wait another 25 years and have as little to show for it as the last 25 years of disorganized
effort has produced. Those who know Professor Gajski know he wasn’t kidding.
It was 6 PM and the sky outside was darkening. I found my way to the Exhibition Theater at the back of Hall B, where a growing crowd was gathering to hear Mentor Graphics’ Wally Rhines welcome everyone to DATE on behalf of the EDA Consortium. Rhines detailed the Who, What, and Why of membership in EDAC, invited non-members to join up, and said the wine was on the house. Although numerous booths across the Exhibition Hall were providing wine, beer, and appetizers as well, there was a remarkably good turn-out for the EDAC reception – organized by EDAC’s Bob Gardner and Jennifer Cermak, who also patiently
oversaw the Exhibition Theater throughout the week at the conference.
Tuesday finally drew to a close, for Press and Analysts at least, at a dinner back in downtown Munich – a rollicking Bavarian meal hosted by ACE, Compaan Design, Coresonic, Fenix Design Automation, and VaST Systems. The Annual International Casual Press & Analysts Dinner at DATE has become a well-known fixture for those lucky enough to be invited, and this year’s event at the Spatenhaus was no exception. A round of applause for the sponsors, and to DATE Press Chair Fred Santamaria who sets the whole thing up year after year after year.
Wednesday at DATE 08
* Given the persistent nature of jet lag, and the ubiquitous nature of bier in Munich, Wednesday morning is always a tad harder to negotiate than Tuesday morning at DATE. It didn’t help that the storm that had plagued Northern Europe earlier in the week, was now bringing its sturm und drang to Bavaria.
Nonetheless, true conference warriors were front and center for the 8:30 AM sessions on March 12th in the ICM. For me, that was: “Physical Architectures,” moderated by U.C. Berkeley/Cadence’s Alberto Sangiovanni Vincentelli. This was the first of many special sessions on Wednesday at DATE about automobiles.
General Motors’ T. Forest talked about the newish FlexRay x-by-wire data bus architecture: “The design and configuration of the FlexRay communication cycle is quite complicated.” He detailed the complications and sold me on the idea of sticking with the older, trusted (but markedly slower) CAN protocol. That probably wasn’t Mr. Forest’s intention, but it was early morning and the older way just seemed easier and less fraught with fret.
Next up, Alberto Ferrari – representing a host of industry players including Parades, STMicro, and Freescale – spoke at length about standards for SIL, Safety Integrity Level, and convinced me that “auto applications are increasingly dependable, because reliability and safety requirements are prime concerns in the definition of the electronic solutions [found onboard].” That’s good news. Ferrari also hinted that, like their counterparts in aeronautics, folks in the auto industry favor evolution over revolution. That also sounded good before the first espresso of the day.
I left the session early to dash up to the Press Room, not for Monique’s cappuccino, but for a meeting with EVE’s VP of Marketing Lauro Rizzatti. He told me, “The only way to address embedded software is through validation. We’re now Number 2 [behind Cadence] in the market, and [because of our speeds] don’t believe we [actually have any] competitors in emulation.”
Back down to the Exhibition Hall, I had 30 minutes in the Synopsys booth and a substantive discussion with Steve Smith about the company’s newly announced multi-core initiative. Smith said, “Synopsys is now taking multi-core seriously. Our customers are demanding multi-thread [versions of Synopsys tools], because they’ve got multi-core systems and want to use them.” Smith added that, with 14,000 servers crunching away for their own internal developers, Synopsys will benefit from progress in the multi-core/multi-thread arena, as well.
* Rushing next to Session 5.7, I sat in the back of an SRO room and sank down deep in my chair. Like some post-modern John le Carré character, I felt to be one of the few (possibly only) Americans in the room as Philippe Reynaert spoke about two new European R&D Joint Technology Initiatives (JTI), ARTEMIS for embedded systems and ENIAC for nanotechnology.
Reynaert detailed the financial rules, the layout of the decision-making bodies for the JTIs, and how the various entities – industry, academia, the European Community, and Member States – would contribute both resources and manpower to drive the initiatives forward. He said the projected budgets for ARTEMIS and ENIAC would approximate 115 million euros in the short run, with goals of 2 billion and 3 billion euros, respectively, over the next 5 years.
The motivation for all of this was clearly stated: To stare down growing competition from both American and Asian players in these crucial technology sectors. Reynaert emphasized the advantages for Member States – the leveraging of resources across Europe, better synergy in overall vision, and more cost-effective implementation of the end-results. He said, “This is a very good way to get all of the players working together.”
Questions from the floor reflected concerns about the ability of small and medium-sized companies to benefit from the programs, and concerns that universities already involved with industrial partners might lose ground. Reynaert expressed confidence the concerns could be addressed, and I left thinking perhaps I should not have been there in the first place. I’m as aware as any of the increasingly intense acrimony between Europe and the U.S. – sometimes, it’s just better to know when to remove oneself.
* Skipping lunch, I headed back to the Exhibition Hall, met briefly with Holly Stump from Jasper Design, had a nice chat with Paul McLellan from Envision Technology about the company’s new Chill clock-power reduction tool, and then sat down to enjoy a 90-minute panel in the Exhibition Theater moderated by Gary Smith: “Concurrency in a Multi-Processor World.” The conversation included Imperas’ Simon Davidmann, Tensilica’s Grant Martin, and IMEC’s Rudy Lauwereins (a possible DATE MVP for all the appearances he
made at the conference).
Davidmann confirmed: “The future is definitely multi-core.” Martin refuted Smith’s “embarrassingly parallel” terminology: “There’s nothing embarrassing’ about it. There are lots of evolutionary steps we can take to [get things going here].” Lauwereins reiterated the need for an evolutionary approach. Smith invoked Asia: “China puts out 50,000 programmers a year. In one year, they could solve the need for [concurrency through sheer manpower].” As I wandered away to meet with Agilent, I thought to myself: In the end, everything will devolve to geopolitics. Everything!
As I never found Agilent (apparently also channeling le Carré, they were hiding’ in Room M6), I stopped in at the University Booth instead and had a great chat with Steffen Moser from Ulm University. He and fellow grad students are working on a way-cool submarine/autonomous vehicle that he proudly told me was essentially designed and assembled by computer science students (with a wee bit of help from their EE professor/advisor). With 3 Altera FPGAs on board, the 5-foot vehicle’s got image processing, a kind of watery GPS set-up (through triangulation), and other cool stuff to assist in its life’s work – underwater spelunking in the Ulm
Before heading off to more sessions upstairs, I had one final amusement on the Exhibition Hall floor – an impromptu debate between Imperas and Virtutech over the real meaning of Open Source. For another day, I’ll revisit this conversation and extend the discussion of difficult semantics – proprietary, free, open, and community. It may all sound easy enough, but trust me – it ain’t!
Attending sessions 6.1 (analyzing auto architectures) and 6.5 (testing low-power devices) proved stolen time well spent, although it’s far from heaven to arrive late, leave early, and attempt to be in two places at once. Following those schizophrenic moments, I found myself back in the Press Room for a lengthy discussion with Accellera’s Dennis Brophy. As well as summarizing the array of contributions that have emerged out of this respected standards body over the last few years, Dennis noted that the Verilog standard has now been subsumed by the SystemVerilog standard and will be approved shortly by the IEEE. He said the emerging low-power UPF standard will
be approved by DAC in June, and predicted that going forward, we should look for major leadership in the standards area from the technology community in India.
Following that conversation, I made one more quick trip to the Exhibition Hall to speak with the team from Coresonic, CEO Rick Clucas and CTO Dake Liu. Coming off of their presentation at ISSCC in San Francisco in February, these two are feeling confident that their baseband processor technology is destined for an up-and-to-the-right market trajectory.
* Finally, returning to Wednesday’s Special Topic on Automotive Systems, I closed out the afternoon by attending what was undoubtedly Best of Show as far as technical sessions were concerned at DATE 08. Moderated, as well, by Alberto Sangiovanni Vincentelli, Session 7.1 on “Technologies, Methods and Tools for the Future Car” included input from Daimler’s Thomas Webber, BMW’s Harald Heinecke, dSPACE’s Herbert Hanselmann, TU Vienna’s Hermann Kopetz, and Continental Teves’ Helmut
Given the caliber and knowledge of these participants, this intensely informative and highly technical panel discussion could easily have served as an opening keynote discussion for the entire DATE 08 conference, and most definitely deserved that kind of showcasing. Instead, it was sadly misplaced at the end of the afternoon on Wednesday as attendees were spending more and more time in the Exhibit Hall and less and less time in the technical sessions.
The film crew at the back of the room told me after the panel ended at 6 PM that the video of the session would be available the very next day on the DATE website. That was 10 days ago, and I am still unable to find the link. Hopefully that will be remedied shortly. When it is available, may I suggest that all of you still reading here be sure to take 90 minutes out of your busy lives to watch this fascinating conversation. Everything from correct-by-construction design, to the applicability of standards, to the definition of an open approach’ to innovation and the pros and cons of point tools was discussed – and not superficially, but from the standpoint of key
technologists who are driving the future of the automotive industry in Europe.
It is this kind of conversation that defines and defends the existence of an event like DATE 08, or any technical conference for that matter. I congratulate Sangiovanni Vincentelli for assembling this panel, and hope there will be more like it in the coming years.
Thursday at DATE 08
* Having opted out of the DATE Conference Dinner at the World Famous Hofbrauhaus in downtown Munich on Wednesday evening (rumored to have been jam-packed), it should not have been difficult to be back at the ICM in time for the start of the Thursday sessions. I was late, nonetheless, and found myself on the U2 whooshing towards Messestadt West at 9 AM Thursday, enjoying a conversation with an EDA CEO who happened to be on my train. Based in Silicon Valley, he said he did not regret having made the trip to Munich, but acknowledged that the ROI for conferences – be it DATE, DAC, or any other conference venue – is increasingly
difficult to sort out. No real news there, but his comments added another data point to the enigma surrounding the future of technical shows in general.
To complete my visit at DATE, I had appointments on Thursday with Atrenta (The company’s growing 70% a year), ACE and Compaan (ACE has recently invested in Compaan), CoFluent (The company’s just announced the latest release of CoFluent Studio), and Teklatech (Teklatech’s debut at DATE 08 coincided with their first product release, the FloorDirector floorplanning tool).
I interspersed those meetings with additional technical sessions – first, Session 8. 5 and the single-electron device, which addressed strategies for simulating these highly problematic constructs, and then Session 8.7 and EPIC, an initiative for Ending Piracy of Integrated Circuits out of the University of Michigan. I also attended a talk in Session 9.4, where researchers from Northwestern University evaluated an FPGA implementation of a network intrusion detection system, using hardware to detect suspicious anomalies in data patterns. Along with debates about the efficacy of such a scheme, there was also discussion of the ongoing use of a difficult-to-update
1999 table of attack data that encryption researchers continue to use to test their algorithms and hardware.
After that session, I spoke with Ingrid Verbauwhede from KU Leuven, who was also in attendance. One of her students, Junfeng Fan, presented a Thursday afternoon paper on an FPGA-based cryptography scheme, as well. Professor Verbauwhede told me that even though only a few dozen people attended this morning talk at DATE about security, if presented at CHES, the paper would have drawn hundreds. (The Cryptographic Hardware and Embedded System Conference is in Washington, D.C. this year)
So, another question: What constitutes the appropriate mix of topics and presentations at DATE, or any venue for that matter?
* Following lunch, I joined hundreds of others in attending the Thursday afternoon keynote, a terrific talk given by Hermann Kopetz from TU Vienna. His talk, “Reliable Services in an Imperfect World,” was a fast-paced presentation that barely left time for him or anyone else in the room to breath, let alone take notes.
Kopetz laid out the requirements for robustness in an embedded system, listed types of perturbations that can disrupt that robustness, and said embedded systems need to be resilient and optimized. He catalogued the things that can go wrong in this Imperfect World – bugs, Heisenbugs, Borhbugs, permanent and transient bugs – and added to the FUD in the room by noting, “To put 1 billion transistors on a chip is one thing, but to put them in the right place on the chip is something else altogether.”
He talked about the evolution of memory, the end of Moore’s Law, the fact the embedded systems are becoming huge, and linked all of this somehow to distinctions between the Idea World and the Engineering World. He said, “The notion of cycle is crucial in an embedded system,” and then offered his list of what defines robustness is such a system:
1) A highly structured design
2) A monitor to detect and contain faults
3) State awareness and state recovery algorithms
4) Resilient actuators and cognitive resilience
5) The ability to reorganize or self organize in response to permanent perturbations
Above and beyond being the most thoroughly entertaining 30 minutes at DATE – and my description here captures only the half of it – Kopetz’s keynote was also the best possible excuse to return to the Exhibit Hall for a good bier und brezel. The crowd that left his talk, after offering a vigorous round of applause for the speaker, seemed both energized and mildly exhausted. They left Kopetz’s “ocean of time” and went to seek an “ocean of bier.”
Sire, geben Sie Gedankenfreiheit
* As others sought out the bier, I dashed one last time upstairs for a cappuccino with Monique. Then, it was time to navigate my own Ocean of Time and sail away wistfully from the ICM, now anchored under stormy skies. Slowly, I made my way via U-bahn and S-bahn to Munich’s world famous Glypthotek, home to a collection of perpetually haunting remnants of Greece and Rome.
There I communed with Caesar Augustus and asked him to comment on the long-term affects of DATE, DAC, EDA, and technology in general. Caesar was not terribly responsive – perhaps he was busy longing for his own bier und brezel – but as I peered into his face, it was hard not to conclude that whatever the future of conferences, design automation, or electronic technology in general, we need to continue to look to our own inner compass as an industry to decide how much we wish to control the power these technologies can unleash on the world.
What would Caesar Augustus have done with embedded systems? Who would Herkules have met on Facebook? At what point would the students of Socrates have utilized Google to find the answers to his persistent questions?
It was on a foundation of science and engineering that we emerged from the fear and superstition of the past. But where we go from here, is anybody’s guess. How we utilize the tools and infrastructure we’ve created in this Brave New World is still an unanswered question.
Thanks to Wikipedia for the photo of Caesar Augustus at the Glypthotek.
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-- Peggy Aycinena, EDACafe.com Contributing Editor.