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February 11, 2008
Does the Industry Need Another P&R System?
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


Does the industry need yet another place and route system? This is the question that Eric Thune asked himself and others before joining ATopTech as VP of Sales and Marketing. He obviously answered the question with a yes. He would undoubtedly say the industry needs not only another P&R system but a better one. I had an opportunity to discuss this with him recently.

Would you give us a brief biography?

I got my start as an electrical engineer, a design engineer for about five years. Then I moved into the sales and marketing area at Texas Instruments. I worked there for a number of years and moved on to the EDA world at Synopsys. After that I was the first sales rep at Simplex Solutions. I was also the first sales rep at a company called Synchronicity that was in the EDA space. Previously to ATopTech I spent my last three years at Apache running the west coast sales for them.

How long have you been at ATopTech?

Almost 2 years.

What attracted you to ATopTech?

I talked with several of my customers that I had a good relationship with and asked them whether the world needed another place and route solution. I was actually surprised that the answer was a resounding yes. Even with the three or four solutions already in the market customers were not able to get their jobs done without a lot of pain. They said that the really needed someone to come in and deliver something that works at 65nm and below. This was not just one customer but many, many customers that I talked to. After doing that due diligence, it was extremely attractive. Then that combined with the talent that we have here and the track record of the team, it was a no-brainer at
that point to come over here.

Would you give us some background on the company?

Some of the original people here trace their roots all the way back to Avanti, part of the original team that did the palace and route solution, Apollo, at Avanti which eventually became at Synopsys after the acquisition. We really have a mix of EDA people from across different companies. People from Cadence, people from Synopsys, people from Chips, and Verplex. We also have people from Magma. People from across the entire industry.

When was the company founded?

Four years ago in January 2004. The two founders were Dr. Don_Min Tsou who is our president, originally from Avanti and responsible for the Milkyway database for Synopsys, and Kaiwin Lee our executive officer whose background is also from Avanti and was most recently at Tera Systems. Later Ping-San Tzeng joined our company. He is a very well known router guru.

What was the market opportunity or problem to be solved that the founders saw?

What they saw generally in the market was that the EDA vendors lost focus on their place and route tools. They were off trying to create their next opportunities in things like DFM. We saw things like 90nm come along. These vendors kind of limped their way through but when the tools hit 65nm they really stumbled in a big way. The problem was that the design rules got much tougher. Signal integrity problems got much worse. These tools were architected in some case 10 years and even 15 years ago. They were never intended to solve these types of problems. What we see is that the current vendors kind of put patches on top of their tools to try to make them fix the problems we see today.
They are really not doing that successfully. The other opportunity that we saw is that we now have hardware available with multiple CPUs very inexpensively. We really wanted to build a solution that would take advantage of these CPUs that are now available at inexpensive costs.

How large a company is ATopTech today?

We are just under 40 people.

When was the product first released?

The product was released in December 2006.

You released the product in December 2006 but your most recent press announcement suggests that you did not announce the release or make a big market splash at that time.

We did not announce the product back in 2006 when we first released it. We did make our announcement in 2007. The reason for doing that is that all too many times EDA companies make product announcements before they have customers and have revenue. There is really a lot of hype behind their product announcements. What we wanted to do is to announce our product when we had customers and revenue as well as tape-out success.

How many customers did you have during that year?

We are not releasing the number but there were several customers involved. We have actually done at this point close to 10 tape-outs already. That is probably going to go up by a factor of 5 or more this year.

The company is venture funded. How much has been invested to date in ATopTech?

We have raised a total of $14 million thus far. It was a combination of our founders and venture capital including Acorn Campus, id Innovation and Hambrecht and Quist.

Can you characterize the 10 tape-outs by process node, end applications and so forth?

There were several at 90nm and several at 65nm. We have 45nm to 40nm projects already going on. In reality we are very focused on the 65nm node and below.

How much revenue is the company generating?

We are already generating multiple millions in revenue.

How many millions?

I can’t disclose that.

Why another place and route solution?

I somewhat answered the question already. Let me go into more detail. At 180nm and 130nm what the industry saw was that wire load models are not accurate enough without placement information in order to get good results. The result is that we saw placement based synthesis. We saw things like physical compiler come about. At 95nm and 65nm we are seeing that crosstalk noise can not be accurately modeled without having real routing information. So the problem is that current tools are making very gross estimates of what the crosstalk noise is or just basically putting a margin on top of the constraint to try to accommodate that. So as I mentioned earlier at 65nm we saw the current generation of tools breaking down. The reason is that there are now challenges such as handling OCV (On Chip Variation), MCMM (multi-corner multi-mode) and very complex design rules. As a result of all this we saw the runtimes for these blocks exploding. DRCs became unfixable. Another big problem is that the timing out of the place and route tools does not correlate to the signoff tools. The physical designer might think his block is done, run it through sign off and find out that they have not only thousand of timing violations but they also have thousands of DRC violations as well. Timing closure became a manual task. We saw a lot of chips slip their schedule and I mean significant
slippage. In the meantime the big EDA vendors were vigorously pushing their DFM solutions. That was not really answering the true problem designers were having.

Would you tell us about the new system?

ATopTech Aprisa is a complete netlist to GDS II design system. We do everything in terms of floor planning, placement, clock tree synthesis as well as normal routing and detailed routing. Aprisa solves today’s challenges. It solves the advanced design rules at 65nm and below. It takes advantage of sophisticated parallel processing and makes use of inexpensive multi-core CPUs for fast turn around time. We made it handle things like multi-corner, multi-mode, on chip variation. It has a very high capacity with a small footprint.

Where are a lot of tools that tap out at 3 or 4 hundred thousand instances, we are able to do blocks or chips of 2 million instances. If you saw the press release from Sharp they mentioned how they were able to do a design flat where the existing tool that they had had to do it hierarchically and they literally could not get the project done without using our tools.

Typical View of an Intermediate Timing/Optimization Result

We have native support for multi-Vdd and voltage island designs. Low power designs is a focus for us. We have significant DFM support within our tools. We do all the standard DFM type things like double visas, wire spreading, end of line, min edge and so forth. All these specialized rules for DFM we do natively inside the router. We have very extensive ECO capability. We can handle complicated ECOs without having to redo the whole design. There is Tcl support for easy scripting. Very easy to use GUI. One of the biggest comments we get back from our users is how fast it was and how easy it was to be able to adopt to their design flow and get it up and running in their design environment.
In many cases it is less than a week. With our tools you specifically tend to see better timing, much less buffering and lower leakage power than our competition and some of the current solutions in the market.

One of the core technologies built into our tools is something called interconnect centric precision optimization to face these 65nm challenges. Some of our competitors use wht we call margin-based over optimization to compensate for this. Let’s say that the clock cycles are 2 nano seconds. They may add 10%, 20% to their tool; basically putting in a margin so the tool will drive to a better results and hopefully capture these effects but not really analyze them. Because of the margin based over optimization most of the physical optimization is based on estimated parasitics. The result is that we see a lot of over sizing of the cell to prevent SI problems. We see large run ties,
much higher cell count and area, much high power consumption. Optimization runs throughout our flow. It runs during placement, clock tree synthesis, and global and detailed routing. Our optimization is based upon precise parasitics and signal integrity information. We are able to use average parasitics in the placement phase without doing this over optimization and having to size up all of our buffers. Our global and detailed routing optimization is based upon tuning up these extractions so that it is very accurate.

We have a timing engine built into this tool. It is extremely fast. We see about five minute for a million instances. We are able to read SDC natively. We do not translate SDC into an internal format. We have very good results and very good correlation with Primetime-SI or CeltIC. So what ever flavor of signoff the customer needs for timing, we can adjust our parameters to match that timing.

For multi-corner multi-mode analysis we support an unlimited number of modes and corners. We use a parallel timing analysis. We can actually distribute these scenarios to do the timing analysis and merge the results together. We can do either across multi-cores in a single machine or we can actually take advantage of a farm of machines and do it across multiple machines.

We have a number of benchmarks comparing our TAT to the competition. They range from 8 to 10 hours versus 3 days to 60 hours versus 13 days.

What types of applications were these?

Ethernet, custom core CPU, graphics block, consumer electronics, video blocks, MIPS core and a network switch.

Let me highlight some of the key differences between what we do and what other people do. Our global route engine includes track assignment. What that means is that we actually have real wires but they are not connected at the very end to the cell. This is how we get a much more accurate way of getting the parasitics than a competitor using estimation. Basically a very fast algorithm. We have a design with 2.8 million instances and global route runs in about 30 minutes. What we are trying to do is trying to fix signal integrity problems early in the cycle. If you kind of wait to fix SI at the very end, then it is too late and you can not fix it. We automatically iterate between routing
and optimization. We do things like sizing, buffering, wire spreading; all for looking at timing, signal integrity and power analysis. We can incrementally route to relieve congestion. We can also rip up, re-route and reassign tracks based upon timing and SI information. All of this is done while encompassing multi-mode, multi-corner analysis. Again the key is the earlier you try to fix these SI problems the better design closure you will have.

The detailed router is a hybrid router. It is a grid based router but it can generate off grid routes when needed. It is very fast. It can route 250K instances in about 5 minutes using 8 CPUs. It is multithreaded but it is virtually linear with the number of CPUs. For 8 CPUs we have seen anywhere from 7 to 7.5 x speedup. With our competitors, you see a benefit after 2 CPUs but that is about it. We also see that when our competitors use multiple CPUs, their quality of results tends to degrade. Our QoR does not degrade at all. As a matter of fact you will see the same QoR whether we use 2 or 8 CPUs. We support all the special routing rules, wide width/spacing, shielding, via doubling.
Then in the detailed routing we automatically iterate routing and optimization. There is excellent correlation between our extraction engine with StarRC and CeltIC.

Can you identify any of your customers?

On December 10 we announced that we have entered into a multi-million dollar per

year, multi-year contract with Broadcom Corporation. I think this is very significant for a startup. It is rare that you se a startup with such a large deal with such a large corporation so early in its history. The quote from Neil Kim, Senior VP, basically says that ATopTech offers a high quality solution to our 65nm closure effort.

The bottom line is that Aprisa was written from scratch to solve today’s generation of design issues. We have this interconnect centric precision optimization that does a better job of timing closure at 65nm and below and that has true correlation with signoff tools as well as DRC tools. We are taking advantage of sophisticated parallel computing.

Our team is a very strong mix of place and route experts. If you look at many of the members of our team, you see that this is their third commercial place and route system that they have built. They know all about the challenges and the mistakes that have been made.

We are more about under-hyping our product and over delivering than creating a lot of hype about it and then not being able to deliver on that proposition. We are tape-out proven.

What is the competition that you keep referring to?

It is the gamut of tools from all the big vendors.
Editor: In June 2007 Mentor Graphics acquired Sierra Design Automation for $90 million. Sierra has an RTL-to-GDSII IC implemention tools including Olympus-SOC place and route system.

What is the price and packaging for Aprisa?

The list price is $795K for a one year TBL.

Does it matter whether the customer is running it on 2 or 8 computers?

There are different pricing models depending upon the number of CPUs.

Is that a decision the customer makes at the time of their initial purchase?

The customer can always upgrade the license to enable more CPUs.

Could the customer go up and down as their need varies during the development cycle?

What we see with our customers is that they always want more not less.

Is the TBL shareable or node locked?

It is a standard LAN license. There is an option for a world wide (WAN) if that is what the customer wants. This is a single location floating license.

What is the sweet spot for Aprisa? What type of end applications would best benefit from using Aprisa?

We are seeing a broad base of applications. We have a customer that is doing very high speed CPU design. One is doing Ethernet design. Another is doing graphics design. One is doing consumer electronics and one still another is doing networking design. This is really a broadly applicable tool for different areas of design today.

How is the product sold? Direct sales? Distributors?

Direct sales.

World wide?


I did see ATopTech KK in Japan listed on the website.

Is ATopTech partnered with anybody?

We have a partnership with Mentor Graphics in their Connection program. And a partnership with Synopsys in their TAP-in and MAP-in programs.

How does Aprisa relate or fit in with Mentor Graphics or Synopsys?

Both of these companies have competitive products.

If you have a partnership, there must be some complementary aspects of the products.

In a lot of cases we have mutual customers who want that to happen.

How does Aprisa fit into existing customer design flows when you are trying to replace such a large and critical part of that flow?

We use standard industry formats like DEF.

You are the head of marketing and sales. What is you major challenge? What is the biggest obstacle to Aprisa’s future success?

That is a good question. Our challenge is really to execute. We have a lot of feedback from our customers about things they would like. The feedback from our customers is that our R&D has done a phenomenal job on customer request. They turn those around quickly. With some of the big guys, they do not see a release for six months. Our customers are asking for things and seeing them in days or weeks.

So ATopTech’s major advantage is basically a technology that enables users to more accurately model parasitics and more rapidly generate the results.

From a higher level what we are enabling people to do is to get their design done better and much faster. I know that this is a pretty broad stroke but that is truly the challenge people are facing; blocks that they were able to do in one or two days at 130nm or 180nm are taking in some cases three, four or five weeks to do at 65nm. We are able to bring those times back down to what they were able to do at the older technologies.

Are there any plans for additional capabilities this year?

We have a roadmap which we are not disclosing publicly. We have a lot of functionality planned that our customers are very excited about. We will bring better turnaround time, better results, and more features. We will certainly deliver a lot of new things in the future. Our architecture is in its infancy and it is still faster than anything out there. A lot of other architectures out there are reaching their end of life.

When you try to persuade prospects to buy Aprisa, how do you convince them that your product does what you claim it does?

It is really not a matter of convincing. They bring us in and say if you can show us that you can do a better job than our current set of tools, then we will go with you. In most cases they give us the most challenging block they have ever done, the block that gives everybody fits. Then we turn that around and show them the results. I would say that in most cases the customer is shocked at what we are able to do.

When they give you this most challenging block, how long does it take for you to turn it around?

It is very block dependent. In every one of those market segments, it depends on whether the block was difficult to rout, whether it was a block that was hard to close timing or a combination of the two. It depends on the size of the block. So many different factors, I could not begin to give you a number.

Would the every difficult to identify typical case be measured in days, weeks or months?


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    -- Jack Horgan, EDACafe.com Contributing Editor.