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December 17, 2007
Apache Design Plus Optimal Equals?
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor


by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!



Introduction



At the end of October Apache Design Solutions announced that it has signed a definitive agreement to acquire Optimal Corporation, a provider of 3D power, signal, and thermal analysis for package, System-in-Package (SiP), and board designs for an undisclosed amount of cash. Optimal’s product line includes package and PCB extraction and analysis solution for power, signal, and thermal integrity compliments Apache’s newly introduced Sentinel product line targeted at system power and I/O signal integrity.

I had an opportunity to discuss this with Apache CEO Andrew Yang.


Hello

You’re in the Los Angeles area.


Yes, north and west of Los Angeles.

805 area code. That used to be place where I went to high school. I went to Ventura High School.


I’m in Thousand Oaks.

That’s 15 miles east of Ventura.


Right! Perhaps we could begin with a brief biography after high school.

I went to college at Berkley and then worked as a designer at AMD for two years. After that I went to graduate school at the University of Illinois at Urbana-Champaign. I got my Ph. D. there and then went to teach at the University of Washington at Seattle for about seven years. Along the way I founded a company called Anagram which provided high capacity simulation, Fast Spice, to compete with Epic. The company was acquired by Avante in 1996. I stayed on for about two years and managed the analysis product division as VP of all products related to extraction, simulation (HSPICE, StarRC, SPICE, FastSpice), library characterization and so forth. Then I became a private investor
involved in several leading investments in EDA such as CADMOS which was acquired by Cadence. I also invested in Ultima which merged with VCH to form Celestry which was acquired by Cadence and in Innologic which was acquired by Synopsys. Then I invested in Mojave that was acquired by Magma. I founded Apache in 2001 with two other founders focusing on power. I have been CEO and Chairman for six and one half years.


What caused you to leave the world of investment community where you had considerable success and get back into running the day-to-day operations of a startup company?

I got bored. I was less than forty years old. The challenge is to take the company to a bigger scale. I did see the vision that power was emerging to be a very important area. This was back in 2001. As we talk today power is indeed the leading market criticality for the semiconductor industry. That vision was also part of the reason I wanted to be hands on with the company form the beginning. Today we have over 140 employees and operations in nine or ten different countries with R&D centers in five locations. So it really became interesting and exciting career move for me. At this point the next step is whether I can challenge my career in moving to an even bigger scale,
providing not just a point tool but a platform solution for the semiconductor industry.


Did you have and the vision and then went out to recruit a team to form Apache or did you find some people with a vision and/or some technology and decide to bankroll them?

There were three of us. The other two were form HP. We brainstormed which areas would have a critical impact on the industry. We isolated the vision to this power area. There was no solution at that point addressing the so called full chip dynamic power or leakage power. We had to build not just the founding team but also the first tier engineering team with expertise encompassing a wide range of domains including extraction, power calculation, signal integrity and so on. That took about a year and a half to two years to build the team. Then the first prototype product was released in 2003. It became the first industry product to address full chip dynamic power solution. That was
exciting because we are building something from scratch, creating a new market not just a me-too trying to do something better than existing solutions. To me that is the most gratifying experience. My career is always to work on something new. I have two or three years ahead of what other people think is important and what they think is possible. Get the market validation and get the business to scale up to confirm the vision. That indeed is what happened here at Apache. This always follows our vision and scales linearly with uninterrupted growth.


Did you bankroll Apache or did you get others to invest?

That’s a good question. Apache follows my previous strategy of so called capital efficiency. If you look at my past record, I have always believed that in the EDA space capital efficiency is critical. That is how we drive the team together and work under a focused effort and target with pin point accuracy a specific area. The company Apache was funded with a very small amount of capital. I am the lead investor. We have had two rounds, a Series A and a Series B. The other investors include Intel Capital and Andy Bechtolsheim who was one of the early investors along with me in another company (CadMOS) we help found. These are the main investors.


What was the approach to addressing dynamic power and leakage power?

At that point back in 2001 the only solution in the market was based on static solution which is a DC based solution. This was mainly because of the complexity of dull chip and also the accuracy required is so high for dynamic. The existing methodology at that time was to simplify the problem by looking only at the DC aspect of dynamic power. Clearly because of the simplification and approximation a huge amount of inadequacy was introduced, mainly the modeling of inductance and capacitance and off-chip package parasitics was missing in the static analysis. The underlying technology behind our first core product called Red Hat was based upon an innovative approach, a three step approach. The first step is to pre-characterize standard cells, IOs, IP and analog memory. And to bring transistor level modeling accuracy into the flow at the abstract level. Then in the second stage we extract the power delivery network in terms of resistance, capacitance and inductance. Then bringing the modeling accuracy of the cells, memory, and IOs to create a network that we can solve in the time domain with transient analysis engine. This transient analysis engine is clearly different from the static solution in the market. At the time because the static solution only solves the network in a single shot, at one DC operating point. The transient analysis solves the entire time domain waveform creating more accuracy and more data for the customer to analyze the true behavior of the dynamic power. The first step is to taking the analog waveform and then analyze its impact on timing such as full chip timing and frequency operation as well as critical areas such as jitter. This three step approach we believe is innovative allowing us to retain accuracy at the transistor level but also expand the capacity to handle full chip with a chip as large as a graphic chip or a CPU chip. And also the ability to look at timing and feed it back into the designers flow. That was the first full product innovation in this area. The leakage solution came along because as processes migrated to 65 nm
and 45 nm, leakage power starts to play a critical role. That is because leakage power becomes a bigger contributor to total power. To manage the leakage there are many interesting design techniques including power switches, NTMOS techniques. Basically it is just shutting down and turning on the power supply. By definition, if you are shutting down or ramping up or turning off, it is a dynamic problem. Our dynamic engine naturally becomes the enabling solution to handle such an important problem. Today for 65 nm and going to 45 nm we believe more and more designs will employ these kinds of dynamic solutions, i.e. turn-on, turn-off type of design techniques.


What does the Apache product portfolio consist of?

We entered the market with this full chip dynamic power integrity solution called RedHawk. We extended that to low power, low leakage management solution called RedHawk-LP. Then we also have the follow-on fix and optimize solution to resolve any noise induced timing issues called FAO for fix and optimize. That is our SoC solution portfolio. Then there are one or two product areas that we introduce to the market every year. This includes Sahara which we introduced two years ago. This is an on-chip thermal solution with the vision that on-chip temperature variation will start to play an important role in impacting the performance and the power characteristics of the design. This
year is also an important year for Apache. We announced our new focus in the area of packaging with a new product called Sentinel with a vision that power and noise requirements will no longer be contained in just the IC but will be a system wide challenge. Our vision is to expand our on-chip solution into the package and board with this new product family. That leads us to the recent activity of acquiring Optimal which specializes in packaging and board extraction and analysis.



                                                                          Apache Design Offerings


The intent to acquire Optimal was announced at the end of October. Has the transaction been completed?

Yes! As of last week the transaction has been completed.

Tell us about Optimal. What was it mission?


Optimal is exclusively focused on package and PCB board extraction as well as power, signal and thermal integrity. It is a strong partner with Cadence in the SIP and PCB flow. They have over 60 active customers. We have been working closely with Optimal for over a year to integrate our on-chip solution with their off-chip package solution so that we can provide the customer with a seamless flow. The relationship continues with the merger/acquisition. There is virtually no overlap. The product synergy also fits with our vision of Sentinel focusing on chip packaging design. We also believe that there is strong customer synergy because there are many major accounts customers that are using
both Apache and Optimal products. This was we can help customers resolve the vendor communications issues. We believe that this is a clear win for our mutual customers. Most importantly we now have tow pieces of important technology, on-chip and off-chip. We believe that we will be able to carry out a tighter integration, not just a so called handshaking type of integration but even at the more detailed level of algorithmic integration. I believe that this will be the trend in the industry in light of upcoming SIP, system in package, multichip package drives.


                                                                        Optimal Product Offerings


The technology and products are complementary. How do you achieve more than a handshake type of integration? What is being integrated?

Basically, if you look at the on-chip problems being solved, it is solving a non-linear electrical problem whereas with off-chip Optimal is solving electromagnetic problems using finite difference and finite element approach. At the end of the process the solution has to involve simulation or matrix inversion solver. The innovation that will have to come is that the simulation and extraction will be fully integrated. Customers will see a clean cut system results between the two domains without going through model creation, handshaking and the mapping of physical geometry design information. At the GUI level there will be full integration. The customer will eventually be able to
visualize the design comprehensively not just from the IC or separately from the package board. They will be able to see the entire physical implementation across different domains. That is our long term vision and road map. In the mean time Apache will continue to invest in the development of the standalone Optimal product to make it more competitive in terms of accuracy, capacity and leveraging some of the important IP developments here at Apache to be deployed in the Optimal solution and vice versa. First of all to strengthen the comparative position of each stand alone tool not just focusing on integration. We will continue all products standalone in each domain.


Did Optimal have any relationship with other EDA companies? Will Apache continue to support these relationships?

Yes. I mentioned earlier that Optimal has a strong relationship with a foundry. That relationship will only get better. I believe that the foundry relationships especially TSMC will be critical for solving the next generation system problems. Optimal also has a strong relationship with Cadence SIP and PCB implementation flows. Apache is definitely interested in continuing to support that relationship.


How big a company is Optimal?

Optimal has about 30 employees.


Earlier you said that Apache has around 140 employees. Does that figure include the 30 people at Optimal??

That number includes the Optimal personnel.


How close are the two companies in terms of location?

Apache just moved to a new place as of last week. Optimal came along with us. SO the day after the merger, the teams were physically integrated in the same building.

Apache has just announced 18 quarters of increasing revenue.


Yes. We just completed the 19th consecutive record quarter and also profitability has continued since 2005. That is quite an accomplishment, especially for a small EDA company. That is a strong endorsement and the result of this market criticality we are addressing. Also there is the customers’ strong desire to invest in this important area.


What was the revenue I the last record breaking quarter?

As a private company we do not disclose the actual revenue or even the booking numbers.


I noticed that you were on a panel at DAC discussing IPOs and exit strategies for startups. You have been in companies that have been acquired. You have invested in companies that have been acquired. What is the exit strategy for Apache?

I believe that the exit strategy is ultimately an outcome of the business and technology execution of any company and should not be forced upon and should not be preplanned. At Apache we execute according to that principle. We first build the technology as the number one priority, second we build the business to follow it and third we ramp up the business from a single product to a platform based business and build value through innovation and solutions provided to customers. At the panel where I participated during DAC I strongly advocated a so called dual track strategy. At a startup company should not be a preclusion of any activity that will help the company to grow. In my mind when you get acquired, it is motivated by because you want to have access to a bigger channel or integrated flow. If you go public, the objective is clearly the same, which is you will have a strong business proposition with capital infusion to build an even bigger channel and more resources to work on new products. So for both routes the incentive should be the same. It should not be precluded. No IPO has happened since 2001 for a variety of reasons. Many of the companies did not grow to a critical mass or the business model has shifted from perpetual license to time based licenses which takes a slightly longer period of time to build up the revenue required. Also because the IPO bar
is higher. At the end of the day I believe that this is all very good because that means that any company that is able to go out as an IPO will be much stronger than previously possible which means you have stronger traction, better revenue visibility, more product diversification and more customer diversification. I think it is helpful for the industry not to rule out any IPO. In fact I think that would create more excitement more viability for the EDA ecosystem.


What happens to the management team at Optimal?

All the management stays. The CEO of Optimal Dave De Maria stays on board as our senior VP driving the chip package co-design package. The founder and CTO (An-Yu Kuo) also stays. We continue to work with Optimal R&D to drive the integration and also the standalone product roadmap. The VP of Engineering will also stay as the architect to continue the product development.


Who do you see historically as Apache’s main competition? Does the Optimal acquisition make you more competitive against them or are you facing new competitors?

In my view we always assume that everyone eventually will compete with us. It is critical that Apache stays two years ahead of the competition in our core area. That is why we have been working on our next generation solution which we have not yet announced. It is my philosophy of execution and my past history to always work with a parallel team on the next generation engine. We will not stand still and be driven to develop the second generation by our competition. We have been working on the next generation in our core area. At the same time we understand the importance of expanding our core competency in single product to adjacent space and formulate a platform based solution that
addresses a wider range of applications for our customers. In saying that the acquisition of Optimal clearly plays to that role. That is we now offer more solution to our common customers and as a result the customer will feel that it is much moiré important and easier to do business with Apache. This will definitely help Apache’s strength as a standalone and long term business proposition.


While many firms could possibly compete wit Apache, which ones do you see today as competitors?

Today, we compete will all the big vendors just like any other EDA solution provider. We compete with every one and we continue to execute. We have not lost any technical benchmarks in a long period of time. Out major customers continue to invest in Apcahe getting more license that are require for their next generation of design. That drives our consecutive record quarters. Our business is a strong indication of our competitive position in the market today. I believe that is the biggest endorsement.


What is the list price of the some of the various products?

We won’t give out that information for public access.


Would you like to expand on the capabilities of the second generation product under development?

No. We will spend more time in the near future to give more information about the second generation, its approaches and benefits but not on this call.


The top articles over the last two weeks as determined by the number of readers were:


Open SystemC Initiative Advances IP Interoperability and Reuse with New Draft Standard for Transaction-Level Modeling. The Open SystemC Initiative (OSCI), an independent non-profit organization dedicated to supporting and advancing SystemC as an industry standard language for ESL design, today announced the milestone release of the new transaction-level modeling standard, TLM-2 draft 2. This standard enables model interoperability and reuse at the transaction level, providing an essential framework for
ESL design. The public review period is now open to the worldwide SystemC community and ends on January 31, 2008. SystemC users, ESL tool developers and IP providers are encouraged to participate and provide feedback. The TLM-2 draft 2 kit is made available under open source license and includes a requirements specification, documentation, library and examples. To download, visit
www.systemc.org.  


Real Intent, Inc. announced that it is shipping a new version of its Ascent™ software for automatic formal verification of electronic designs. Ascent finds bugs in Register-Transfer-Level (RTL) designs and improves design quality, with significantly higher performance when compared to Real Intent's previous generation of automatic verification software, Implied Intent Verification. Ascent is shipping now, was first introduced in 2006, and replaces Real Intent's Implied Intent Verification software. The price starts at $35,000 for a one year term license. Existing customers on active maintenance receive Ascent at no charge.


Verigy Signs Agreement to Acquire Inovys announced that they have signed a definitive agreement for Verigy to acquire Inovys. Inovys, privately held, provides innovative solutions for design debug, failure analysis and yield acceleration for complex semiconductor devices and processes. Financial details were not disclosed. The acquisition is expected to be final in 30 to 60 days, subject to certain closing conditions.


ATopTech Signs Multi-year, Multi-million Dollar Contract with Broadcom ATopTech, Inc. announced that it has entered into a multi-million dollar per year, multi-year contract with Broadcom Corporation, a global leader in wired and wireless broadband communications semiconductors. Broadcom will use ATopTech's next generation place and route software for designing integrated circuits at 65nm and below. Broadcom's first chip using ATopTech's software has already taped-out and had first pass silicon
success. On the same day ATopTech launched the company and unveiled a new product with new technology for the physical design of ICs at 90 nanometers and below. The company formed in late 2003 and development on the EDA software was begun in 2004. The company has raised $14 million in two rounds of funding. Investors include the founding team, Acorn Campus Fund II, VCEDA, iD Innovation, Inc., and H&Q.


Other EDA News

SiPort Selects Berkeley Design Automation Analog FastSPICE(TM) for Mobile Digital Multimedia Broadcast Receivers

Mentor Graphics Precision Synthesis Combined With Xilinx SmartGuide Technology Dramatically Reduces Design Time

UMC Releases 65nm DFM Design Enablement Kit

ATopTech Signs Multi-year, Multi-million Dollar Contract with Broadcom

Pioneers in Breakthrough IC Design Tools Launch New Company, Announce Proven Physical Design Product

Tensilica Enhances Xtensa Configurable Processor Families With New Options, Bridges and Software Tools

Virage Logic Partners with MTEK I&C to Bring Its Advanced Silicon Aware Intellectual Property (IP) to the Korean Design Community

Virage Logic and Marketech International Corporation (MIC) Partner to Provide Silicon Aware Intellectual Property (IP) to Rapidly Growing China, Singapore, and Taiwan Markets

OneSpin Solutions Delivers First Equivalence Checker Dedicated to FPGA Synthesis Verification

Mentor Graphics Announces Industry's First Multi-mode Multi-corner Signal Integrity Solution for 65/45nm


Other IP & SoC News

ON Semiconductor Releases New PureEdge(TM) High-Performance Clock Generation Devices for Telecom, Networking and Consumer Applications

Wind River Enhances On-Chip Debugging Solutions to Address Growing Complexities in Mobile and Handheld Device Development

Seoul Semiconductor Introduces the World's Thinnest High-Brightness Chip-LED at 0.17mm

Fresco Microchip Delivers High Performance, Low Power Single-Chip Hybrid Receiver for Terrestrial and Cable Television

UMC Releases 65nm DFM Design Enablement Kit

OKI Increases its Lineup of Power Management LSIs for Mobile Devices

Diodes, Inc. Releases New Dual 100V SBR(R) Rectifiers with Industry Leading Performance

Cypress Peripheral Controller Delivers Fastest Mobile Handset Download Times in Recent Comparison by Industry Analyst

Violin Memory and AMD Collaborate on Terabyte-Scale Server Memory

IBM Alliances Deliver Easier Path to Next Generation Semiconductor Products

AMCC Introduces Low-Cost Evaluation Kits for PowerPC 405EX and 405EXr Processors

Tessera Files New ITC and District Court Complaints Aimed at Infringing DRAM Devices

PMC-Sierra Announces Quad 8Gbit/s Fibre Channel Controller for High-Performance Storage Systems

IDT Introduces 6-, 8-, and 10-Channel Low Power, High Definition Audio Codecs

TI’s New Microcontroller Families Offer Twice the Performance and Battery Life, Enabling Ultra-Low Power Applications



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-- Jack Horgan, EDACafe.com Contributing Editor.


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