November 19, 2007
Can One of the Big Three Compete in a Market Dominated by Others?
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| by Jack Horgan - Contributing Editor
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In my last editorial I discussed the case of how a firm (Ciranova) could make money, if it gave away its own product. This time the issue is how does one compete with a significant player who is offering if not free, very inexpensive tools? Xilinx and Altera dominate the FPGA marketplace. In fiscal 2006 they had revenue of $1.84 and $1.3 billion respectively. Both firms offer tools for designing and developing with their FPGAs. Mentor Graphics believes it can compete by offering vendor independent physical synthesis with advanced capabilities like automatic incremental physical synthesis and resource management. Mentor has recently introduced a new offering called Precision RTL Plus
with these capabilities. I had an opportunity to discuss this situation with Daniel Platzer, Product Line Director for Synthesis Products
Would you give us a brief biography?
I started my career at Daisy. I started as a hardware engineer. I think I was one of the very first ones who actually used CAE tools for the purpose of designing hardware. At that point it was PMX, some accelerators and stuff like that. Then I moved within Daisy to technical marketing and product management around PLDs and behavioral languages. Daisy had a proprietary language called Able and we had a product called PLD Master. My career back then was around the original EDA tool for programmable devices. I did some kind of major detour to networking companies and to e-learning. I actually started my own business and was CEO for 7 years in a pioneering e-learning company (Tegrity). A
little over two years ago I went back to my childhood so to speak and joined Mentor and here I am.
What are some of the trends in the FPGA arena that Mentor is seeking to exploit?
There are some obvious industry trends. The first one is of course increased design complexity as the silicon becomes more capable in terms of functionality, speed, area and so forth. The consequences of being more complex is it runs the risk of delays and being over budget. Coming from the EDA industry we are convinced that EDA tools are the best friend of the designers and their management to make sure projects are on time. The complexity means that we really do not want to cut corners when it comes to selecting tools. The second trend is that there are more advanced EDA tools. It is quite open now that companies find themselves designing with chips from Xilinx, Altera, Lattice, Actel
and so forth. The reason is very simple. Altera might be the best tool for you today but maybe tomorrow or for another project you find out that Xilinx is 30% cheaper or better. As a designer or management you need to retain the flexibility to move from one silicon to another, from one vendor to another. It is becoming more and more apparent that a good way to ensure that an engineer can actually do that is that you need vendor impendent tools. The designer community and the management are less and less thinking of using vendor specific tools because these vendor tools are not about the flexibility to move from silicon to silicon. The third trend is there is more ASIC prototyping. More
than 50% of complex ASICs are being prototyped. Prototyping is all about taking the ASIC and trying to prove the design in FPGA platform. The truth of the matter is that there are not too many tools that are designed from the ground up to support the needs of ASIC prototyping. For example, these vendor tools do not necessarily do gated clock conversion, designware support and so forth. So if you are in the business of ASIC prototyping, you want to make sure the FPGA synthesis support the ASIC prototyping flow. The last trend in the last 5, maybe even the last 10 years, is that big companies realize that selecting the best tool in class without paying attention to whom you buy from will end
up with the situation where you have too many vendors which means less buying leverage, multiple points of support and interoperability issues. Therefore, big companies are trying to reduce the number of their EDA vendors.
Today, are FPGAs used mostly as a component in the final solution or as a prototyping tool for ASICs? Is it 50/50 or something else?
Most of the design starts are end products. It’s not 50/50. I would say as a guess that 30% are in ASIC prototyping. But no one really knows the numbers. But it is significant either way.
How does Mentor fit into the picture?
Mentor is clearly the EDA leader in servicing the FPGA design community because of one simple fact. In order to have an FPGA solution you need to have four basic components. These are design entry, simulation, FPGA synthesis and PCB tools. There is no other EDA company in the world that has these four basic components. Without these four components, you do not have a complete solution. Therefore Mentor is clearly the leader. That is not to say that we don’t have lots of other tools for hardware/software integration, high level synthesis and so forth.
There are over 1,000 companies using Mentor’s FPGA synthesis products. The reason we are seeing an increased business is that more companies are realizing that vendor independent synthesis is important. They realize this especially after they have to undergo a painful switch from one vendor to another. If you look at overall vendor independent synthesis, it is Mentor and Synplicity. Roughly judging by the size of the install base and the number of users is approximately the same.
Synplicity is a company with annual revenue in the $60 million to $70 million range. Is Mentor’s FPGA revenue about the same?
No. We have less revenue. The reason is very simple. When Mentor is selling FPGA synthesis, it is almost always as part of a basket of tools and therefore the business terms are much more favorable for the customer. The customer ends up paying much less for Mentor FPGA synthesis as opposed to the solutions from Synplicity. So while the number of seats is the roughly the same, Synplicity is generating higher revenue because it costs the customer more money per seat.
What are the issues that need to be addressed?
Every state of the art FPGA synthesis needs to address three stages. The first stage is to start right by supporting industry standards for the input of HDL and constraint filers. If the tools do not support standards, it will be very difficult to actually take and reuse designs successfully. The second one is the engine itself. Synthesis today needs to deploy the latest and greatest in optimization. The third one which is hardly the case today is to be able to push a button and meet aggressive design goals. You end up having in many cases especially in large and complex designs that you are not quite there and you have to start engaging in analysis and debug. Today FPGA
synthesis needs to be very strong in the analysis and debug process
The first thing that comes to mind is language support. We are convinced that we (Mentor) are the leader in FPGA synthesis language support. For example, if you look at System Verilog it has increasing popularity not only for verification but also for design. When it comes to supporting synthesizable subset of System Verilog Precision is by far the leader. No one else actually comes close. Whenever, we do market education and seminars, the System Verilog to synthesis is always over booked.
Of course it is also important to support standard constraints because a design is not just HDL, it is also the constraint file. Also important today is the fact that HDL is not only hand coded but also generated by high level synthesis and some other tools. It is important that synthesis supports the flow generated by neighboring tools. Being Mentor we have more neighboring tools around synthesis than anyone else.
State of the art synthesis needs to support technology independent inferencing. All kinds of gated clocks are extremely important for ASIC prototyping. ASIC prototyping is all about taking the design from the designers and very quickly synthesize it into FPGAs. In the ASIC arena there are a lot of gated clocks and sometimes Designware. If you do not have a gated clock conversion, your tool will not be successful in achieving reasonable performance.
The last one is that when you pushed the button and got close but not quite there, the tool needs to show you where the critical paths are. And it needs to show you in different ways including graphical views so you can actually track and see the reason, you can cross probe from timing reports to the source so you can understand which line in the source is actually the offending line that created the critical path. There is the missing constraint report, the domain crossing report. All of those interact. You do not have to re-synthesize them from the beginning. All of that capability is important for the designer to be able to identify the problems so that he/she can fix them. In an
objective customer satisfaction survey done by the FPGA Journal, Precision was voted the one with the highest satisfaction for analysis by a synthesis tool
As proud as we are in the progress we have had in synthesis, more than 1,000 companies using us is a vote of confidence, the work is not done yet. There is a lot of development that needs to be done to catch up with advancements in the silicon. When we asked our customers we found three major challenges that typical FPGA designers are facing. The first one is in order to get timing closure there are too many iterations. The second challenge is that each iteration takes a very long time. It sometimes takes a day for just one iteration. The third challenge is how to make sure that the resources inside the silicon are utilized to the maximum because inside advanced FPGAs today there are
hard macros, all kinds of special purpose blocks. These are the three challenges that our customers told us need to be addressed.
How does your new product address these issues?
We have introduced a new product called Precision RTL Plus. The official announcement was September 24th. The product is shipping. This is a vendor independent solution for break through productivity. If you want to achieve your timing faster and predictably, it is about how to make you more productive. It has three breakthrough capabilities. It is easy to use for every designer and equally powerful for the vendor FPGAs. They are breakthroughs because none of them are me too. Each one of them has uniqueness and has measurable value to the end user. The first problem was there were too many iterations. For that we are introducing unique physical synthesis in order to minimize and shorten
the iterations. In order to reduce the length of the iterations, we have introduced the first technology for automatic incremental physical synthesis. In order to solve the efficient challenge of the architectural blocks we have introduced patent pending resource management equality.
We call the first breakthrough physically aware synthesis but it is really physical synthesis. It is the only multi-vendor physical synthesis. Let me break that down for you. Physical synthesis is now a reality and it must have features for all synthesis today. The reason is that much of the delay typically is no longer the cell but the routing length and the net delay. In order to solve the net delays, you need to have physical synthesis capability in your tool.
If you want a tool that is vendor independent, clearly the important capability of physical synthesis needs to support all the vendors because it is that central, that important. If the physical synthesis supports only one vendor, you will not be able to use the capability when you want to switch to another vendor. As obvious as this is, this is the only product that is true multi-vendor synthesis. Therefore we can confidently claim that Mentor is now the leading vendor independent tool. From another perspective it means 10% improvement in Fmax with a typical improvement of 5% to 45%.
What is the benefit of this Fmax improvement to the end user?
There are two major challenges. The first is timing and second is area. A third one we are now seeing is power. For many complex designs the requirement to achieve a certain clock speed is the number one challenge in design constraint. If you have a push-button like you have with this capability that can achieve an additional speed up of the clock by 10%, it can sometimes be the difference of meeting you design goals or not. Sometimes it can mean being able to change to a cheaper or less expensive device.
The average we and our customer have been observing with objective test runs is typically between 5% and 40% improvement.
What is innovative about this? Everyone understands that in order to have vendor independence, the physical synthesis needs to support all vendors. But up to now, no one could achieve that because whenever you have physical synthesis, it has to know the intimate details of the physical characteristics of the silicon. Therefore every additional vendor or every additional device was a major, major project. The innovation here is that we are now introducing a technology where it is easy to add new devices and vendors. Therefore, we are currently the only one. Just for comparison the only other physical synthesis tool which is available on the market supports only one of the vendors.
Synplicity has physical synthesis, Premier, for a year and a half but it still supports new devices only within Xilinx. We are support the four major vendors, 19 devices families.
What percent of the total number of FPGA devices does this represent?
When it comes to complex designs and the most common designs, I would estimate it would be 70% to 80%. There are hundreds of devices but when you look at complex designs and where designs are being focused these days, these 19 families are really covering the majority of designs,
When Xilinx, Altera,
introduces a new FPGA does Mentor have to come out with new models, update the software,
? How does that work?
We are very good partners with all of the vendors. When the vendor is in the initial stages of developing a new part, they disclose to us the details so when they are developing and readying the silicon, we are readying the software even before the silicon is available, long before. When the product is announced we are ready to support it. For every device that is being added, the synthesis tool needs to do something about it.
With physical synthesis we are reducing the number of iterations because you can get to your Fmax goals and time closure faster but you still need to iterate. Because most designs today are complex and challenging, iterations which include synthesis and place and route can take 8 hours, 10 hours. It is not unheard of to run over night. Therefore as you come closer to the end of the design and there is a change request or I need to change an inverter, then going through these 8 hours is very painful. For the first time Precision RTL Plus includes automatic incremental synthesis. This product also supports the traditional partition based approach. We are not just inventing a new way we
are supporting the previous way to handle incremental design.
Up to now if I made a small change and I did not want to wait for synthesis and P&R then to shorten the time the designer had to partition the design. This approach could be effective for team based design but in the vast majority of designs this turned out to be too complex. Therefore the designer community did not do that. For the first time we came up automatic meaning that the designer does not need to do anything in order to benefit from the shortening of the run time. There is up to 60% synthesis runtime saving. The nice thing about this is number one you do not have to do anything. You run it the first time to establish the base line. The next time you run assuming the change
is relatively small, the synthesis will be smart enough to synthesize only the difference. Not only did the designer not have to do anything to benefit from the time saving, you are not compromising any quality of results. In the previous means of partition based not only was it complex and therefore most people do not do that but if you did partition it, many times you would end up with shortened run time but your Fmax or area would suffer. You would compromise the quality of results. The first automatic incremental synthesis does not require any partitioning or any preparation. You do not lose any QoR. Just like the physical synthesis where we support a broad range of devices and
vendors, all of the FPGA devices we support are enjoying automatic incremental synthesis.
When you combine the unique automatic incremental synthesis with Xilinx SmartDrive for the first time you have a complete incremental flow because synthesis is only one part, the other part is place and route. If you combine incremental P&R with Xilinx SmartDrive then for the first time you do not have to do anything especially in the late design stages you have an extensive shortening of the iteration.
For example if synthesis and P&R takes 10 hours, with this flow if you had a reasonably small change it would take one or two hours. This is a big difference. For the first time you have a complete incremental flow.
In these days it is quite commonplace to do partitioning. When you do that you are saving both in synthesis run time and the P&R runtime. Of course you have to make the effort of partitioning and need tool support as well. We have innovation here because sometimes the partition can be very big. If you do a small change within a big partition, all the others would re-synthesize the whole partition. Thanks to our incremental capability we will synthesize only the subset of the partition that is needed. We believe that up to now we are the only one with physical synthesis that support multi-vendor and the only one with automatic incremental synthesis which is also vendor independent.
Partition-based incremental synthesis takes traditional block-based iterations one step further by localizing design changes within a partition.
Vendors are spending a lot of time deciding what kind of DSP, what kind of memory, what kind of resources to put inside silicon and hard macros. Designers told us that no matter how sophisticated the synthesis tool is, they would like to have control of how to map their designs into the resources available inside the FPGA. An example might be that the critical path when you have negative slack to go through a slow run resource. With the pull-down menu you can decide that this specific slow run can be implemented in the fabric. That’s how you can solve your timing issues.
We are the only ones in the industry that has graphical representation, cross probing and an easy way to analyze the resources utilization and quickly remap to solve timing or other mapping problems.
We have given the tool to our partners. They have checked it themselves. Altera has checked it with its own design suite. In this case there are over 70 designs. They found significant improvements in quality of results for new products. Obviously, we do not know what those designs are. They have observed the same results we have. Xilinx has given us a quote saying “you know guys the capability you have been developing is needed because that this what our customers have been saying to us. That means you did a good job in the right places.” Pierre-Xavier of IP Extreme is an example of an end user that always faces challenges of maximizing the speed of their cores. They are
creating IP. They want to make sure that their IP runs on the fastest clock possible. They realized in that case 17% improvement in Fmax which is very significant.
Where does the new Precision RTL Plus product fit into the Precision family?
Up to now we have had Precision RTL and Precision Physical. The new product lies in between. We believe that it will become our flagship product because of its unique capabilities. It has all the Precision RTL capabilities and features plus the first to market capabilities. Precision Physical is a superset. It also has the new features.
What is the pricing for Precision RTL Plus?
The starting price is $27,500.
Is that a time based license?
It is a node locked perpetual license.
How does that price compare with other member of the Precision Family?
Precision RTL starts at around $20K. Precision Physical is much more expensive. Precision Physical has capabilities for advanced physical synthesis, debugging and placement resuse/eco. Most of the time Mentor customers are not paying list price but are paying based upon what they buy overall.
If I completed a design using a Xilinx FPGA and Xilinx tools and wished to migrate that design to Altera and obviously not having used Precision RTL Plus for the original design, would I be able to do this as smoothly as if I had used Mentor’s product in the beginning?
If you started the design with our tools, that is the best way. It gives you the smoothest transition. What you are describing is very possible and is indeed being done. Many times people who are using other tools are coming to us for business and performance reasons. The transition of the design that was done with another tool to our tool is not painful.
Is it conceivable that if I used Xilinx tools or Alter tools for a design that I might end up with some IP from those vendors. If so, would that make it more difficult to migrate to the other vendor?
Yes of course. When you are using tools like Precision, it will enable you and even encourage you so to speak to minimize the use of IP that locks you into specific silicon. If you are using a tool from a vendor, you might end up using much more of those IPs. We support the IP flow of the vendors but obviously if you are using IP that is for a specific vendor, it will be more difficult afterwards to shift to another vendor. By using vendor independent tools we make sure it is the easiest for you to do. But of course IP is one of the methods to lock the customer to a specific vendor.
Do Zuken or Altium have anything in the FGPA synthesis arena?
If one wants to use FPGA prototyping for a large ASIC, one may need to partition the ASIC design to fit onto multiple FPGAs. How does this situation fit into the Precision RTL Plus flow?
There is a stage called partitioning whereby as you said correctly some big ASICs if you want to prototype all of them you need to partition it because it doesn’t fit into one FPGA. In this case you can either do it manually but when you have to partition into too many, you might want to consider automatic partitioning. For that approach we have a certified flow with a company called Auspy. For customers who need automatic partitioning because the ASIC is too big to fit into one FPGA, they can do manually and then use Precision or use the certified flow between Auspy and Precision.
Is this a different type of partitioning than the one you discussed earlier?
Yes. Before I was referring to cases where you have one FPGA and in order to benefit from incremental design flow, you need to partition the single FPGA design into multiple blocks. But it is still one FPGA. The second type is where you have a very large FPGA which can not fit into one FPGA. Therefore you have to partition the ASIC deign into multiple FPGAs.
Does Cadence, Synopsys or Magma have any offerings in FPGA physical synthesis?
Cadence and Synopsys are not in the physical synthesis market. Synopsys used to be but they are no longer. For Magma it is not their focus. They might have something. We don’t come across them.
When it comes to FPGA synthesis, you have four major players. You have Xilinx and Altera. We are cooperating with them but they have their own synthesis but only for their tools. You have of course Synplicity and Mentor. These are the four major ones. If you ask how Lattice or QuickLogic and other FPGA vendors do synthesis? The answer is that they usually oem synthesis software from us or from Synplicity. As far as we know, we are the leader in oeming software to FPGA vendors.
On the backend if you do not want to use your own board we offer off the shelf solutions. We are partnering with companies like ProDesign. The ecosystem to completely support FPGA and AASIC prototyping is there.
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-- Jack Horgan, EDACafe.com Contributing Editor.