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October 01, 2007
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


When the size of geometries fell below the wavelength of the light used to print them, certain undesirable lithography effects appeared. The shapes of geometries were distorted relative to the idealized form used to represent them during design and hence the manufactured chip behaved differently from the designed version. This often led to yield loss. The approach has been to develop resolution enhancement techniques (RET) to correct for these effects after the fact. The best know technique is optical proximity correction or OPC. Similarly effects due to chemical metal polishing or CMP have been addressed by adding metal fill. Collectively these techniques were referred to as design for
manufacturing or DFM. As the old adage says an ounce of prevention is worth a pound of cure i.e. doing things during design to avoid or reduce these manufacturing effects should be preferable to after the fact corrections. So design rules were developed for this purpose. Unfortunately this can lead to guard-banding making timing closure more difficult. Further the number of rules has increased significantly over time. More recently model based approaches have been developed to give designers insight to the likely impact of these litho and CMP effects and to enable them to modify their designs before tapeout.

Cadence has acquired several firms including two over the last few months with DFM technologies for both design and manufacturing. During its recent CDNLive! Cadence announced a broad set of new design products and capabilities that provide “what you design is what you get” (WYDIWYG) modeling and optimization for critical manufacturing variations during the design phase.

I had an opportunity recently to discuss this with Mike McAweeney.

Would you give us a brief biography.

I am Vice President of DFM Marketing. I have been with Cadence for 14 years of the last 17 years in a bunch of different roles. Before that I was at LSI Logic. I have a designer background. At Cadence I moved into the DFM role about 9 months ago. Prior to that I was in a group called the Industry Alliances that was focused on low power solutions across the ecosystem.

This summer Cadence made two acquisitions in the DFM arena. In July there was Invarium. What was the motivation for this acquisition and what did Cadence get from it?

The simplest way to think about Invarium is as the next generation RET (Resolution Enhancement Technology) focused on the synthesis and optimization of the layout to mask flow. The leaders in that space over the last several years have been Synopsys and Mentor Graphics with their OPC (Optical Proximity Correction) technology. What we have seen with that technology is a new generation that provides the accuracy needed at the advanced process nodes. We are currently working with memory suppliers at 32 nm half pitch which is similar to 22nm logic. What those customers are seeking is to get the accuracy that is required at those very fine geometries given the 193 nm litho equipment
as well as the broadest process window. Even with a significant amount of defocus we still manage to get very good prints of the original GDS onto silicon.

How big a company was Invarium at the time of the acquisition?

It was about 30 people. The stage of the company at the time was technology. It has been applied mostly through part of service engagements. It has been applied to customer challenges but it has not been a product to date. We are just in the process of productizing it.

So their DimensionPPC was in alpha or beta status by Cadence standards?

Yeah. It was really used in particular engagements where the customer came to them and said “This is an interesting technology giving us the accuracy in the process window that we need to be successful. Can you take this design as a service engagement, fix it for us, come onsite and help us go through the design?” It is very good technology for solving tough problems.

That is the process and proximity correction approach?

Exactly Right.

How does that differ from other approaches?

It has to do with the way the models are built. The others sort of do a purely experimental creation of models. It takes many, many iterations over a long time. That is why you hear people complain about three to four months to create the models. We have some examples where the typical creation of the model would be 3 to 4 months and then the first few masks that came out with that model don’t give the CD (critical dimension) uniformity and accuracy of the transistor that is required. So then there is the tweaking of the model and the next set of masks come out. The whole process can take up to a year. We have some sample engagements where it took a year with the
competing solution and it took us about 3 weeks. Our approach is physics based models. We actually model the physics of all the steps between the layout and the mask including modeling the mask. Then we take that model and calibrate it against the actual silicon process. We can do model creation measured in days and get the first OPC done in a matter of one or two weeks and 3 weeks for the whole process.

Wouldn’t the model verification have to be done for every foundry and process node?

Absolutely! We calibrate the model for every foundry and different processes within the foundry.

Last month, the middle of August, Cadence acquired ClearShape. What was the motivation for the acquisition and what did Cadence get?

The customer base for Invarium is the manufacturers of the silicon. When they get a chip from their customer whether it is an internal design customer or a fabless customer of the foundry, the technology is used to correct that and make it printable. ClearShape’s focus is on the design side. It provides technology that models the whole lithographic process from layout to mask. It creates a model of the process that the designers can use. It is both high speed and high accuracy, the right sort of combination of speed and accuracy. So when designers are designing, they can take into account these lithographic effects and can understand if they are going to have catastrophic yield failures and they can fix them. They are called litho hot spots. The designers understand after they have fixed the hot spots there are still going to be effects due to lithography. They can comprehend the effects on things like timing and power. You can understand that you are going to have a timing issue when you take into account the fact that the transistors will look different than the ideal transistors you laid out and the wires will look different from the ideal wires you laid out. It can take all of that into account from a catastrophic perspective as well as from an electrical perspective. The technology is being used today. It has been integrated already into both Virtuoso
and Encounter platforms. We have been working for about a year and a half with ClearShape and a number of customers that wanted that capability both in the custom space and for developing standard cells, PLLs and things like that. They wanted to be able to understand litho effects and correct for the hot spots. We have an interface with Virtuoso that is for people doing full blown SoCs. We interfaced with ClearShape technology potentially for the same purpose to identify hot spots that will cause litho failures, fix those and then take those litho effects into account when you do power and timing analysis.

Are the ClearShape products, namely InShape and OutPerform, now offerings within the Cadence portfolio or have their capabilities been incorporated into existing products?

It is still a standalone product that we sell. It is our strategy to makes these integrations even tighter in the Cadence flow. But customers can also use them in competing flows as well. The InShape product is now the Cadence Litho Physical Analyzer and the OutPerform product is now the Cadence Litho Electrical Analyzer.

What is the list price of these products?

They are officially going into the price book at the beginning of next year. But we are engaged with a number of customers whom we have given access to the technology. We will hold off on providing their list prices until we formalize it in the price book. It will be similar to what the ClearShape pricing was.

Editor: At time of its introduction by ClearShape InShape pricing started at $300,000 per master license per year. Distributed Processing was also available at incremental pricing. The same price was given for OutPerform.

When the technolgy identifies hot spots how is that information fed back to the designer?

Good question. Let’s step back to the design tools that can read that information in from a file that is called hot spot interface format (HIF). This file format has two elements to it: the x,y location of the hot spots and a hint as to how to fix that hot spot. You move this wire 3 nm west and this wire another 2 nm to fix this hot spot. It gives a series of hints. Those hints and hot spot locations go to our nanoroute technology which will correct for the hot spots as well as the Cadence Chip Optimizer which also corrects for them.

If this techncology is to work not only with Cadence RET/OPC tools but other vendors’ OPC tools, don’t you have to know something about how each such tool operates?

The strategy even prior to the acqusition by Cadence was to be RET/OPC agnostic. The approach they have taken is to work with the foundries to develop test chips. They have proprietary algorithms that do not just model the litho effects but the whole transformation from the original ideal layout structure which looks like a bunch of rectangles to what actually gets printed on silicon and read through sen images as contours. They have built some pretty heavy duty math that takes the transformation between all those different scenarios of patterns in GDS II and the corresponding patterns that come through on silicon. They do not need to model or comprehend the specific OPC tools.
They take into account a lot of other things beyond OPC like biasing and retargeting, things that go on from the time the layout is accepted by the foundry until the time when those patterns are printed onto silicon. They model that whole process. The advantage of this approach is first off it is very, very fast. It is also quite accurate.

TSMC went through a process over the last year and a half of qualifying different litho tools or litho analysis tools on the design side to determine which tool would be what they call the litho process checker, the LPC. They asked customers to run an LPC tool before taping out so that they would know that they are getting litho clean designs. The first product to be qualified at 65 nm, 55 nm and 45 nm and until recently the only product that was qualified was ClearShape. It was way ahead of anybody else. It sort of speaks to the level of accuracy provided. They also provide much better speed than competing technology because they take their OPC tool and repurpose it for the design
side. It can take one to two weeks to run a litho check on the design side which is impractical for designers. They need an overnight run type of tool.

How big a company was CleaShape when Cadence acquired it?

They were in the 30 to 40 person range.

How much did Cadence pay for ClearShape.

I’m sorry. We are not disclosing that information.

What did Cadence recently announce at CDNLive?

We announced a design flow RTL to GDSII targeted at the most advanced processes, 65 nm and 45 nm. The purpose of this design flow is to really enable custmers to account for the variability in design at these advanced process nodes, to bring the knowledge of manufacturing effects to the designer so that they can tape out knowing they are going to get a yield without over guard-banding. Before this technology was available, the approach most people would take is to just guard-banding. The big manufacturing effects were litho and CMP. Doing that guard-banding makes it more difficult to achieve timing, to meet your power and area requirements and to close your design. It impacts
every axis of the design, if you have to add too much guard-band. It allows designers to take away all that excessive guard-banding, model those manufacuring effects and understand where those effects impact what parts of the design and to compensate where you have to and don’t compensate where you do not have to. That’s the key is allowing the design to manage the variability of the design.

The way we do that is we provide these models with litho, CMP and random variation effects into the design. The approach we provide to the flow in three phases. There is a prevention approach where you try to prevent these manufacturing effects from getting into the design in the first place through automation. Then the analysis phase where we analyze the design for maufacturing effects like CMP and litho. And then there is optimization phase where you correct for the effects and optimize the design for yield.

As part of this flow we have introducted a number of new technologies. The first new technology is built into our existing Encounter nanorouter product. It is a fast litho estimator. Essential what it does is as the tool is routing it identifies patterns that are going to be hard to be printed by the manufacturer, those that are lithographicaly challenged. It manages to avoid those paticular routes. It will come up with alternate routes that will be clean from a litho perspective. This technology typically reduces the number of hot spots by as much as 60 percent to 80 percent right off the bat. It gets rid of the gross errors very quickly.

The next technology we introduced is a litho physical analyzer that was previously the InShape technology from ClearShape and then the Cadence Litho Electrical Analyzer which is the high performance technology. The difference between the two products is that the first one, the physical analyzer, is the one that looks at your design, it could be a custom block in Viruoso or it could be a full chip in Encounter, and it analyzes that design using the model that the foundry creates to identify what we call the litho hot spots and gives hints on how to correct those things. It then passes those to the optimization engine for correction. The other thing the physical analyzer does is it
creates contour of the actual structures. So if you lay down a wire, it actually shows you the curvey shape of the wire due to the litho effects. The Cadence Litho Electrical Analyzer has the technology to extract those contours and understand the impact of those countours on both timing and power. So you get more accurate power and timing analysis.

The third technology we are introducing is the Cadence CMP Predictor. This is a technology based on the Praesagus acquisiton about a year and a quarter ago. This predicts the thickness variability due to CMP effects and once again identifies hot spots in this case CMP hot spots where you have too much variability, too big hills and valleys in the design that could cause yield fallout. It also identifies the impact of that thickness variability on timing. It passes information to our extraction engine which extracts the thickness variability and applies that to timing.

The last technology that is part of this release is the Encounter Timing System GXL. Last year we introduced the Encounter Timing System which was our static timing analysis tool. That has done quite well in the marketplace. We are now introducing a new version, GXL, which is a high end version that does statistical timing analysis. The high level goal of that technology is not to require designers to run a number of corners where they do timing analysis of best case/worse case combinations of power, voltage, process and temperature and then look at litho, CMP and other sources of variability. The number of runs from the corner perspective is growing substantially. Rather than that
approach we take a statistical compliation of all these effects and apply that to one run that does the variability of timing and from that you can determine whether you can tape out.

There are variability effects due to lithography. A transistor that is drawn in the Cadence environment, the Virtuoso environment, and what actually gets fabricated is different. There is a signifcant amount of variability in how different those shapes look. You can have complete control of the process window but a transistor whose neighbors are different and there are some 40 different cases, has variability in its performance and timing. At one process window you can have up to 22% variability based just on the context of where that transistor sits relative to other transitors and up to 300% variability in leakage. That can be compounded by the fact that the focus and exposure of your
litho equipment can vary as well. So you can see a compounding of effects due to litho at 45 nm.

For the flow that we designed we coined the term “What You Design Is What You Get or WYDIWYG” The basic concept is that what people layout is not what gets manufactured. There is a significant difference. The focus of the flow is for people to be able to comprehend and model those differences with the manufacturing effects and apply those to their design so that what they signoff when they signoff their chip has taken into account those manufactruirng effects. So what they get back from manufacturing is closer to what they designed and so what they designed is what they get back. If what you designed is not what you get, then the approach has been to just
over compensate through margin. This makes it more difficult to close timing and you can still miss some of the manufacturing problems.

Within the Soc Encounter GXL platform you have prevention capability, nanoroute which prevents bad litho patterns from getting into your design. Then we have the Cadence Litho Physical Analyzer and Cadence Electrical Analyzer that gives the designer insight into the impact of litho on the design from the both a yield and an electrical perspective. Then the CMP Predictor which gives the thickness variability. Those tools drive the optimization which automatially corrects the litho and CMP hot spots. Then there is the Litho Physical Analyzer and Electrical Analyzer that predicts one last time for signoff as well as the Encounter Platform GXL which gives statistical analysis of your
timing. Then you are ready for signoff.

The foundation of our strategy is that at the core it needs to be endorsed by manufacturers. For everything we do we need to work closely with foundries to create models, calibrate those models and make sure the manufacturers endorse those models. Everything we do has to be silicon validated. So we are working closely with customers to ensure that the DFM flow does in fact produce chips that are manufacturable. We are now in the process of trying to quantify yield impact of these flows.

What we are delivering needs to be a complete DFM solution. What we have heard time and time again from customers is that they are not interested in point tools. They want tools that are integrated into the overall flow. The main components of the strategy are having DFM comprehended in the implementation, enhancing the extraction technology to take into account manufacturing effects, enhancing physical verification which today has been a design rule checker to be not only a rule based approach but also a model based signoff approach for things like CMP and litho. The optimization being able not just to identify manufacturing problems but to automatically correct those problems.
Manufacturing is really what drove the Invarium acquisition. Even if we can make the design as clean as possible coming out of the Cadence system, because we (the industry) have decided to stick with 192 nm even down to 22 nm geometries, there is still going to be a strong need for a new generation of OPC technology and layout to mask optimization technology. That is the area of focus for Cadence.

The way we look at the whole Design For Manufacturing flow is that there are three different phases: implementation, signoff and manufacturing. The implementation phase is a matter of taking models and integrating those models into the Encounter and Virtuoso Platforms so that customers can find their manufactuirng yield limiters while they are designing. The optimization is the automation of the correcting those manufacturing effects. On the bottom is extraction though electrical analysis, the ability to comprehend those manufacturing effects on timing and power. Then signoff is leveraging a lot of the same technology. The focus on the implementation is making sure you have the performance so that it is usable by the designer. In signoff the focus is making sure you have the accuracy so that people can signoff with confidence. We are working with partners on a model based verification flow that includes not just DRC and LDX but also includes the models of manufacturing effects as well as the ability to do yield scoring, to rank order the impact on yield of these different manufacturing effects and rank order the hot spots so you fix the ones that have the most impact on yield first and then also understand the qualitative analysis of what the yield goodness is based upon different implementations of your design. Yield scoring is work done in partnership with IBM. We did a
joint white paper on model based verification last week at CDNLive! that went into a lot of details. Once again you have extractrion through electrical signoff and final yield optimization. Then we move into manufacturing and that’s where we automate the process from layout through mask design.

One of the big annoucements last week was that Cadence is now in a position to deliver a pretty comprehensive suite of technologies in each of these different environments. In implementation we have the analysis technology, the optimization technology and the extraction technology for timing. In signoff we have the analysis technology with the level of accuracy that people need. We have the DRC technology with physical verification. We have optimization technology and extraction to electrical technology. In the manufacturing space we have DimensionPPC. We also have mask compose which is technology we have had for about 4 or 5 years which is the leading technology for laying out the mask
and the wafer.

The litho estimation technology built into the router prevents sixty to eighty percent of the erros from ever getting into the design. Virtuoso, our custom platform, has a rule based checker to enable designers to prevent litho hot spots as they are designing. The Cadence phase router, that is the technology that came out of the Catina group, that prevents yield limiters from ever getting into design, a sort of DFM aware router for custom digital blocks. People designing big processors use that technology.

From an analysis persepctive we have the Cadence Litho Physical Analyzer that detects the hot spots. The Litho Electrical Analyzer that analyzes the impact on timing and power and then the CMP Predictor that analyzes the thickness variability, identifies hot spots and drives the extraction of CMP on the effected wires.

On the optimization phase there is the Cadence Encounter GXL, the high end version of Encounter, that has the Cadence Chip Optimizer built into it, has enhancements to the nanorouter built into it that automatically corrects the litho hot spots based upon the HIF file that the Litho Physical Analyzer sends. It moves wires around to fix those hot spots. It does optimized metal fill. It takes those hot spots from the CMP Predictor due to thickness variability and optimizes the metal fill which will reduce the variability of thickness.

Then it does additional optimizations to improve yield like optimizing the vias and wiring. In signoff there is a lot of the same technology. We have a very strong presence in the custom space with the Assura technology and then our new technology which is PVS is focused on the large digital blocks as well as full blown SoCs. Then we have the model based verification approach which enhances physical verification, the lithos and CMP models and the optimization capability. Once again the key in signoff is that you are qualified by the foundries to have high levels of accuracy. The Litho Physical Analyzer is qualified by TSMC to have up to the highest level of accuracy for 65 nm, 55 nm and 45 nm. This is the first one to be qualified. The Cadence Electrical Analyzer provides the signoff accuracy for timing and power analysis and the CMP Predictor. This is the technology we spent the last year working with the foundries something like 12 different foundries. I should say 12 different fabs, a combination of pure play foundries and IDMs, to qualify it at 65 nm and we are also doing that at 45 nm as well. That is far greater than any other tool in the market. Nobody else has qualified anywhere other than TSMC because TSMC provides the model to all the different CMP tools whereas for all the other foundries, pure play and IDMs, their model for CMP is something that is created
specific to the particular tool. We are qualified pretty much everywhere. I think we are the only one qualified anywhere.

Then there’s the Cadence Chip Optimizer which corrects those hot spots which the CMP Predictor and the Litho Physical Analyzer identify. It does that while preseving timing integrity. When you are getting ready to signoff and have already done timing closure, you want you optimizer to be aware of the timing and be able to make adjustments to the design without violating the timing paths.

The last one is layout to mask optimization. I mentioned DimensionPPC which provides a high level of accuracy at the advanced nodes, and the CMP process optimizer. We are introducing a version of our CMP Predictor which is targeted at the manufacturers to help them optimize the CMP process as they are developing it, as they are ramping up the CMP process at the next process node. It helps them model that and helps them optimize the actual process. Then the Cadence Mask Compose which is used to layout the reticles and the wafers, a very strong technology in the marketplace.

Have you copyrighted the WYDIWYG phrase?

I don’t know. There is a term that came out years ago WSIWYG for What You See Is what You Get. That came out I think in the seventies. It had to do with matrix printers. Our phrase is a play on that. I do not know if we have copyrighted it.

What about CMP?

CMP is the next challenge at 65 nm and more so at 45 nm. A couple of big things happen at CMP when we moved from aluminum to copper which started at 130 nm. Copper has better performance but it is also softer. When you do CMP, when you do the polishing step, the manufacturing metalization depending upon the topology of your design along with the metal fill that you add to it, you can end up with certain areas polishing deeper than other areas. You end up with hills and valleys in your design and in your manufacturing. So you sort of compound things. At the lower levels you may have small hills and valleys but they can compound on top of each other. You might have a small hill on level 4 and then on metal 5 you might have a small hill on top of that and on metal 6 and so on. So you can end up at the higher metal layers with pretty big hills and valleys. If you get to that point, you end up with the potential for what is called copper pooling which can lead to shorts between wires. We have seen that in a number of examples. In fact at CDNLive! last week, a couple of customers presented papers about the fact that they had a number of designs where they had significant yield loss due to pooling because they did not have the ability to analyze it. Even though the design was DRC clean, they did all the metal fill and they did everything they normally do but at higher metal layers they had copper pooling and significant yield loss. They took their design data bases and worked with us to create the CMP models. When they ran our tool on their design, they were able to identify about 20 CMP hot spots which was a big yield killer. What it shows is that number one a pure rule based approach can not comprend the effect from layer to layer. It does each layer separately, so you can end up with multilayer effects. You need to be able to model that impact in a 3D sort of way, looking through each layer as well as the interations between layers. That is what the CMP Predictor does. It can identify copper pooling. What you do from there is that you use that information to drive your metal fill so that it is not what you would call dummy fill. We call it intelligent metal fill. It takes a lot of the knowledge about the actual hills and valleys and applies the metal in a more intelligent way. It also does not over metal fill because every additional metal fill causes coupling capacitance that effects timing. So you want it only when you need it. That’s the big focus of the CMP Predictor. The last thing it does is that it actually understands the changes in the shapes of wires due to CMP and drives that into the timing analysis tool. When you are running timing, you can take into account what is called dishing erosion which impacts the
shape of wires. Our QRC extraction tool can take this file from the CMP Predictor and use that to drive more accurate timing.

Who do you see as the competition and how does Cadence differentiate itself?

On the CMP side I think we are pretty unique. The way we differentiate is because we have been qualified by a dozen different either pure play foundries or IDMs on the manufacturing side. As far as I know we are the only one qualified at all those places other than TSMC. TSMC’s strategy has been to provide the model to all the CMP tools on the market. In that regard the competitors have models as well as us but otherwise we are pretty much unique. The Common Platform has made the statement that the CMP Predictor is their standard tool for thickness variability. The CMP Predictor is very unique in the market. The uniqueness of the litho analzyer from ClearShape comes from a couple of things. First off it is OPC agnostic. The competing tools in the market have basically taken their OPC technology to the design side. The limitation there is that if the manufacturer is using an OPC tool from vendor A, then on the design side it is only company A’s tools that would be applicable. ClearShape is independent of whatever OPC tool is being used. The other quick differentiator for the technology is that the approach they took was rather than simulating the OPC function itself, they model the entire layout to printing on silicon structure. We model that whole flow which includes more than just OPC. It includes all the effects of biasing and things like that. It
is more comprehensive. The approach is also very fast. The comprehensiveness is what enabled us to get qualified very quickly before everyone else by TSMC at 65 nm and 45 nm. That it is very fast makes it applicable not just for signoff but also for doing implementation because they can do an implementation flow during the day, run litho analysis overnight and understand the impact of litho on things like timing. It considers litho much earlier in the design

How much of Cadence’s revenue or what percent of Cadence’s revenue comes form DFM?

I don’t now if I am in a position to discuss that right now. It is a key growth area for us. I can say that.

Editor: DFM accounted for 9% of revenue in 2005, 7% of revnue on 2006 and 7% of revenue for the first two quarters of 2007.

During the course of this interview you have mentioned four or five acqusitions in the DFM arena by Cadence. Why do you think that technologies like this seem to come from two guys over a garage rather than from R&D groups within a billion dollar company?

I wouldn’t say it is two guys over a garage. There are cetainly technologies that we develop internally. We have a large inernal development organization that have developed a number of technologies. A perfect case in point is the Cadence Chip Optimizer and the phase space router which was completely organically built. The Encounter Timing System and the Encoundter Timing System GXL as well. They are all technologies that are internally developed. The internal team also builds integrations and design flows. Our responsibility to the customers is to provide the best and complete flows including technologies within those flows. So when we see an acquistion that makes sense
to deliver the best solution to our customer then we will decide whether we acquire or whether we partner and what is the right solution for our customer.

Editor: It is rather commonplace for large companies in this industry to acquire small startups for their technology. Of course not all startup are acquired and even fewer are going public these days. Development teams for large firms have the responsibility for enhancing broad product portfolios by increasing performance, adding features, improving usabililty, porting to new operating environments, interfacing to emerging standards and third party offerings and so forth. They also have to support customers and sales efforts. While these efforts may be relatively straightforward they present considerable demands on time and resources. Developing new technolgies from scratch is
far riskier. Startups have the luxury of being able to focus on a specific problem and to use the very latest available tools. Often time their technology is based on years of research in academia. Acquiring a startup with demonstrable technology and customer testimonials minimizes the risk of developing one’s technology. And of course there is always the issue of patents.

The top articles over the last two weeks as determined by the number of readers were:

Microsoft and Cadence to Cross-License Patent Portfolios Microsoft Corp. and Cadence Design Systems Inc. have entered a patent cross- licensing agreement, expanding on a long-standing relationship between the two companies. The agreement allows broad access to each company's respective patent portfolios to facilitate future technical collaboration in areas of common interest to both companies.

Since 2003, when Microsoft announced it was "open for business" on IP, Microsoft has continued to license its IP portfolio, providing access to the fruits of its significant R&D efforts. The company maintains a growing worldwide quality patent portfolio that includes several thousand issued and pending U.S. patents. Recent Microsoft cross-licensing collaborations include Cisco Systems Inc., LG Electronics, Samsung Electronics Co. Ltd., NEC Corp., Seiko Epson Corp., Siemens AG, SAP AG and Toshiba Corp.

Berkeley Design Automation Selected by Matsushita Electric Industrial Co., Ltd. for Digital-RF Chip Design Platform Berkeley Design Automation, Inc., provider of Precision Circuit Analysis technology for advanced analog and RF integrated circuits, announced that Matsushita Electric Industrial Co., Ltd. has entered into a partnership for analog/RF and mixed-signal design verification for Matsushita's Digital-RF Chip Design Platform. The partnership is based on the technology from Berkeley Design Automation's Analog FastSPICE and RF FastSPICE tools which provide full SPICE accuracy,
with 5x-10x faster speed and 5x-10x higher effective capacity than traditional circuit and RF simulation. Matsushita's design teams will use this capability to further its lead in complex digital-RF ICs for mobile communications and digital TV.

Mentor Graphics Accelerates FPGA / PCB Design Collaboration with New I/O Designer Product Targeted at PADS Users Mentor announced the availability of the PADS I/O Designer product specifically targeted at its PADS product user community. For designers implementing complex FPGAs on their PCBs, the I/O Designer product has a proven track record of decreasing design cycle time, improving performance, and lowering product costs. These same benefits are now available to the PADS product users at an aggressive entry price as the use of high density, high performance FPGAs increases across
the spectrum of electronic products. For the first time the PADS I/O Designer product is being made available to the PADS community.

Ciranova Appoints Eric Filseth as CEO Ciranova, Inc., an EDA start-up developing open and robust automated layout technology for analog and custom integrated circuit design, announced that Eric Filseth has been appointed chief executive officer. Filseth spent a total of 17 years with Cadence Design Systems, where he was most recently marketing vice president for Digital Implementation products. He also held executive positions with Silicon Perspective Corporation and Sente, Inc. Previously, he managed product marketing for analog, RF and mixed-signal products at Cadence. He started
his career in 1983 as an analog design engineer with National Semiconductor. Filseth received an MBA from UCLA and a BSEE from Stanford University.

Nikon and Synopsys Announce Manufacturing-Aware DFM Solution for 45 nm and Below Nikon Corporation, a lsupplier of lithography equipment for microelectronics manufacturing, and Synopsys announced that Nikon's proprietary optical lithography exposure tool data is available for the latest release of the Synopsys Proteus optical proximity correction (OPC) software. As part of an ongoing collaboration, the two companies developed an embedded scanner parameter module, which delivers the "manufacturing-aware" OPC and resolution enhancement technology (RET) lithography simulation models
needed for advanced 45-nanometer (nm) and below IC (integrated circuit) manufacturing. Mutual customers can benefit from improved OPC model accuracy and reduced time to silicon.

Other EDA News

  • picoChip multicore-DSP: Forty-Fold Better Cost-Performance than Traditional DSP in Berkeley Design Technology Independent (BDTI) Benchmarks

  • EDA Consortium Hosts CMP and their Presentation of 'The Future of Media and What it Means to EDA Companies'

  • Simucad Releases Enhanced VBIC SPICE Model

  • Synopsys Recognizes Engineers' Technical Excellence With Best Paper Awards at SNUG Boston Conference

  • Pyxis Announces NexusRoute, DFM-aware, Yield-driven Auto Router

  • Pyxis Technology Teams with PDF Solutions® on Yield-driven DFM Routing

  • EVE Set to Kick-Off Worldwide Seminar Series

  • Synplicity Launches Newest Addition to the HAPS ASIC Prototyping System

  • Dubai Silicon Oasis Chooses Synopsys to Establish First IC Design Center in the United Arab Emirates

  • Renesas Technology Adopts Cadence Statistical Timing for 45NM

  • Virtutech Simics to Support IBM Mambo Processor Model

  • Mentor Graphics Announces Precision RTL Plus for FPGA Synthesis -- Vendor-Independent Solution for Breakthrough Productivity

  • Cadence Expands Research Laboratory to Extend Technology Leadership

  • Synopsys Star-RCXT Extraction Solution Achieves Industry's Broadest 65-Nanometer Qualification and Usage

    Other IP & SoC News

  • National Semiconductor's New Audio Amplifier with Spread Spectrum and Integrated Boost Architecture Reduces EMI Sensitivity in Portable Applications

  • Atmel Announces the Only WiMAX Transceiver with Internal Calibration

  • Impinj Delivers Reprogrammable Nonvolatile Memory IP Breakthrough - AEON(R)/MTP World's First 2.5V Floating-Gate NVM in TSMC's 65 Nanometer Process

  • Broadcom Delivers World's First Single-Chip 802.11n Solution

  • ITC Upholds Ruling Favorable to AnalogicTech

  • Lightspeed Logic to Discuss Reconfigurable Logic Applications at the IEEE International SOC Conference

  • Analog Devices Introduces RF Transceivers for Mobile WiMAX Applications

  • Intelleflex Debuts Extended Capability RFID Tag for Use in Challenging RF Environments

  • Cypress Introduces World's Smallest USB Transceiver to Conserve Board Space in Mobile Handsets

  • Motorola Unveils Revolutionary WiMAX Chipset for Handheld Devices

  • Broadcom Introduces Advanced Single-Chip GPS Solution for Mobile Applications

  • OmniVision OV7725 CameraChips Power Fitivision CS-1000 IP Cameras for Security Market

  • GDA Technologies Announces Availability of HiGig IP

  • New Three Channel LED Driver IC From Supertex Provides High Current Accuracy

  • GCT Semiconductor Announces Sampling of the Industry's First Mobile WiMAX IEEE 802.16e Wave 2 Compliant 2.5 GHz Monolithic Single-Chip Solution

  • Freescale Introduces World's First Multi-Stage RFICs Optimized for 2.7 and 3.5 GHz WiMAX Base Station Power Amplifiers

  • Alchip Selects Verigy V93000 SOC Series Pin Scale as Next Generation Test Platform

  • Tilera Names Industry Veteran Omid Tahernia CEO

  • NXP Unleashes Advanced UHF Smart Label ICs

  • 40 Years After Inventing the Electronic Handheld Calculator, Texas Instruments Launches TI-Nspire, Math Technology For 21st Century Needs

  • Power.org Debuts Specification Advances and New Services At Power Architecture(TM) Developer Conference

  • TI Power Management Fuel Gauge Accurately Predicts Battery Life in Smart Phones and Other Handhelds

  • New High-Speed Amplifiers from National Semiconductor's PowerWise Line of Energy-Efficient Products Provide the Industry's Highest Performance at the Lowest Power

  • Lattice Semiconductor and Silicon Laboratories Collaborate on SONET/SDH Compliant Solutions

  • AMFELTEC Corporation Launches Universal In-Circuit Programmer "Easy Loader"

  • Xceive and Genesis Launch Reference Design Supporting Digital and Analog Broadcast Reception for HD Flat-Panel TVs

  • Sequans and PMC-Sierra Deliver Complete Mobile WiMAX Femtocell

  • Xilinx Announces New Low Cost, High Performance DSP Development Platform

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    -- Jack Horgan, EDACafe.com Contributing Editor.