September 10, 2007
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
| by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!
As always, the pace quickens as the autumnal equinox looms and a host of fall conferences elbow their way onto the calendar. Summer is almost history and it’s back to life in the fast lane.
There’s a range of news in this edition of EDA Weekly. QuickLogic is redefining its position in the market, MIPS is acquiring Chipidea Microelectronica, Synopsys has announced a significant partnership with SMIC, Altera’s been working overtime, Cadence says it’s well on its way to establishing a DFM methodology, AWR has a new EM analysis tool, and a plethora of companies are paying close attention to automobiles, televisions, and mobile devices in China. There are also good books to read and seminars to attend, but let’s start
with some recent indicators that the world’s not quite as flat as Friedman claims. Click on Print Article to avoid the click-throughs.
Skip this section if you’re sure the world is flat
Paraphrasing from recent press releases:
Belgium – IMEC announced that Qualcomm has joined IMEC's technology-aware design program (TAD). IMEC and Qualcomm say they’ll be collaborating on innovative circuit and system-design methodologies. IMEC set up the TAD program to develop a methodology built on top of commercial design tools and flows, relevant to 45 nanometers and below, that propagate variability and reliability data from the technology level to the device, circuit, and system-architecture level. IMEC VP Rudy Lauwereins is quoted: "We are very pleased that Qualcomm acknowledges the strength of our TAD program. This proves the value of our solution, which
starts at an earlier stage in the design flow than is being offered today by design-for-manufacturing solutions." Qualcomm Sr. VP/GM Behrooz Abdi is also quoted: "We are pleased to be a part of IMEC's TAD program, collaborating on next-generation design flows, and ultimately optimizing results."
France – France says it boasts several zones dedicated to advancing nanotechnology excellence, including the SCS cluster in Sophia Antipolis, the Systematic cluster in the Paris region and the global micro-nanotechnology cluster, Minalogic, in Grenoble. Minalogic is investing 80 million Euros into eight new collaborative projects focused on micro and nanotechnologies for semiconductors and manufacturing, while recently announced partner Hewlett-Packard is providing access to 2-TeraFlop data processor “virtual nodes” for Minalogic cluster partners. France’s nanotech laboratory CEA-Leti
and Japan’s Nikon announced a joint effort to examine double patterning and double exposure technology for 32-nanometer devices, while Japan’s Yamatake is also working with Leti to develop nanotechnologies. California-based Monolithic Power Systems has opened headquarters in Bernin-Crolles, Boc Edwards has moved its European semiconductor headquarters from London to Grenoble, and Clinatec, an experimental nanotechnology-based neurosurgery clinic, expects to open in the next several years, benefiting from work being carried out at Minatec, Europe’s largest research
center in micro-nanotechnologies.
U.K. – Queen Elizabeth II previewed the latest research in wireless body sensors and personalized healthcare in July when she officially opened the Institute of Biomedical Engineering at Imperial College London. The event was hosted by Prof. Chris Toumazou, Founding Director and Chief Scientist of the Institute, who had his heart rate monitored wirelessly via a "Sensium-enabled" digital plaster during the ceremony, and posted to a PDA – a technology being brought to market by Imperial College spin-out Toumaz Technology.
QuickLogic – nimble, mobile, and proud
It took 3 hours and 1 sumptuous meal to drive home 2 ideas at QuickLogic’s recent press and analysts luncheon at the Four Seasons Hotel in East Palo Alto on August 28th.
Idea No. 1: QuickLogic wants to be more than a garden-variety, also-ran in a crowded field of FPGA providers. As CEO Tom Hart put it, in a clear reference to QuickLogics industry position relative to Xilinx and Altera, “Who needs another Dr. Pepper when you’ve already got Coke and Pepsi?”
Idea No. 2: Thanks to Reed Publishing’s master lexicologist, Ron Wilson, QuickLogic has a new moniker – CSSP provider. That’s Customer Specific Standard Product provider, or in QuickLogicSpeak: “Your idea. Our platform. Customized for you.” By revisiting their purpose in life, QuickLogic has discovered they’re no longer an FPGA provider. They are, instead, a one-time programmable CSSP provider perfectly/uniquely positioned to meet the sharply escalating worldwide demand for programmable single-chip solutions for the wireless devices market.
So why did it take 3 hours to get these ideas across to the 30 folks who came to lunch at the Four Seasons in August? Well, the first hour was consumed by a detailed presentation about the wacky world of wireless, delivered up by Francis Sideco, Senior Analyst for Wireless Communications at iSuppli.
Sideco said, by his calculations, the wireless devices market clocked in a cool $600 billion in 2006, and is set to grow 7.7 percent annually going forward when you throw everything into the calculation – 3G, 4G, Wlan, wireless broadband, a range of different devices, standards, variable infrastructures, and the kitchen sink. And despite/because of these opportunities, Sideco said the situation in the wireless market today is tantamount to a war between a finite set of commercial players duking it out for domination.
He argued that in the past, the high-end and ultra-low-end markets in wireless straddled the medium-cost and feature-rich markets sandwiched in between. Now, however, those middle markets are moving out. They’re cannibalizing from above and below to create a voracious new mid-market niche, which combined with the geo-specifics of China and India [“There are already more wireless subscribers in China than we have people in the U.S.”], is transforming the wireless industry into a “capital intensive, high-stakes game” where successful players are only staying abreast of their competition through flexible, platform-based designs.
Based on that analysis, Sideco concluded that QuickLogic is perfectly positioned to meet the need, and yielded the floor to lunch and the folks from QuickLogic.
As we all wolfed down a truly gourmet meal, CEO Tom Hart took the podium and told us that QuickLogic is having a lot of success in the market with their new CSSP initiative. He thanked Ron Wilson for coining the term, and noted one need only go to the FCC website and surf the device tear-downs there to quickly ascertain the notable, but unnamable, customers in QuickLogic’s repertoire.
He elaborated on QuickLogic’s evolution from FPGA provider to CSSP provider: “We no longer have FAEs – field application engineers. Now we have CSAs – customer solutions architects.” (Who, he assured me after lunch, are not competing with QuickLogic customers, but partnering with same.) Hart also pointed out that QuickLogic’s CSSPs can brag on a better energy-per-bite-transferred metric than their competitors’ technologies, and a tidier form factor. All told, he was clearly pleased and said QuickLogic’s only limited by bandwidth when it comes to meeting the huge demand for CSSPs.
Never one to shy away from candor, Hart then made short work of several questions put to him after his prepared remarks were complete. Yes, QuickLogic will still offer FPGAs “to legacy customers who aren’t put off by the fact that they’re one-time-programmable.” No, the company is not being reorganized in the wake of the CSSP re-launch, except that “we’re no longer selling through reps [because] you’ve got to partner with your customers [to succeed].” And no, QuickLogic does not see a threat from either structured ASICs or ASSPs: “You’ve got to build a flexible platform [to succeed in the wireless market], and ASSPs are not
flexible.” Structured ASICs aren’t a threat to CSSPs either, he said, because they arent a threat to anyone. Period.
He wrapped up his presentation, and the event, by stating several self-evident truths: “It turns out customers like the value of a sustainable core technology,” and “The consumer electronics guys are like birds. All you hear from them is, Cheap. Cheap. Cheap.’” Clearly, Hart believes QuickLogic’s CSSPs are positioned to step up to the challenge on both fronts.
Who says there’s no such thing as analog IP?
MIPS Technology is acquiring Portugal's Chipidea Microelectronica SA, an analog IP company. The Press Release outlined the details: “Under the terms of the transaction, MIPS Technologies will pay an aggregate of $147 million in cash, with an additional performance-based milestone payment of 610,687 shares of MIPS Technologies' common stock in 2009. MIPS Technologies will make an initial payment of approximately $120 million [on August 27th] from its current cash reserves, with the balance released from escrow within two years subject to an indemnification holdback and deferred payments for the Chipidea co-founders remaining with the
MIPS CEO & President John Bourgoin sees synergy in the acquisition: “Analog represents an essential component of our IP growth strategy, and has become one of the key strategic considerations in customer designs today. Chipidea is the clear leader in analog IP with a broad product base, an impressive array of customers worldwide, and excellent financials. The synergies of MIPS Technologies and Chipidea are compelling for our customers' SoC design initiatives.”
Reflecting additional synergy, Chipidea just announced that Cadence Design Systems is licensing Chipidea's USB 2.0 OTG Link Controller and PHY for integration into Cadence’s newly announced SoC Functional Verification Kit (see below).
2008 Olympics as tech driver
First, per the Press Release: “As the Beijing 2008 Olympic Games are drawing near, more fabless and design companies are targeting the digital TV market. The research and development of relevant chips are advancing at an unprecedented speed. However, there is currently no uniform standards in low-power design, IP access, and foundry access for local manufacturers in the mobile TV market in China, making it tough when they want to compete in the market.”
Therefore, Synopsys and Semiconductor Manufacturing International Corp. (SMIC) have announced a “strategic alliance to develop a low-power design solution optimized for the mobile TV market in China, while also providing key IP components
the solution is based on 130-nanometer and 90-nanometer fab processes. In addition, the companies will provide key IP required by mobile TV IC designers
[The agreement] also calls for the provision of design and counseling service to help Chinese chip manufacturers take timely advantage of opportunities in the mobile TV market.”
Chi-Foon Chan, President and COO of Synopsys, is quoted: “It's our great honor to form this strategic alliance with SMIC to support Chinese chip manufacturers and the development of the digital TV market.”
Richard Chang, SMIC President and CEO, is also quoted: "Synopsys has a leading technology advantage in IP and low power design. I believe our cooperation will promote the development of China's digital TV sector's standards and marketplace."
Cadence – the WYDIWYG DFM flow
Though it may not be the most euphonic of names, Cadence’s new DFM initiative – What You Design is What You Get – is not out to win any word-smithing contest. It is, however, out to win one of the biggest prizes in EDA – dominant market share in the design-for-manufacturing world.
Monday, September 10th marks the opening day of CDNLive! in Silicon Valley, and it also marks the formal announcement date for WYDIWYG. I’m guessing that’s not a coincidence. If you’re at CDNLive!, you’ll hear all about it there. If you’re not, here’s a thumbnail sketch of the announcement, based on a phone call and PowerPoint presentation I shared with some of the folks from Cadence on August 31st.
Cadence VP Eric Filseth acknowledged that any DFM flow is a complex one, with multiple targets – floorplanning, signal integrity, timing closure, IR drop, dynamic and passive power, ATPG coverage, and DFM closure, among others – and not necessarily in that order. He also said, at 65 and 45 nanometers, people are distressed that what they’ve designed is not necessarily what’s coming out of the fab, so they’re putting a lot of guardbanding into their designs. Too much guardbanding, which wastes money, time, real estate, and power. Now Cadence believes they’ve got the answer to all of this DFM “whack-a-mole” stuff (my phrase,
not Eric’s) and hence it’s here – the Cadence DFM flow.
WYDIWYG includes, per Slide #2 on the PowerPoint presentation: New design capabilities for 45 nanometers, accurate modeling of manufacturing effects within the design flow, prevention, analysis and optimization through physical design and signoff, new core technologies – patent-pending fast litho estimation and InShape/OutPerform litho physical and electrical variability analysis (courtesy of last month’s Cadence/Clear Shape acquisition) – plus a new CMP Predictor and Encounter Timing System GXL statistical timing analyzer.
In a nutshell, it’s a “model-based, variation-aware solution” that’s heavily dependent – per Nitin Deo, now at Cadence thanks to the Clear Shape acquisition – on the “deep relationships” that Cadence has built and continues to maintain with organizations such as IBM, TSMC, UMC, and so on. In other words, the people who can give Cadence the info and/or models they need to get the manufacturing-awareness back upstream into the hands of the designers.
Okay, so there are some of the words from the WYDIWYG phone call and PowerPoint presentation. Now the hard part begins.
Will the customers understand WYDIWYG, and will they “get it” in both senses of the word? Will they comprehend WYDIWYG? And, will they buy WYDIWYG?
Cadence clearly believes the answers to both questions will be yes.
Read any good books lately?
Okay, they’re not trashy novels, but you’re too cool for pulp fiction anyway:
* Understanding Fabless IC Technology – Straight from the FSA (Fabless Semiconductor Association), this one sounds like it might be a keeper, even at $69.95. Elsiver’s the publisher and you’re probably the reader if you’re interested in 300+ pages discussing the number one business innovation in the semiconductor supply chain over the last 20 years – the fabless/foundry model. The FSA says the book is targeted at a wide audience – everybody from fabless employees, to IDMs, suppliers, investors, legislators, entrepreneurs, and college students – and “gives insight into the various aspects of the
outsourced semiconductor supply chain, [describing] the interdependence semiconductor companies have with these suppliers using the fabless business model. [It also] addresses questions on how fabless employees should handle various cultural, language and time zone differences, to ensure operational efficiency.”
I haven’t actually seen the book up close, but it was waved around in front of the audience at the August 21st FSA luncheon in Santa Clara, so I know it really exists. You can buy it on Amazon and you’ll get a discount if you’re an FSA member.
* SystemC Behavioral Synthesis Style Guide from HD Lab, Inc. promises to be “a reference book that documents production-proven expertise and design techniques based on SystemC.” The company says the book captures its 3 years of experience in SystemC design, verification, and methodology consulting, and provides “well organized, easily implementable” suggestions for the reader. In fact, they’re so sure you’ll love this book, they’re suggesting that you’ll reduce design cycle time on projects with over 3 million gates by anywhere from 33-to-50 percent. Along with an intro to SystemC, the book
includes coding suggestions for design reuse and behavioral synthesis examples using Forte Design Systems’ Cynthesizer. You can get the book by interacting directly with HD Labs, but I’ll bet Forte can also help you out should you be looking to add this one to your library.
* Cellular Handset & Chip Markets '07 – It’s not cheap ($3750), but this one from Forward Concepts promises to keep you up at night. It’s an “in-depth study” of the worldwide cellphone market and the chips that love them. If you order the study, you’ll get 370 pages, info on 100 companies, and “dozens of forecasts by technology and by region through 2011 of handsets, subscribers, and chips of all types. In addition, the report provides estimates of the market shares of cellphone vendors by air technology (GSM, GPRS, EDGE, CDMA2000 1xEV, 1xEV-DO, WCDMA, WEDGE, HSDPA and even
PHS/PDC/iDEN/TDMA).” Can you hear me now?
Your $3750 will also get you some stern advice from study co-author, Carter Horney: "The cellphone continues to be the physical and market magnet that is pulling in the functionality of digital cameras, PDAs, MP3 players, GPS navigators, Bluetooth, FM Radio, digital TV, cordless phones and even smart cards, and is quickly becoming the dominant market for each and all of these functions. Companies making such stand-alone products would be well-advised to understand how their market will be affected by cellphones." Consider yourself warned!
Got extra time on your hands?
* CDNLive – September 10th to 12th in Silicon Valley
* EDA Tech Forum – September 12th in Silicon Valley
* FSA Suppliers Expo – September 12th in Silicon Valley
* Denali's PureSpec VIP Training Course – September 14th in the Bay Area
* Embedded Systems Conference – September 18th to the 21st in Boston
* Chartered 2007 Technology Forum – September 19th in Shanghai, September 21st in Beijing
* Power Architecture Developer Conference – September 24th & 25th in Austin
* Xilinx Serial Connectivity Seminar – September & October in a variety of locations across North America
* 17th Annual IMEC Research Review Meeting – October 18th & 19th in Brussels
* The 5th International SoC Conference – November 7th and 8th in Newport Beach
And then there's the news
* Applied Wave Research (AWR) announced its AXIEM electromagnetic design tool. The company says, “AXIEM delivers EM analysis as a true upfront design technology, where it benefits designers most by helping to diagnose issues early
The AXIEM product was developed for 3D planar applications such as RF PCBs and modules, low temperature co-fired ceramic (LTCC), monolithic microwave integrated circuit (MMIC), and RFIC designs
The technology is an open boundary, non-gridded, method-of-moments (MoM) solver that supports true thick metal in layered dielectric media
The solver algorithm [was] pioneered to overcome limitations of existing 3D planar
formulations that rely on the Sommerfeld (or similar) integral for delivering speed of simulation at the cost of accuracy and dynamic range
The AXIEM meshing algorithm supports thick metal, in that it creates 3D meshes of extruded planar geometries, correctly accounting for all x, y, and z directed currents on all surfaces
a prerequisite for successful design of 90-nanometer and 65-nanometer RF CMOS, where line thickness is often in parity (1:1 ratio) with line widths. Similarly, thick metal support is required to correctly characterize silicon spiral inductors as well as very large designs like complete GaAs MMICs.”
* Altera’s been busy! First they announced that Tsinghua University used Altera’s Stratix FPGA to develop China's Digital Multimedia Broadcast Terrestrial national digital television broadcast standard (DTMB, also referred to as DMB-TH). Per the Press Release: “The DTMB standard became the mandatory terrestrial TV signal for Chinese broadcasters on August 1, 2007.
“The digital video modulation IP in the standard will be used by all digital TV system suppliers providing video transport equipment to broadcasters in China. Supported by China's State Administration of Radio, Film and Television (SARFT), the terrestrial DTMB standard delivers digital television signals to fixed television sets and mobile televisions found on public transportation. The DTMB standard uses both time-domain synchronous orthogonal frequency-division multiplexing and vestigial sideband multiplexing. The Stratix II FPGAs are optimal for the standard because the devices include all the logic, DSP blocks and memory required for the application's complex signal processing
* Next, Axon Digital Design announced it used Altera’s Stratix II GX FPGA to create a quad-split module that Axon says is “the first commercially available” video signal processing product that supports triple-rate SDI standards, useful in high-resolution monitor walls for the surveillance and television industries. Per the Press Release: “With the GQW200 quad split
broadcast studio engineers can readily accommodate 270-Mbps, 1.5-Gbps and 3-Gbps SDI signals.”
* Then, Dune Networks announced its SPAUI code for Altera’s Stratix II GX FPGAs: “SPAUI, an interface based on the XAUI industry standard, incorporates several extensions to support dense 10Gbps-level applications with speedup, for accommodating such factors as packet headers, full rate 12GE, and in-band flow control.” Dunes CEO Eyal Dagan is quoted in the Press Release: “"Since FPGAs have always been at the forefront of interface transitions, the SPAUI definition has inherent flexibility to take advantage of an FPGA-based implementation. Altera's Stratix II GX FPGA devices support SPAUI today with no
changes and with minimal logic requirements at both 3.125Gbps and 6.25Gbps."
* Then, Edgeware announced it’s using Altera’s Stratix II and Cyclone III FPGAs, “to achieve previously unattainable performance and scalability with its groundbreaking video-on-demand server Orbit 2x, [with which] on-demand and interactive television service providers can deliver up to 20-Gbps output, streaming to as many as 8,192 concurrent viewers at the lowest cost per stream.” Kalle Henriksson, CTO at Edgeware, is quoted: "Altera's Quartus II development tool enabled us to maximize our engineering efficiency. We spent 95 percent of our time on actual design, which is the best I've
experienced in 15 years of FPGA design.”
* Finally, Altera announced its EP3SL150 65-nanometer Stratix III FPGA family, which includes 150K logic elements and the “lowest power consumption of any high-density, high-performance programmable logic device.” Thomas Stubitsch, Chief Architect at XtremeData, is quoted: "Some of our customers are asking for maximum logic density, while others are asking for the highest double precision floating point performance. The Stratix III 'L' and 'E' families allow us to offer both."
* Anchor Bay announced an expanded sales and support networks in Asia and Europe. The company now has distribution agreements with ASEAN (Singapore, India, Malaysia), China, Taiwan, Korea, and the U.K. (including the Nordic regions), and four new distributors: E-Smart Distribution (Singapore), Weikeng Industrial (Taiwan), ProGate Technology (Korea), and Sequoia Technology (U.K.). Per the Press Release: “The partnerships will position [Anchor Bay] for aggressive growth and enable it to tap the increasing market demand for its products in the Asian and European regions.”
* ARC International announced five new members of the ARC Video Subsystem family: AV 417V, AV 407V, AV406V, AV 404V, and AV 402V. The company says all of these products include “patent-pending dynamic encoding" of video streams at the lowest power. The Press Release also says, “The products are capable of encoding and decoding up to Standard Definition resolution video using advanced video coding standards such as H.264. Each [new product] is programmable, encodes and decodes a wide range of popular video standards, and comes with optimized media processing elements.”
* Averant Inc. announced its SolidPC 2.0 property-checking product has been awarded an AMBA 3 Assured status. Per the Press Release: “SolidPC was the first formal verification product for AMBA interconnect compliance to be endorsed by ARM, in 2003, and remains the only formal verification product to have achieved AMBA 3 Assured status.” Not surprisingly, Averant is a member of the ARM Connected Community.
* The Embedded Microprocessor Benchmark Consortium (EEMBC) announced publication of certified benchmark scores for NXP Semiconductors' PNX1702 media processor. Per the Press Release: “Tested against EEMBC's ConsumerBench digital imaging and DENBench digital entertainment suites, the PNX1702 achieved exceptionally high scores for a 499.5 MHz device, with out-of-the-box scores of 89.9 Consumermarks and 94.4 DENmarks.”
* Cadence Design Systems announced the Cadence SoC Functional Verification Kit, which the company says provides “design and verification IP from Cadence and third parties, including an accurate high-speed model of the ARM968E-S processor, AMBA PrimeCell IP including interconnect and peripherals, the ARM RealView Development Suite debugger, USB 2.0 from Chipidea, and 802.11 from WiPro. The kit includes three main flows – architectural, RTL block to chip, and system-level – [and] provides complete example verification plans, transaction-level and cycle-accurate models, design and verification IP, scripts
and libraries – all proven on a wireless segment representative design and delivered through applicability consulting
The Cadence Incisive Plan-to-Closure Methodology will support the Open Verification Methodology (OVM) in Q4 2007, which is based on Cadence's Incisive Plan-to-Closure URM module and Mentor's Advanced Verification Methodology module.” That’s the long version of the announcement. Here’s the short version:
Per Chang-Soo Kim, CTO at Kairos Logic: "The Cadence SoC Functional Verification Kit is just what is needed for today's feature-rich SoC designs."
* Frontier Silicon and Fraunhofer IIS announced what the companies are calling “the world’s first range of DAB+ radios. Solutions incorporating Frontier Silicon’s multi-standard digital radio SoC Chorus 2 with Fraunhofer’s audio decoder IP are being designed into products from specialist brands including Bush, Grundig, Magicbox, Ministry of Sound, Pure, Revo, Tivoli, and others, which will be available in shops by the end of this year.”
Steve Evans, VP Sales and Marketing at Frontier, is quoted: “As DAB+ is being adopted by an increasing number of broadcasters worldwide, we are pleased to announce that our DAB+ solution is being integrated into a variety of audio products, including table top, clock radio, battery powered and WiFi enabled radios. While DAB+ is not required for established markets such as the UK and Denmark, this development will help to accelerate the global adoption of digital radio.”
* Interra Systems announced a license agreement with Dolby Laboratories for supporting Dolby Digital Plus and Dolby TrueHD audio technologies in Interra’s Vega family of offline audio/video analyzers. Sabine Bravo, Senior Manager of Professional Licensing at Dolby, is quoted: "Dolby is excited to work closely with Interra Systems to enhance its Vega family of media analyzers for advanced analysis of encoded audio with Dolby Digital Plus and Dolby TrueHD technologies. We're confident that with these added Dolby technologies, Interra Systems has the right components in its analyzers to help authors ensure high-quality HD content."
* LogicVision announced “major enhancements” to its embedded SerDes test solution. The company says, “The new release provides more accurate measurements and the ability to perform bit error rate testing (BERT).” Farhad Hayat, VP of Marketing at LogicVision, is quoted: "The latest enhancements to ETSerdes accommodate the increasing levels and types of noise on today's nanometer ICs and deliver more test capabilities for reuse in the end-application."
* Mentor Graphics announced an agreement with the College of Automotive Engineering of Tongji University to set up a Joint Lab and Technical Training Center for auto electronic system design in Shanghai. Mentor Graphics says it will donate $16+ million worth of software in order to support Tongji's teaching and research programs.
Yu Zhuoping, Dean of the College of Automotive Engineering at Tongji, is quoted: "Our cooperation with Mentor Graphics gives researchers, faculty and students of the College access to the most advanced auto electronic system design software in the world. We are confident that this cooperation will enhance Tongji University's research capabilities and its influence on both domestic and international auto electronic system industry."
Danny Perng, GM for Mentor Graphics China, is also quoted: "The rapidly developing China market has been a top priority for Mentor Graphics. We have been increasing our input in China in recent years. By engaging in strategic cooperation with the College of Automotive Engineering of Tongji University and other specialized academic institutions, Mentor Graphics makes its substantive contribution to high-level technical personnel training in East China with our quality products and service capabilities in the China market.”
* Mentor Graphics also announced its PCI Express (PCIe) Controller and AMBA Bridge IP products for “rapid and cost-effective integration into ASIC and SoC platforms.”
Kishore Mishra, President and CEO of ASIC Architect, speaks about the joint effort leading up to the announcement: “As a leading provider of high speed controller IP solutions, ASIC Architect partnered with Mentor Graphics to deliver our silicon proven PCIe solutions to the market. ASIC Architect has been at the forefront of solving complex IP and integration problems of today’s SoC designs. By working closely with Mentor Graphics’ world-class support and sales teams, we will be able to reach a much broader base of designers and integrators.”
Bill Martin, Mentor’s GM for IP in the Embedded Systems Division, is also quoted: “These leading PCIe Controller and Bridge IP solutions from ASIC Architect expand our specification-compliant and high-performance IP portfolio and accelerate our IP subsystem strategy.”
* MIPS Technologies announced that PowerLayer Microsystems has licensed the MIPS32 24KEc processor core to “advance the development of next-generation digital television (DTV) products". Per the Press Release: “Today, Asia Pacific represents MIPS Technologies’ fastest growing region worldwide. Asia Pacific’s rapid growth has resulted in unprecedented consumer demand for home entertainment, a market where MIPS has been building a prominent position. According to In-Stat, the popularity of digital television in China continues to grow - in 2006 alone, nearly seven million households were converted from analog cable
TV to digital cable.”
* OCP-IP and the NEXUS 5001 Forum announced a collaboration that the organizations say “will ensure an improved and more integrated on-chip debug tools solution for SoC, software and IP.” Did you know that the Nexus 5001 Forum was created in 1999 and is focused upon on-chip debug solutions based on the IEEE-ISTO 5001, the Nexus 5001 Standard for a Global Embedded Processor Debug Interface?
* Also noteworthy: The OCP-IP Debug Working Group announced a white paper “discussing a standardized Debug Interface Socket and OCP-bus compliant debug interfaces for IP blocks and cores to support on-chip core, multicore, and systems analysis and debug needs for software, hardware, and mixed SoC prototyping.”
* The Open SystemC Initiative announced a new website, which features “fresh technical content, a range of free downloads [and] links to the activities of worldwide SystemC user groups.” If you check out the site, you’ll find free downloads of the IEEE 1666-2005 Language Reference Manual, open source OSCI standards, and the documents and minutes related to OSCI technical working groups. OSCI President Mike Meredith is quoted: "We now have a modern, interactive website that will bring forth the best that the community has to offer in SystemC collaboration and advancement."
* PLDA announced a new business division, Application IP, that the company says is designed to “leverage PLDA's high speed bus IP core designs into key vertical markets.” Those markets include video/broadcast, automotive, and bridging applications.
* Rambus and Cadence Design Systems announced they have collaborated to offer: “PCI Express digital cores and PHY IP from Rambus, tightly integrated and verified with Cadence verification IP. [The new offering] includes the Cadence Compliance Management System (CMS) featuring a PCI Express compliance verification plan (vPlan) and compliance tests, both of which have been specifically customized to the Rambus design IP.”
Testimonial comes from John Brown, VP of Engineering at Tilera: "Using the combination of the Rambus configurable PCI Express Digital Controller with the independently developed verification IP from Cadence enables the rapid and successful IP integration we are looking for."
* Solido Design Automation announced a $6.5 million second round, which the company says brings its total funding to $9 million. The new financing was led by Golden Opportunities Fund, and included BDC Venture Capital, Victoria Park Capital, and private investors. Not surprisingly, Ulrich Felbermayr, Senior Investment Manager at Golden Opportunities Fund, is now a member of the Solido Board of Directors.
* The SPIRIT Consortium says they’ve partnered with Demos on Demand to create online presentations summarizing recent demos from various vendors showcasing their successes with IP-XACT. The demos are online and include content from ARM, Beach Solutions, Denali, Magillem Design Services, MataiTech, Mentor Graphics, NXP, Scarlet Code, and Synopsys.
* Synopsys announced that eRide is using Design Compiler Ultra to design its "Opus" GPS “low-power, high-functionality ICs, that include ultra-sensitive positioning technology to help wireless carriers reduce the costs.” Allen Chen, VP of VLSI Engineering at eRide, is quoted: "Advanced synthesis technology coupled with excellent support from the Synopsys team drove our decision to adopt Design Compiler Ultra for our next-generation Opus ICs."
* Synopsys also announced SHARP Corp. has evaluated Synopsys’ DFT MAX, and “has demonstrated in working silicon that this new small delay defect ATPG technology improves quality and is cost-effective when deployed with DFT MAX to compress the test data.” Synopsys said it has collaborated with both SHARP and STARC (the Semiconductor Technology Academic Research Center R&D consortium) to develop this ATPG technology.
Hiroyuki Shibata, Department GM in the LSI Test Engineering Department, Large-Scale IC Group at SHARP, adds: "We wanted to apply all the patterns without slowing down the production line or making costly changes to our ATE infrastructure. We achieved this by reducing the test data volume by 95 percent using DFT MAX to implement scan compression on-chip.”
* Synopsys announced, as well, that Tessolve has adopted Synopsys' DFT MAX. Per Mohit Bansal, Director of DFT Engineering at Tessolve: "DFT MAX is a straightforward extension of the standard scan techniques using Synopsys' DFT Compiler and TetraMAX ATPG design flows currently in use at Tessolve. Because TetraMAX supports automated diagnosis of DFT MAX-compressed test patterns, analysis of failed patterns on the ATE can be completed much faster and cost-effectively."
* Tsantes Consulting Group (TCG) announced that Toshiba America Electronic Components (TAEC) is now a client. Hideya Yamaguchi, Sr. VP at TAEC, is quoted: “We need to work with an agency that has a deep understanding of all aspects of the semiconductor business, how that business relates to the end consumer and one that also has close ties to the media. Tsantes Consulting Group is that agency.”
* X-FAB Silicon Foundries announced sales of $186.2 million for H1 2007, an approximate 69% increase over H1 2006. Per the Press Release: “The X-FAB Group attributes this growth to consistently high demand for its technologies and services, and its expansion including X-FAB Sarawak and X-FAB Dresden.”
* Xilinx announced that intoPIX will port its IP portfolio to Xilinx Virtex-5 platform FPGAs. Per the Press Release: “The intoPIX JPEG2000 encoding algorithm running on a Xilinx Virtex-5 FPGA, allows encoding at up to 120 frames-per-second (fps), over 20-percent faster than previous solutions. This creates the potential to create a multi-stream encoder delivering up to four channels of HD-SDI image management at 30 fps.”
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-- Peggy Aycinena, EDACafe.com Contributing Editor.