August 06, 2007
It’s the Network Stupid, the Network-On-Chip, that is.
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| by Jack Horgan - Contributing Editor
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Scott McNealy and SUN Microsystems popularized the concept that the “network is the computer”. Ateris, Inc is a Paris-based start-up that seeks to deliver network-on-chip solutions (NoC) to address the problems of on-chip communication for complex SoCs using lessons learned from network procesors. Arteris' NoC solutions transport and manage the on-chip communications within complex SoC integrated circuits, increasing performance, reducing number of global wires, with lower power utilization while enabling the most complex, IP-laden designs. It allows chip developers to implement efficient and high-performance NoC designs, overcoming limitations of traditional layered or
pipelined bus-based architectures. In mid-June the company announced a Series B round of investment if $8.1 million led by Synopsys. I had an opportunity to interview Charles Janac, president and CEO of Arteris.
Would you give us a brief biography?
I started my high tech career by being employee number 2 of Cadence on the EDA side. I spent about 10 years at Cadence in various sales, marketing and financial positions. My final job was as VP of the Analog Division. I became president of HDL (High Level Design System), the first floor planning company that was ultimately acquired by Cadence. Then I ran a robotic company that made semiconductor equipment called Smart Machines. We sold that to Brooks Automation in 1999. Then I spent about a year as an EIR (Entrepreneur-in-Residence) at Infinity Capital. Then I ran a company called Nanomix which was a nano technology company that made the world’s first working nano electronic
sensors. After that I would up being CEO of Arteris in Paris, France.
How does a person educated as an organic chemist (BS and MS from Tufts University) end up in EDA?
Damn good question. Basically it was circumstances. I had some time on my hands between the first and second year at Stanford Business School. Jim Solomon, the founder of SDA, offered me a job. I wound up in and around semiconductor industry ever since.
You are not a founder of Arteris. How did the company start?
Arteris was basically a spin off from a company called T.sqware. They got bought by Globespan. Then there was the dot.com meltdown in the early 2000s. The founders of Arteris came up with the idea of scaling down the networking technology that was built for networking processors, scale it down to operate as a network inside a semiconductor chip. They got early funding ($12 million) from venture capital firms: Crescendo Ventures (US), Techno Venture Management (Germany) and Ventech. I was brought in two years later to put sort of a sales and marketing spin on the company and to get the first accounts.
The VCs brought you in.
How did that work out? What was the reaction of the founders?
The CTO, one of the founders, was pretty much gone when I started. With my taking over the company Alain Fanet, a founder and CEO, moved to the board and out of operational responsibility. The third founder, Philippe Boucard, kind of the architect of the network-on-chip, is still with us as head of the hardware group.
The firm just announced another round of investment.
Yes. We just completed a Series B round of investment in June led by Synopsys, raising $8.1 million to help fund future growth.
How large a company is Arteris?
We have about 43 people.
Is there a revenue stream?
Yes. We started shipping for revenue in the beginning of 2006.
How large is that?
We typically do not discuss that. It is growing nicely.
Where are you located?
I am actually in Paris, France at the moment. As part of the recent financing we wound up doing something called a flip. Right now we are a French company with a US subsidiary. We made a change where we are an American company with French and American subsidiaries. We went to a holding company structure. I will be permanently based in California starting in August.
Are you fluent in French?
My French is terrible.
I believe that most professional at least in high tech speak English but I doubt an America EDA firm would hire a senior executive who did not speak English regardless of location.
I speak Italian and Czeck. I have European citizenship. I was born in Prague. I have a high tech background. I have learned enough French so that I can communicate pretty well. The rest of my family is better in French than I am. Most of our engineers speak English so it is not much of a problem.
I once had a short consulting assignment in Budapest. They said they would arrange for an interpreter. It turned out that this was not necessary because all the technical people spoke English very well and of course apologized for not speaking it better.
The language is the easy part. The harder part is the culture, understanding the cultural nuances. It is not the easiest thing to be a multicultural CEO.
Was the issue of wanting to be headquartered in the US more due to the possibility of going public in the US or more due to where the market is?
Arteris did it because Synopsys wanted to be dealing with a US entity. We have pretty good penetration in Europe. These days from a point of view of going public, there are still some advantages of going public on the NASDAQ but dollar volume is higher on the Aim market in Europe. So it is almost a toss up. My attitude is that these days in this type of market you have to be global, a strong presence in both management and engineering support in the US, the European community and in Japan. The management has to move across these three geographies and make sure they function correctly.
When the company started was it a case of having some technology or did they identify a market opportunity or both?
Both! They saw a problem which was that chips were getting much more complex, that hardware costs were going up. For the future the right structure is the network instead of a dedicated wire or a bus. They also had some technology. They had 10 years of experience in networking from building network processors. They had a lot of know-how on how to optimize for low power, using as few wires as possible, packet transport. So they had a lot of expertise that could be applied to this problem.
What were the short comings of the traditional bus architecture?
It is kind of equivalent to what happens in an office environment when you have a few computers and one or two printers. Then having a dedicated cable works just fine. When you have hundreds of computers, 20 printer, scanners, gateways and so on, a dedicated cable becomes less attractive as a technology. The same thing is happening on a chip. Even two years ago when I started with Arteris, the state of the art was that people were just starting to get to 130 nm. They typically had maybe six or ten IP blocks. At that point the network approach was a “nice to have”. Now we are at 65 nm. We are seeing chips with more than 100 IPs. We are doing the first 45nm benchmark. It is
very clear that, we used to say 5 years, but it is really 3 or 4 years that buses are going to be done because they are too complex and too inefficient. You have too many wires, consuming too much power, you have multilayer bridges. It is much less elegant approach than having a network. This is the same thing that has happened in the office environment.
Is there any company offering similar products to Arteris?
In terms of competition we are the first and only Network-On-Chip. However, there are two other companies that have products that offer commercial interconnect. A lot of companies still do their own home made interconnect. We think that is going to become more and ore challenging and expensive to do. Obviously, ARM has some interconnect technology in the form of AXI and AHB. There is also a company called Sonics that has reasonably capable product that is being used on a commercial basis to interconnect all these blocks.
Will you give us an overview of the Arteris product offerings?
We call our product Arteris NoC (pronounced knock) Solution. It is comprised of three elements. The first is network-on-chip library of networking elements: switches, network interface units, adapters, those kinds of things. That is the hardware part. From this library a network-on-chip instance is configured to customer’s requirements. The other thing we provide is a toolset, two tools. One is called NoCexplorer, a network communication exploration tool for system architects at a very early stage of design cycle to define their traffic patterns. Then there is a tool called NoCcomplier which is based upon those results that scales the IPs, allocates the right level of hardware
resources for the communication requirements, spits out the NoC instance in RTL which goes directly into Synopsys or Cadence synthesis tool.
Is there one NoC instance per SoC?
Yes! On a chip you have the memory, processor, video engines like JPEG and NPEG, the audio stuff and some analog stuff. Then you have the interconnect. We provide about 10% of the chip with our latest product.
Three products: library, explorer and complier.
There would also be methodology. We have know-how on how to improve the architecture for data communication. We share this methodology with our customers. These are specific to multimedia, telecommunication and wireless SoCs.
Do you charge for sharing this methodology?
No! It comes free with the tools and the library.
What is the pricing and packaging for you products?
We have two basic models. One is a license plus a royalty. The other business model we have is a pure license model. We give the customer the option to either pay for NoC from the gross margin where we share the risk with the customer or from the ?
Which is more popular?
The license model is more popular.
The sweet spot is SoCs in the multimedia, wireless and telecom industries. Typically 90nm or below at around 200 MHz in terms of frequency and more than 15 to 20 IPs. It is basically a complexity threshold where the NoC adds a lot of value. People have SoCs with smaller complexities than that but the NoC at some level of complexity becomes completely essential and this is a kind of break point.
The NoC has a layered architecture.
It is like a network, the standard 7 layer protocol except scaled down. We use three different layers to isolate the IP from the data communication. We isolate each layer from each other. Not only is the NoC approach more wire efficient and more power efficient, it is also more reliable.
The three layers are the transaction, transport and physical layers.
The Transaction layer typically happens when the signal is packetized. The transport layer routes the packet through the switch fabric. The physical layer is the wires.
Greater reliability comes from using layer appropriate approaches?
Correct. It is pretty much the same in the office environment. If you have a cable connection and a communication problem anywhere along the wire, you have a major problem. Whereas a network basically allows does not impact others. You can do error correction. You can do all sorts of tings. You can do Quality of Service determination where some packets have higher priority than others. You have all kinds of flexibility.
Do you have any concerns about protecting your intellectual property?
We deal with some of the largest corporations in the world. They typically have pretty good IP protection. We also have some protection schemes inside our things. The technology is protected by patents. We have not had any issues in his area.
Do you have a roadmap for Arteris’ future direction?
Yes! Basically our goal is to make network-on-chip more and more important as the level of complexity increases in SoCs. We think that the network-on-chip will be the most important part of the SoC in the future. We are bringing together technology functions every release that will allow us to get there.
From a sales and marketing point of view, how do you go about increasing the market given that Arteris is the only company in it? Is it still a missionary sale?
Absolutely, it is still a missionary sale, brand new technology. We have to sell directly except in Japan. We sell with very qualified support people. We get involved with the projects themselves when the architecture is defined. It is a strategic missionary sale. But ultimately the market is very large. Over the next 6 to 10 years it will be almost a $1 Billion.
One of the challenges of a new technology is the degree to which the target user has to change. Change is always difficult. Change means risk. How do you convince people, particularly system architects, to move to a NoC approach for the next chip?
We have made some pretty good technical decisions. One of the significant decisions we made is that we will not impact the customer’s IP or the EDA flow. We can deal with Cadence, Magma and Synopsys unmodified. We do not make the customer change the IP. If you are using an ARM processor, an AMBer call IP using a MIPS processor with memory and memory controller IP from Synopsys or Denali those kinds of things do not have to be changed That makes the technology easier to adopt. The challenge is that the NoC has quite a bit of benefit in terms of improving the architectural performance over the bus so we get involved in discussions with the system architect about how to best take
advantage of the network-on-chip in order to improve the architectural performance of the SoC.
Is that because the cost if known and fixed?
The royalty makes sense in certain cases. It just depends on the situation. If you have a situation where the NoC enables the chip to exist, where there is a lot of business risk or there isn’t a lot of capital available then the royalty model makes sense. On the other and if you have a chip that has a very determined market share with customers for it so the business risk is very low then our customers would prefer the license approach.
Is there a target market or a sweet spot for you products based upon the end use application?
There are actually two types of target users. One is the system architect. The other users are the integration people. The first thing that is done for the SoC is the data communication architecture. So we get involved very early in the cycle. One of the last things that is done for the SoC is integration of the physical design. We get involved with the integration people. We also get involved with the verification people. Three groups inside the customer that touch this technology.
Would it be fair to say that the system architect would be the peon to make the decision to use this product?
From a technical perspective that’s correct. But it also winds up to be a strategic decision. We get involved with fairly high level executives as well. It is kind of strategic sale where you have to align the technical level and the management level in order to be able to proceed.
What benefits do you tout to the executive level?
It is things like much greater wire efficiency, lower power, higher system bandwidth, higher frequency of operation. At the strategic level it is really about time to market. We allow people to lower their design costs because with this kind of network-on-chip toolkit, you get your chip and particularly your derivatives out faster. We lower the cost of the design chips themselves because there are fewer wires. In the case of complex SoCs there are fewer gates and we lower project costs. There it is about economics and being able to deliver to your customer quicker. We have a more predictable methodology.
How do you prove to a prospect that your product does what you claim it does?
With typical benchmark. People want to know that there are some working designs out there. So we do it with tapeouts and with a benchmark say on an existing design or the last generation design.
What is the sales cycle with the typically customer?
It is all over the map because the designs typically take 18 months. The design cycle can be as long as 18 months. But most people do two projects or more. It is somewhere around 9 months on average. You hit a few situations where if you are exactly at the right time when the project is starting and at the tail end of the definition phase before the architecture is locked in, you can have sales cycles as short as 4 or 5 months. About 9 months would be normal.
If you are selling a new and faster simulator, it should be easy and straightforward to do a benchmark. Wouldn’t this type of product require a redesign of some sort to benchmark?
Because of the decisions we have made in terms of being able to conform to virtually all of the IP protocols, we can actually design with our automated tools a NoC instance pretty quickly that can be basically dropped in to replace a bus. We wind up with the benchmarking phase being fairly quick. The customer does not have to change anything about the chip except the interconnect. The benchmark can be challenging but it can be done reasonably quickly.
What obstacles stand in your way to capture the lion’s share of the $1 billion market you see?
The biggest obstacle right now is that some of the major companies have decided that they are not going to do this in house but the majority market has not yet decided that they are going to outsource this function. I think that this is the biggest barrier to the market bring fairly large. This particular situation has been there with the processor in the early 90s. People said that they would never outsource their processor core. Today almost no one does their processor core. Another one would be logic synthesis. All the major companies had large synthesis projects under way. Today everybody uses Synopsys or Cadence. Once a technology like the NoC gets to a point where it has
horizontal applications where multiple companies can use it virtually a standard product then you end up overwhelming the internal solution but we are kind of at that point where it is becoming obvious that the NoC will do that but the major companies have not made the decision yet.
Is that simply a not invented here syndrome or are their legitimate issues. Software programmers resisted the move to higher level languages because they felt that assembly language programs performed better. Do your tools give you a “better” design or just a design in less time?
With the NoC there are no penalties to pay. The NoC is area competitive and latency competitive with a bus for complex SoCs. You give up nothing by using a network and you actually gain a lot. As you said this song has been played several times before over and over again. The outcome is the same in the end. It will take a couple of years.
Anything to add?
We think the network-on-chip or the interconnect is the next growth area of IP. It is a strategic technology that is emerging that will allow all of the IP industry to grow because one of the big features of network-on-chip is IP reuse. It will become much easier to add, adapt, subtract and test third party and internal IPs. We think that mass adoption of this technology will be very good for the IP industry and for the EDA industry.
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-- Jack Horgan, EDACafe.com Contributing Editor.