July 30, 2007
Nanotechnology – Science vs. Engineering
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| by Peggy Aycinena - Contributing Editor
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The IEEE San Francisco Bay Area Nanotechnology Council hosts a series of meetings throughout the year in Silicon Valley. Most are monthly lunches, pizza and a speaker, but twice a year the Council expands the event to a half or full day.
On July 17th, I attended their day-long summer symposium in an auditorium at National Semiconductor in Sunnyvale, and I wasn’t the only one. There were at least 150 people there, along with compelling topic material and great food. Given the caliber of the speakers on the program – a Nobel Prize winner, a university chancellor, a CTO, a VP of engineering, various directors and research scientists, four VCs and a lawyer – it was impossible not to learn something over the course of the day. In my case, I learned a bundle.
First off, I learned what nanotechnology is. And, yep, if you think the definition is vague, you’re absolutely right. Even Nitin Parekh, IEEE SFBA Nanotech Council Chair, says it’s vague. But why quote the experts? After talking to Parekh and others over the course of the day, I developed my own definition at the symposium and I’ll suggest it’s as good as anybody else’s at this point in time:
Nanotechnology is about anything that’s Small (preferably below 100 nm) that can be manipulated, engineered, or utilized to do something Big.
And Big can be defined many ways – increasing device density on chip, replacing CMOS with something else, creating self-assembling systems, accessing vast amounts of renewable energy and clean water, traveling faster, communicating more, fixing what nature got wrong in the human body and elsewhere, or making gazillions of dollars in emerging markets for alternative energy, new composites, low-power ubiquitous compute platforms, smarter drugs, or cleaner transportation.
So, don’t get hung up on carbon, particles, or tubes, because nanotechnologys far more profound than that.
Nanotechnology is Small. The (potential) applications are Huge.
Voilà. That’s it.
Arno Penzias won the Nobel Prize in Physics in 1978 for discovering the background noise left over from the Big Bang that makes it so hard to hear stuff out across the universe. These days, his interests are far more concrete. As a Venture Partner at NEA, he’s making money investing in “An Energy Agenda for a Sustainable Environment,” which also happened to be the subject of his talk. Here's the Penzias agenda:
Lots of solar power, not just 10-megaWatt power farms, but multiple, teraWatt installations to meet the global need. Every sun-exposed dark spot on any building everywhere is a candidate because the sun’s got to be there anyway. Coat it with photovoltaic materials and use it to generate power.
Every person needs access to light so they can study at night, refrigeration for food and medicine, and clean water – and that’s not water from polluting, fuel-generated purification systems. Biodiesel was a 19th century invention of Dr. Diesel who taught farmers to use local biofuels. We need to use what’s in the neighborhood, and not some fussy fuel that has to be brought long distances.
Sustainable propulsion systems that are evolved way beyond just hydrogen-fueled or hybrid vehicles. We need to get past the need for a battery, so do you really want to do nanotech? Then solve this!
Vibrant and impact-free human settlements that keep the environment clean for all time, which is more than just controlling over-population. People say they don’t want a genetically modified world, but we’ve had 100 centuries of ad-hoc genetic modification. So, stop resisting the improvements that genetic engineering is offering and accept that it’s always been a part of our history. Per Penzias, “Ingenuity is our only inexhaustible resource. The more knowledge we create, the more we know.”
Arno Penzias was a hard act to follow, but Steven Kang, Chancellor at U.C. Merced, was up to the task with an even more straightforward agenda. He wants to combine energy research and nanotechnology to improve the quality of life for the 8 to 10 billion folks we can expect to be inhabiting the planet by the middle of the 21st century. Seems simple enough.
Along with his colleagues at Merced, Dr. Kang has set out to make energy/nanotech the overarching emphasis on the newest campus of the University of California. Got kids? Do they have dreams? Send them to Merced. There they can work on water, solar, and wind power with a “clear trend towards miniaturization,” along side such emerging solar energy gurus as Roland Winston.
By the way, Kang’s talk was not limited to energy issues. He also detailed a boatload of technology initiatives in the life sciences, underway in California and elsewhere, including retinal prosthesis, lungs-on-chip using porous polymeric scaffolds, neuron-FET interface devices, microelectronic arrays for epilepsy control, and bioinformatics for tracing human drug interactions. And, in a nod to the EDA industry, he asked, “ How could we have designed any circuits without SPICE? Similarly, CAD tools can be extended for bioelectronics and biologics circuit for biomimetic systems development to increase quality of life.” Kang said there are huge opportunities to apply EDA
technologies to human-engineered biological circuits. I cheered.
Kang knows CAD because he led the team at Bell Labs that produced the first 32-bit microprocessor, which he noted during his talk could not be perceived as an engineering success: “We didn’t know how to take it to market.” Kang is applying the lesson of that failure to his engineering agenda in nanotechnology and energy at Merced. He said, “No matter what technology we develop, if it’s not cost effective it won’t go anywhere. You’ve got have mass production of these technologies which means low cost.”
[Editor’s Note: Interestingly, both Dr. Kang and Dr. Penzias originally hailed from Bell Labs. What does that tell you about the level of innovation and quality of intellect that rattled around in those legendary halls?]
Sustainable energy and the real world
Following the plenary, the morning session was devoted to sustainable energy technologies. SRI’s Barbara Heydorn laid out a litany of opportunities for applying nanotech to energy, and detailed current use statistics for different energy modalities.
Not surprisingly, the lion’s share of our energy comes from coal, oil, and natural gas – the not-renewable triplets. However, “renewable” sources are not ready to take over. Nuclear energy’s drawbacks are well known, hydroelectric is tapped out and “dams are not admired environmentally,” geothermal provides only a small percent of the world’s demand currently, and biomass, wind, and solar are even smaller contributors. “It’s not realistic to think about replacing oil and gas right now,” Heydorn said.
So, she concluded, let’s use new materials to improve the recovery and utilization of our existing, conventional energy supply. Per Heydorn, we’ve got 40-to-200 years of oil left (depending on efficiencies), 60-to-400 years of natural gas, and 250-to-700 years of coal left. If we use nanotechnology to upgrade the exploration, refining, blending, distribution, and utilization of petroleum resources, we’ll buy the time we need to bring the renewable energy sources online.
Bill Yerkes, CTO at Solaicx, was up next. Yerkes founded Solar Technology International, which was purchased by ARCO and then became the largest photovoltaic manufacturer in the world. Combined with his early years as an engineer at Boeing, it’s not surprising that Yerkes’ talk at the symposium was a gritty, hand-on evaluation of the real-world technology and economics of solar power. He said glass substrates are better than plastic, and certain photovoltaic materials far outperform others.
Yerkes is bullish on solar – nanotech solar cells, in particular – which can survive the rigors of outdoor living, and he thinks concerns about using Cadmium Telluride (toxic when ignited) is nonsense (the required temps are too high to be of concern). He also has powerful opinions about a host of other solar materials, companies, and people involved in the industry. He ended, “Each technology [I’ve described] is going down the trail due to the good old free market economy. Everybody making solar cells is rapidly going forward, and the costs [and rewards] are being driven by the engineers!”
The morning ended with Guido Radaelli, Vice President of Engineering at Aurora Biofuels, talking about energy production from biomass using algae grown on an industrial scale – or even harvested from the North Sea. It was pretty interesting, although I suspect the neighbors prefer not to be downwind from the biofuel algae farm when its ablooming.
The hands-down most dynamic speaker of the day was on during the noon hour. Ira Ehrenpreis, General Partner and head of the Cleantech Investment practice at Technology Partners, is a lawyer, a VC, and a terrific speaker. Per Ehrenpreis, clean technology has captured the imagination of the nation and the world and, as of 2006, VC investment in green business opportunities has now surpassed semiconductor investment worldwide. Wow.
“Clean energy is now the greatest economic opportunity of the 21st century,” he proclaimed, and dared his audience to keep up as he sped through a great set of slides:
Transportation – solar, ethanol, GM, hydrogen, Tesla Motors, batteries; Solar – silicon shortage, lower cost per Watt, FirstSolar, Renewable Energy Corp.; Corporate Interests – Alcoa, IBM, 3M, WalMart, Google, GE; Global Players – Brazil, Saudi Arabia, Germany, China; Public Interest – social responsibility, innovation, health.
Ehrenpreis invoked Al Gore, the antiquated power grid, water shortages, economists, security exports, entrepreneurship, and LOHAS [Lifestyles of Health and Sustainability]. He said Green is far more than the New Black; it’s the New Red, White, and Blue.
As he leaped from the stage and strode out of the room, he threw out his email address and invited [challenged] everyone to contact him. It was exhausting – and garnered a standing ovation.
Clean water and good jobs
Following lunch, the afternoon session was devoted to clean water and was very technical. Dr. Olgica Bakajin, a Fellow at Lawrence Livermore Labs, described in detail a novel method for assembling carbon-nanotube array filters that have real promise in water purification. Dr. Mamadou Diallo, Director of Molecular Environmental Technology at Cal Tech, talked about an equally novel dendrimer nanotechnology water treatment concept that he’s in the process of commercializing.
Then, Dr. Jeonggi Seo, Research Scientist at Xerox PARC, explained his high-throughput, continuous flow, membrane-less water filtration system. It’s a maze-like micro device that garnered more questions than the Bakajin and Diallo talks combined. I’m guessing it’s because there was more skepticism about Seo’s proposal than about the other two proposals combined. Nonetheless, in addition to their own technologies, all three speakers gave detailed and informative explanations of the current state of the art in water purification worldwide, and it ain’t pretty.
The final session of the day was an hour-long panel that could just as easily have been plunked down in a conference about EDA. Moderated by Eric Wesoff, Publisher of the Venture Power Report at Greentech Media, the topic of the discussion was “Career Opportunities and Requirements.” Panelists included Foothill College Nanotech Professor Robert Cormia, X/Seed Capital’s Bala Padmakumar, Melinda Richter, Executive Director at the San Jose BioCenter, and Anthony Waitz, Managing Director for Quantum Insight.
The conclusions of the group were not unique to the nanotechnology sector. You’re best off if you’ve got a PhD, but if you come into the industry with a doctorate don’t presume you’ve also got the gift or skillset required to start a business or keep it up and running. Get help from accountants, lawyers, investors, and other such resources that abound in Silicon Valley.
Other countries are providing huge financial incentives for their brain trust to innovate and thrive back home. The ones who are getting educated there are staying there, and the ones who are getting educated here are going back. The U.S., and the Bay Area, in particular, cannot ignore the threat of a brain drain and has got to get to work changing things for the better here – everything from visas, to venture capital, to partnerships between government, industry, and academia to promote the environment for innovation and financial reward.
Finally, we’ve got way too many scientists and not enough engineers to bring the explosion of good ideas in nanotech to market. The ratio right now in our educational system is 10 scientists for every engineer, but it should be 1 scientist for every 10 engineers. Again, let’s get this fixed ASAP.
And, don’t take offense at the ongoing tension between science and engineering. It’s the single most important factor in innovation and we need to encourage it to grow. Per the panelists at the nanotech symposium:
Science vs. Engineering = Nanotechnology + Success
The IEEE San Francisco Bay Area Nanotechnology Council would love to see you at their next event at lunchtime on Tuesday, August 21st, at the SEMI Headquarters in San Jose. Go to
News over the last several weeks
Accellera announced the Board of Directors elected 14 corporate member companies to its Board for the 2007/8 membership year, including companies from the user and supplier communities. On the list: ARM, Cadence Design Systems, Denali Software, Freescale Semiconductor, IBM, Intel, Magma Design Automation, Mentor Graphics, Nokia, Novas, Rockwell Collins, Sun Microsystems, Synopsys, and Texas Instruments. Shrenik Mehta, Accellera chair, is quoted: "It is advantageous that we have a balance of semiconductor, IP, systems houses, and EDA companies represented on our Board."
Altera Corp. announced what the company calls “the FPGA industry's first full-compliance support for high-performance DDR3 memory interfaces. Under the newly ratified JESD79-3 JEDEC DDR3 SDRAM Standard, Altera's Stratix III family of FPGAs provides designers with the high-performance and low-power benefits of DDR3 memory
[The] applications process large amounts of data that require quick and efficient access for optimum memory performance. Compliance with the JESD79-3 JEDEC DDR3 SDRAM standard meets the 1.5V, low-power supply voltage of DDR3 memory, which provides about a 30 percent system power reduction, faster performance and increased memory density for next-generation
systems, while maintaining software compatibility with existing DDR applications.”
Altera also announced IP support for the EtherCAT protocol from the EtherCAT Technology Group. The companies says the IP was previously qualified on Altera’s Cyclone II devices, and now targets Altera's new low-cost, low-power Cyclone III FPGAs. The company also announced FPGA-based support for various Ethernet communications protocols, including ProfiNet, Ethernet/IP, Modbus-IDA, EtherCAT, SERCOS III Interface, and Ethernet Powerlink: “IP cores for these key communications protocols can now be implemented on Altera's Cyclone series FPGAs. The Industrial Ethernet IP cores enable designers to implement any of the standards on a single board.”
Arasan Chip Systems announced “USB IP core sales are soaring as a result of its new Emerging Markets Program operating in Asia. Arasan is gaining market share rapidly by offering China customers a special set of incentives on Silicon IP along with the critical elements of a total USB solution that they require to efficiently integrate USB into a SoC/ASIC. Arasan’s ability to provide onsite support and integration services in China and Taiwan have set it apart from the pack.”
Athena Design Systems, announced DSM Solutions as Athena’s exclusive sales representative in Japan.
Atrenta announced Mike Gianfagna has been named Vice President of Marketing, reporting to President & CEO Ajoy Bose. Gianfagna has 36 years in semiconductor and EDA, most recently as VP of Design Business at Brion Technologies, an ASML company, and President and CEO at Aprio Technologies. Previously, he worked at eSilicon, Cadence Design Systems, and Zycad, and was in management at GE and Harris Semiconductor. Gianfagna began his career at RCA Solid State as part of the team that launched the company's ASIC business in the early 1980s. He has a BSEE from New York University and an MSEE from Rutgers University.
Cadence Design Systems reported Q2 2007 revenue of $391 million, an increase of 9 percent over the $359 million reported for the same period in 2006. On a GAAP basis, Cadence recognized net income of $60 million, compared to $30 million in Q2 2006. Using this non-GAAP measure, net income in Q2 2007 was $91 million, as compared to $73 million in Q2 2006. For Q3 2007, the company expects total revenue in the range of $395 million to $405 million, and for the full year 2007, the company expects total revenue in the range of $1.585 billion to $1.635 billion.
Cadence Design Systems also announced that Toumaz Technology used Cadence’s Virtuoso AMS Designer Simulator for mixed-signal simulation in the verification of a recently developed product, Sensium, “an ultra low power sensor interface and transceiver platform for a wide range of healthcare and lifestyle management applications.”
Meanwhile, Toumaz Technology announced its Sensium Platform Integrated Development Environment Resource (SPIDER). The company says the development kit includes two Sensium hardware development boards for the sensor transmitter and the receiver base station, respectively, Keil 8051 compiler, and JTAG debugger.
Cadence announced, as well, that CES Design Services, the Technology Center for Chip Design at Siemens IT Solutions and Services PSE, is using Cadence assertion-based verification IP (ABVIP). The companies say the technology center serves both the Siemens group and non-Siemens customers.
Finally. Cadence announced a “silicon validation collaboration” with Jazz Semiconductor working on Cadence’s RF Design Methodology and AMS Methodology kits. Per the Press Release: Jazz supports design and methodology kits based on the Cadence Virtuoso’ custom design platform
Jazz's Analog-Mixed-Signal Process Design Kits (JAMS PDKs), based on its 0.18-micron Silicon Germanium (SiGe) process (SBC18), now support the Cadence technology and usage models
with the intent to extend the collaboration to the Jazz SiGe 0.13-micron process family.”
Calypto Design Systems announced Doug Aitelli has been named Vice President of Worldwide Sales. Aitelli has 20+ years’ EDA sales and sales management experience, most recently as Director of Global Accounts at Magma. Previously, he held various sales and sales management roles at Synopsys, Quickturn, and Racal-Redac/HHB Systems.
Carbon Design Systems announced a program to offer customers of Tenison Design Automation’s VTOC products an easy migration path to Carbon’s family of model generation solutions. Per the Press Release: “The Tenison Migration Program is a limited-time offer that includes free use of Carbon’s tools, custom integration software, and tailored services to speed the migration in exchange for signing on with Carbon. The program runs now through October 31, 2007.” “Our migration program is designed to give Tenison’s customers peace of mind that they will have a fully supported solution to continuously meet their design needs,” remarks Scott
Seaton, Carbon’s vice president of sales. “We’ve previously been successful in migrating multiple Tenison customer’s to Carbon in a couple weeks each.”
Cimmetry Systems, a subsidiary of Agile Software, recently acquired by Oracle, announced AutoVue v.19.2, which “solidifies Cimmetry's presence in the electronics and high-tech market with new EDA centric product offerings to address the specific requirements of PCB design and contract manufacturing.” Does that put Oracle in the EDA market?
Dolphin Integration announced a high-resolution measurement ADC, that the company says is for SoCs for low frequency sensor applications and MEMS: “SensADC-16.02 covers optimally the needs of measurement applications with stringent requirements in terms of noise management: blood pressure sensors or weight scales for medical markets, as well as all kinds of high-resolution wireless sensors.”
EEMBC, The Embedded Microprocessor Benchmark Consortium, announced that Cypress Semiconductor has joined EEMBC as a member of the consortium’s workgroup focused on developing multi-core and system-level benchmarks for automotive and industrial applications.
EMA Design Automation announced it now offers SymXpert from Perception Software: “As large-pin-count components are more frequently used in PCB designs, the creation of schematic symbols for new parts has become increasingly time consuming and error prone.
SymXpert automates the symbol creation process by eliminating manual data entry and simplifying pin data verification [with these] features: intelligent content extraction, data validation, rule-based graphics and pin arrangement, and template driven generation.”
FSA announced that Dwight Decker, non-executive chairman at Conexant Systems, has been named FSA Chairman. Sanjay Jha, who has been in the role for three years, will assume Decker’s role as vice chairman. The rotation in leadership roles is effective immediately. Decker has served on FSA’s Board of Directors for six years and has been FSA vice chairman since 2004. Prior to Conexant, Decker was senior vice president of Rockwell International and president of Rockwell Semiconductor Systems.
IMEC announced it has expanded its 3D packaging research program to include system design methodologies. Per the Press Release: “Both the technology and design sub-programs will be based on actual system requirements and closely coupled
IMEC also added a design technology sub-program in which system architectures will be revised. By involving other companies such as e.g. fabless companies and EDA companies, IMEC aims to develop 3D architecture methodologies enabling 3D optimization across heterogeneous technologies
In the future, IMEC intends to extend its 3D system technology program with a 3D IC program which will investigate wafer stacking for interconnects at the
IC local interconnect level.”
In related news, Amkor Technology , and IMEC announced a 2-year collaboration agreement “o develop cost-effective, 3D integration technology based on wafer-level processing techniques.”
Meanwhile, IMEC also announced progress on high-index 193-nanometer immersion lithography, double-patterning schemes for 193-nanometer water-based immersion lithography and extreme UV (EUV) lithography. Luc Van den hove, Executive Vice President and COO at IMEC, is quoted: "Over the last year, we've made significant progress in the three litho approaches we are investigating within our advanced lithography program. Driven by the needs to quickly develop 32-nanometer processes for memory applications and based on the promising results, we are quite confident that double patterning will be taken up as an intermediate solution for 32nm half pitch before a single exposure solution
is ready for production.”
Innovative Silicon (ISi)) announced it has joined the Cadence OpenChoice IP Program, program “designed to ease the process of integrating IP such as ISi's Z-RAM into SoC designs.”
Jetway Security Micro, a security products company based in China and Elliptic have signed a license for Elliptic’s asymmetric security engines. The companies say this will “permit Jetway to better serve the emerging Asian and world markets for security incorporating high performance public key algorithms. The two companies have also agreed to collaborate on a long term basis to tailor the engines to the precise needs of the target markets and applications specified by Jetway.”
Kilopass Technology announced new XPM (Extra Permanent Memory) IP for 90-nanometer general purpose and low-power designs: “With the availability of the XPM-90G and XPM-90LP families, Kilopass [is] the first memory IP supplier to announce availability of a high density NVM technology on both general purpose and low power 90-nanometer advanced geometries.”
Knowlent Corp. announced its Opal TBE test bench development and simulation control environment, which the company says supports all circuit simulation technologies from Synopsys. Per the Press Release: “Opal TBE will provide Synopsys users with a graphical user interface for analysis, characterization and verification of complex analog/custom blocks used in SOC designs implemented in the latest nanometer silicon technologies
Synopsys' analog and mixed-signal design customers have the advantage of a complete test bench development and simulation control environment launching simulations and post processing simulation results in a structured spec-driven
Lightspeed Logic announced new Reconfigurable Logic IP for 65- and 45-nanometer process nodes. The company says, “Because of the regularity provided by the tiling structure and the full knowledge of the immediate neighborhood of the tile, Lightspeed Logic, in partnership with its customers, can fully deploy OPC/RET technologies without facing the typical computing limitations associated with standard cell structures
Both lithography-related variability and stress-related variability are substantially reduced and the timing modeling does not need to accommodate overly pessimistic guardbanding.”
Magma Design Automation announced that Toshiba has adopted Magma's FineSim Pro and FineSim SPICE circuit simulation products, and is using the tools on “its most aggressive designs to achieve superior performance and accuracy.”
MathStar, Inc. announced that Nuvation, an electronic design services company, has joined the Certified Design Center (CDC) program. The companies say, “Members of MathStar's CDC program have been extensively trained to provide professional services to designers who are migrating to MathStar's Arrix family of field programmable object arrays (FPOAs).”
Mentor Graphics announced a collaboration with the RV-VLSI Design Center in Bangalore. Per the Press Release: “Under the auspices of its Higher Education Program, Mentor Graphics will provide the Center with leading-edge design tools for classroom instruction and academic research, by donating a complete suite of EDA tools. This donation, worth over $20 million, will enable students to gain proficiency in VLSI design and other emerging nanotechnology challenges such as design for manufacturability.”
MOSAID Technologies announced an agreement to sell “certain assets” of its IP product development business to Synopsys for approximately $15 million in cash. The agreement is expected to close in August 2007, with the payment subject to a $2 million holdback for one year. Synopsys says will hire MOSAID’s IP engineering team. Theres additional detail in the Press Release: “Synopsys has agreed to purchase the assets and intellectual property associated with MOSAID's Double Data Rate (DDR) memory controller and Phase Locked Loop (PLL) product families. In connection with the transaction, Synopsys will also receive an exclusive license to certain patents and
pending applications associated with MOSAID's current memory controller and PLL product lines.”
John Lindgren, President and CEO at MOSAID, is quoted: "With the sale of our Semiconductor IP assets to Synopsys, we will move forward as a pure-play intellectual property company focused on patent licensing and advanced memory R&D. Our Semiconductor IP group has successfully developed and sold best-in-class technology and products to the global semiconductor industry. We decided that these assets would perform better in the hands of an industry leader with complementary product lines and the scale to succeed in a competitive market, allowing us to concentrate on our core business."
ProDesign announced CHIPit Iridium Edition version 5. Per the Press Release: “V5 gives ASIC and SoC design engineers unprecedented speed and flexibility to verify and debug their designs
It can be scaled from 1 up to 6 FPGAs Xilinx Virtex-5 FPGAs and handles ASIC design capacities up to 8 million ASIC gates.”
Sequence Design announced a collaborative licensing agreement with Faraday Technology Corp. to bundle Sequence’s PowerTheater tool suite with Faraday’s Design Kit for its U.S. customers. Per the Press Release: “Once the designers are satisfied with the trade-off of performance, area, and power, they can [migrate those] power techniques into the synthesis and place & route stage with Faraday's
PowerSmart design flow methodology.”
Solido Design Automation announced integration of its new transistor-level statistical design and verification technology with Cadence's Virtuoso Analog Design Environment and Virtuoso Spectre Circuit Simulator. Per the Press Release: “Solido is currently working with customer partners and will announce its transistor-level statistical design and verification tool suite in the next few months.”
Synopsys announced that NetLogic Microsystems used Synopsys’ NanoTime transistor-level static timing analysis tool to tape out its “next-generation knowledge-based processor
[The] 65-nanometer processor was optimized for high-performance packet processing and low power consumption.”
Synopsys also announced that ProMOS Technologies is using Synopsys' Proteus OPC software as the company’s production standard for advanced process technologies. Per Peter Zhao, senior director for R&D at ProMOS: "Using Proteus, we achieved the most accurate OPC correction, as well as impressive cost-of-ownership improvements, at the advanced technology node."
VaST Systems announced $12 million in Round D funding led by ZenShin Capital, with participation from previous investors Allen Buckeridge, Foundation Capital, and Mohr Davidow Ventures. Takeshi Mori.
Valens Semiconductor Ltd. announced a $7 million series A round of equity financing, led by Genesis Partners along with Magma Venture Partners. Not surprisingly, Eyal Kishon of Genesis Partners and Eitan Dekel of Magma Venture Partners will join the Valens Board of Directors. In addition, Yossi Kofman will join the company's advisory board.
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-- Peggy Aycinena, EDACafe.com Contributing Editor.