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July 02, 2007
EDA Inside: From Late Republic to Imperial Zone
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

When the Senate fell upon Julius Caesar in 44 B.C.E., ostensibly they did it to save the Republic. Unfortunately, the Republic was already long gone, having fallen victim to the excesses of power and consolidations of influence that had characterized the nation state for well over a generation at that point.

When the publishing industry fell on Richard Goering in 2007 C.E., ostensibly they did it to streamline coverage to more effectively serve the Republic of EDA. Unfortunately, the EDA Republic was already long gone, having fallen victim to the excesses of power and consolidations of influence that had killed the innovation state in EDA for well over a process generation at that point.


You think I’m overstating the situation? Do you know how many people have suggested to me, since the news broke on June 14th, that Richard Goering’s dismissal was tantamount to the Death of EDA? But is it really the Death of EDA, or the Death of the Republic of EDA? What is really going on when the single most influential journalist in the industry is laid off?

Here’s one spin on the story …


Your tools made chips denser and faster, which made data aggregation, manipulation, and transport more efficient, which enabled the PC and the Internet, which facilitated globally distributed design teams, which fed into the ever-present desire to reduce labor costs by additional outsourcing from higher overhead and direct cost economies to lower overhead and direct cost economies to bring down the cost of design, which threatened the historical design communities in North America, Europe, and Japan. Meanwhile, the tech boom turned to tech bust as the losses of 9/11 were layered on top of the unraveling of injudicious over-investments in dot.com and telecomm and Y2K, which led to
precipitous declines in revenue for EDA vendors trying to sell into a struggling customer base, which was itself selling into a struggling customer base, so that everybody’s bottom line declined sharply, which led to fewer discretionary dollars for things like PR and advertising – particularly print advertising – which led to fewer ad pages and lower revenues for publishers and further motivation to put content, ads, and marketing campaigns online, because the cost of electrons appeared to be less than the cost of trees, ink, and mailmen, which was possible because the PC and Internet were being enabled by denser, faster chips.

But, the revenue from electron-based content, ads, and marketing campaigns was lower because the ROI for such spending was even more obscure to the advertisers, so there was even less money to be earned in publishing, so the publishers had even fewer discretionary dollars to spend on paper, ink, mailmen, and editors. And editorial heads began to roll. And the list of distinguished journalists who found their jobs and/or publications cancelled out from under them began to grow alarmingly, and the PR community had less and less access to editorial platforms for their clients. But then, even after the end-customers and their vendors and their vendors’ vendors – the EDA guys
– started to recover with the uptick, particularly with the ferocious onset of worldwide demand for consumer electronics, the publishers could not recover from the irreparable damage that had been done to their paper-and-ink business models, and all the while, because of your faster, denser chips, the Internet got even faster and denser – but not necessarily more lucrative to the publishers – and the whole thing spiraled even further out of control, exacerbated by more and more self-publishing pundits throwing themselves into the online fray.

And the Big EDA vendors looked out across this shifting landscape, and added into their calculus the fact that faster, denser chips were harder to design and more expensive to manufacture, so the number of ASIC starts was beginning to decline – precipitously – so the customer base was beginning to shrink, and those same EDA vendors would not or could not innovate fast enough to satisfy that shrinking customer base to the extent needed to inspire the market to grow, or investments or stock valuations to climb, and so they decided to work even harder to corner the market with their suite of offerings. Meanwhile, many customers began to consolidate their R&D dollars through cross-corporate collaborations and hence began to revisit the ancient art of making their own tools in-house, and even worse, started to turn to other sources such as aggressive fabs and mega IP vendors for aid and assistance, so that the EDA vendors became even more obsessed with reaching out to just their own users and their own legacy markets – as well as to those same aggressive fabs and mega IP vendors – and worked even harder to guarantee lock-in among their customers, and increasingly concluded that their declining discretionary dollars were badly spent on industry-wide conferences and print ads, or even online ads, and were better spent on focused user conferences,
focused online newsletters generated by their own in-house staff, and bigger compensation packages to reward their leadership for their pain and suffering and business savvy in a transient world.

More and more, the EDA vendors began to ask why they should be forced to support media outlets or conferences where independent-minded journalists continued to insist on saying whatever they wanted and overtly/covertly continued to resist the relentless shove coming from their publishers in the direction of ’sponsored editorial,’ the journalists clearly and continuously refusing to acknowledge their moral debt to the financially-strapped advertisers and economically-crippled publishers. And the thing spiraled even further out of control. Until one day in June of 2007, the Internet and the mess and the outsourcing and the in-housing and the over-investment and the
under-returns and the shifting sands and the crippling and the spiraling and the madness and the pain and the suffering and the consolidation reached a climax and the unthinkable happened. The legendary Richard Goering was laid off, the PR community, starved for access to editorial platform, lost yet another long-cultivated conduit to that platform, a cry of collective pain went up, and …

… the Republic of EDA died.

Although, in truth, it had died quite some time ago. Already in the era of the Late Republic, the Big Three in EDA owned 50 percent of the market. Now in the Imperial era, the Big Four own more than 80 percent of the market. Good news for some constituencies, but not so good for others. More than a Greek tragedy sheathed in a Roman toga, the whole saga is downright Elizabethan, particularly for jettisoned editors:

“Et tu, Bro?”


News from in and around DAC …

It is my intention next time here in EDA Weekly to complete my DAC report – assuming EDA has not died in the interim. Meanwhile, among recent news items in EDA you’ll find three acquisitions, three endorsements, a conference, and the end of a rumor.

Mentor Graphics acquired Sierra Design (discussed in EDA Weekly on June 18th), Synopsys acquired ArchPro (see below), ARC acquired Tenison Technology EDA (also see below) and VaST announced endorsements from LSI, Freescale, and Infineon (below, as well).

On June 14th, 160+ technologists attended the “Logic NVM 2007 – Inside Tomorrow’s Consumer Electronics” conference in Silicon Valley, which focused on embedded non-volatile memory in applications such as mobile phones, MP3 players, USB controllers, and Flash drives. Speakers included eSilicon’s Jack Harding talking about “Smaller, Faster, Cheaper, Better” and iSuppli’s Jordan Selburn. The panel discussion included folks from Chartered, eMemory, Kilopass, Sidense, and Virage Logic. FSA, Chingis, Elliptic, Intersil, and SiTime made presentations as well. Happily, the whole event is now
available online at

Finally, the DAC-week rumors quoting “unnamed sources” that Cadence was in buy-out discussions with KKR and/or The Blackstone Group were put to rest by way of yet more rumors during the week of June 18th, also quoting “unnamed sources,“ that all discussions were off. Undeterred, Blackstone went public on June 22nd in the largest IPO in North America in the last 5 years. Wow.


EDA Inside …

VaST Systems announced the LSI Networking group is experience performance improvements on new devices using VaST’s virtual prototyping products. LSI says VaST’s tools are now the company’s “preferred” way of doing architecture analysis and pre-silicon software development.

VaST also announced development of a virtual processor model of Freescale's e200z6 core built on Power Architecture technology. Per the Press Release: “This development is part of VaST's Universe Initiative structuring collaborative development of high-performance and accurate models of semiconductor IP for pre-silicon software development.”

VaST also announced the company reached an agreement with Infineon Technologies that will expand the use of VaST products at Infineon, and include distribution of Virtualized Hardware to Infineon customers. Per the Press Release: “VaST solutions are now being expanded to Infineon Automotive and Communication business units and their respective key customers.” VaST CEO Alain Labat is happy: “Infineon has pioneered the use of virtual prototyping technology with the goal of providing virtualized hardware to their customers. Now this Virtualization across the supply-chain is a reality.”

Virage Logic Corp. announced participation in the first Armenia Technology Congress (ArmTech Congress 2007) to be held July in San Francisco. Per the Press Release: “The company boasts a significant presence in the Southwest Asian nation.” President and CEO Dan McCranie will give a keynote and Vice President and Chief Scientist Yervant Zorian will serves as Program Chair.

VSIA announced that ChipEstimate.com and Design & Reuse have added "QIP Metric Rated" as a search field to their databases, “enabling users to search for IP that has been qualified against the VSIA QIP (Quality IP) Metric.” In addition, Mentor Graphics says it has qualified all its SIP cores through the QIP Metric and users can now search both portals for Mentor SIP cores.

Texas Instruments announced plans to integrate a high-k value material in its 45-nanometer chips. TI says it will reduce leakage by more than 30x per unit area as compared with SiO2 gate dielectrics. TI CTO Hans Stork is quoted: "TI has been at the forefront of Hafnium-based research and development for nearly a decade, and we're confident that our high-k choice overcomes the technological hurdles faced through continued digital CMOS scaling and the transition to smaller process geometries."

Teseda Corp. announced its ScanXY, described as “the first in the Teseda Diagnostic Manager Series software products … ScanXY allows engineers to quickly link structural test data mismatches to their physical domains. The viewing capabilities of ScanXY show the XY location where test failures and subsequent ‘hot spots’ are taking place. ScanXY runs without third party intervention, either independently or in conjunction with the Teseda WorkBench software.”

Tensilica announced that two Korean universities have licensed its Xtensa configurable processor. The Center of System on Chip Design Technology of Seoul National University is using the Xtensa processor in the classroom and has announced their third annual SOC design contest, which will, for the first time, accept designs that use Xtensa processors. The Korea Advanced Institute of Science and Technology has licensed the Xtensa configurable processor to develop multimedia SOC designs.

TEA Systems announced its Vector Raptor overlay product, which the company says is “designed to address the unique problems now being introduced by double patterning and sub-45-nanometer process nodes. Double patterning introduces single-layer registration errors that originate during reticle manufacturing, can be amplified during wafer processing, and vary with changes in exposure of the individual feature. Current matching and modeling techniques cannot accurately deconvolve the sources of these errors that include a whole new family of overlay and feature-size product yield loss factors. Vector Raptor provides an object-oriented, fully-interactive graphic
interface for advanced control of overlay/registration with matching to any format feature-profile or film data.”

Target Compiler Technologies announced improvements to its Chess/Checkers tool suite for the design of ultra-low power SoCs, including multi-faceted support for parallelism as well as RTL-level optimizations. Per the Press Release the enhancements address a current need: “While there is an ever growing quest for more functionality and higher performance in today’s SoC designs, there is an even more pronounced need to minimize energy consumption – either to prolong battery life or to reduce operating temperatures.”

Synopsys announced that NEC Electronics Corp. has adopted Synopsys' PrimeTime advanced on-chip variation (AOCV) analysis technology for NEC’s SoC designs.

Synopsys also announced that Solarflare Communications, Inc. taped out a 90-nanometer 10-gigabit Ethernet controller using the Synopsys IC Compiler tool. Solarflare says IC Compiler reduced design time and resulted in smaller overall area for the chip and “10-to-20 percent power reduction in several critical blocks.”

Synopsys also announced the DesignWare VPXA3 Virtual Platform for smartphones, hand-held, and CE devices that use Marvell PXA3xx XScale technology next-generation application processor. Per the Press Release: “The DesignWare VPXA3 Virtual Platform is now available to engineers who want to evaluate and use the Marvell PXA3xx in their portable and handheld devices.”

Synopsys also announced work with UMC to port the Synopsys DesignWare USB 2.0, PCI Express, SATA and XAUI PHY IP to UMC's 90-nanometer and 65-nanometer technologies.

Synopsys also announced that it has acquired ArchPro Design Automation, a vendor of power-management tools for verification of such things as power gating, substrate biasing, dynamic voltage, and frequency scaling. Terms of the deal were not announced. ArchPro Chairman and CEO Pratap Reddy is quoted in the Press Release: "ArchPro's silicon-proven power management technologies are a natural fit with Synopsys' advanced verification platform. The combination of ArchPro's technologies and Synopsys' market- leading verification solution will enable designers to successfully meet their power goals." In addition, Manoj Gandhi, Senior VP and GEM for Synopsys’
Verification Group, is quoted: "Adoption of sophisticated power management techniques is increasing rapidly in the industry. This acquisition will help Synopsys continue to address customers' needs beyond our SystemVerilog leadership and deliver state-of-the-art power management verification technologies."

STMicroelectronics announced its 45-nanometer CMOS design platform for SoCs. Per the Press Release: “ST's innovative low-power process option with multiple threshold transistors cuts the silicon area by half compared to designs implemented in 65-nanometer technology … The process improves speed by up to 20% or reduces leakage current by half while in operation, and, in retention mode, reduces leakage current by several orders of magnitude.”

STMicroelectronics also announced new motion sensors with a digital-output 2-axis linear accelerometer. Features include click and double-click recognition, motion-detection/wake-up, and high-pass filters that make it easier “to associate simple tapping gestures with user commands, such as opening a document or selecting an option from an application menu. Similarly, a ringing mobile phone can be muted with a single tap, without taking the phone out of the pocket.”

Sidense and Chip Estimate announced that Sidense has joined the Chip Estimate Prime IP Partner Program. Per the Press Release: “As a Prime IP Partner, Sidense is enabling centralized access to information about the company's embedded, non-volatile memory (NVM) SiFuse and SiPROM IP cores at ChipEstimate.com.”

Renesas Technology Corp. announced an “extremely high-performance transistor technology with low-cost fabrication capability for microprocessors and SoC devices at the 45-nanometer generation and beyond. The new technology improves the performance of CMIS transistors with a proprietary Renesas-developed hybrid structure ... The new semiconductor manufacturing technology has a p-type transistor with a titanium nitride (TiN) metal gate and an n-type transistor with a conventional polysilicon gate. However, the new p-type transistor uses a 2-layer gate structure instead of a single-layer gate for better control of the threshold voltage.”

MOSAID Technologies announced that Roger Stricker and Ted Galanthay will serve as consultants to the company “on patent licensing and other matters related to asserting the Company's intellectual property rights.” Michael Vladescu, MOSAID Vice President for Licensing and IP, is quoted: "Before their current consulting roles, both Roger and Ted rose to senior positions with multinational companies where they generated significant licensing revenues and dealt with a wide variety of licensing and litigation matters."

MOSAID also announced it has licensed the company's patent portfolio to Etron Technology, Inc. Under the terms of the agreement, Etron has licensed MOSAID's patent portfolio for a 5-year term. Financial details of the license agreement were not disclosed.

Happily, Nicky Lu, President and CEO at Etron, is quoted as saying: "Etron believes in the importance of protecting intellectual property as a key factor in participating in global markets."

Mentor Graphics announced it is supporting its iSolve emulation-based IP products for ARM. Per the Press Release: "Mentor’s iSolve products take full advantage of the high-performance system verification capabilities of Mentor’s recently announced Veloce hardware assisted verification platform… The iSolve family of vertical market solutions now includes two new ARM processors, the ARM11 MPCore multiprocessor and the ARM1176JZF-S processor."

Mentor Graphics also announced success in an AUTOSAR demonstrator project with Volvo Trucks. Per the Press Release: "AUTOSAR is the standards organization working to create an open standard for automotive engineering architecture. Mentor is a premium member of AUTOSAR. The project entailed completely redeveloping an existing climate control system using AUTOSAR technology. The goal of the project was to increase the knowledge about AUTOSAR within the Volvo group as well as evaluate commercial viability of the AUTOSAR concept itself."

Magma Design Automation announced an "enhanced statistical static timing analysis (SSTA) methodology that is tuned to TSMC's 65-nanometer process. The methodology is based on Magma's Quartz SSTA and expands the capabilities offered in TSMC Reference Flow 7.0. This advanced methodology now supports global (inter-die) and random (intra-cell) process variations, composite current source (CCS) models, statistical leakage analysis and statistical optimization as validated in TSMC Reference Flow 8.0."

Magma also announced that TSMC selected Magma’s QuickCap NX for parasitic extraction at 130, 90, and 65 nanometers. Per the Press Release: "[TSMC] designated [QuickCap NX] as the deviation comparison target for RC extraction tools on special pattern structures and real design samples such as critical nets." In related news, Magma also announced that TSMC has qualified Magma’s Quartz RC extraction technology files at similar process nodes.

Kilopass Technology and Data I/O Corp. announced a partnership to provide "affordable, mass-production programming solutions for all Kilopass XPM IP products … Using traditional Automated Test Equipment (ATE) to program embedded Non- Volatile Memory (NVM) in an SoC is very capital intensive, adding to the device's unit cost … The partnership aims at ensuring quality and reducing manufacturing cost."

Kilopass also announced that Jeannie Duncanson has been named CFO. Duncanson has 20+ years’ experience in high tech, most recently at SGI. Prior to SGI, she was CFO and Co-founder of Kasenna, a venture-backed software company. She has a BS in Business Administration from Loyola University and an MBA from the American Graduate School of International Management.

IMEC and IMEC-NL (at the Holst Centre) say they have fabricated an "energy harvester to generate energy from mechanical vibrations by using micromachining technology. Output power as high as 40 micro-Watts was obtained, thereby achieving the range of required power for wireless sensor applications. The harvester comes with a model that can be used to optimize the device during design. Energy harvesters, which transform ambient energy into electrical energy, are of great value for situations where batteries cannot be easily replaced. A typical example is autonomous sensor networks that are spread over large areas or placed in locations that are difficult to access."
Very cool!

IMEC also announced an agreement with Silterra Malaysia for a joint development project to create a foundry-compatible 90-nanometer CMOS process technology with "intention" to scale to 65 nanometers. At the same time, the organizations say a 110-nanometer derivative will also be developed. The collaboration is an extension of a join project conducted at130 nanometers.

IBM announced it new Cu-45 ASIC that utilizes SOI technology, which IBM says, "historically [has only been used] for high performance microprocessors – into communications, consumer and other major market segment … The Cu-45HP ASIC offering is the first-ever product application of a new generation of embedded dynamic random access memory (eDRAM) implemented in Silicon-on-Insulator (SOI) technology – an innovation introduced February 2007 at the International Solid State Circuits Conference (ISSCC) … IBM’s new 45nm eDRAM technology implemented in SOI can dramatically improve on-processor memory performance in about one-third the space with one-fifth the
standby power of conventional SRAM (static random access memory)."

The Fab Owners Association announced formation of a semiconductor Group Purchasing Organization (GPO), to be called FOA Purchasing Partners, Inc.(PPI). Per the Press Release: "PPI will be the official group purchasing organization of the FOA and its device maker members, providing procurement services, including aggregation of demand, contract negotiations and contract management for semiconductor manufacturing consumables. L.T. Guttadauro, FOA Executive Director will also serve as President of PPI."

eSilicon Corp. says it has launched the eSilicon HardCore Program, "which offers a broad portfolio of pre-hardened ARM processor cores. The Program, which will also offer cores from other IP suppliers, provides easy-to-integrate hard macrocells that are optimized for performance, power or area, reducing design risk while enabling faster time-to-market."

Denali Software announced that its MMAV verification IP software has been applied by SST to simulate the PSRAM features in its combination flash memory devices.

Clear Shape Technologies announced that TSMC has qualified Clear Shape’s InShape for its 45-nanometer process technology and included it in Reference Flow 8.0, and has included the tool in TSMC’s Reference Flow 8.0 as a lithography analysis tool.

Cadence Design Systems and TSMC announced a TSMC 65-nanometer RF process design kit (PDK) compatible with the new Cadence Virtuoso design platform, and downloadable RF, analog and mixed-signal design-flow demonstration packages for wireless designers.

AMI Semiconductor and MagnaChip Semiconductor announced that MagnaChip will manufacture AMI's 0.35-micron SmartPower technology, and the companies will continue joint development of ULP (ultra-low power) technology.

Altos Design Automation Inc. announced the TSMC Reference Flow 8.0 includes Altos’ statistical timing model generator Variety. Per the Press Release: "Reference Flow 8.0 supports 45-nanometer process technology … The new 8.0 flow includes support for the creation of libraries to enable statistical static timing analysis (SSTA). The collaborative effort between TSMC and Altos involved the creation and validation of statistical timing models using TSMC’s standard cell library. The models created by Variety include intra-die (random) variation as well as global systematic variations. The results of these models were passed to SSTA and the resulting path
delays were compared against golden results generated by Monte Carlo Spice simulation using TSMC’s statistical device models. TSMC analyzed a large number of paths and all were found to have excellent good correlation to the Monte Carlo results for both the mean path delay and the standard deviation (1 sigma)."

Altera Corp. announced that NEC System Platforms Research Laboratories has selected Altera's Stratix II GX FPGAs and Nios II embedded processor for implementing NEC’s new high-speed ExpEther interface.

Altera also announced its EP3C120, described as "the largest member of Altera’s new low-cost 65-nanometer Cyclone III FPGA family … The EP3C120 devices consume less than 200-mW standby power."

Arteris announced a Series B round totaling $8.1 million. The company says this round was led by Synopsys and Arteris' original investors, Crescendo, TVM Capital and Ventech. Per the Press Release: "Synopsys' investment was driven by the desire of both companies to lower the cost and risk of designing complex SoC ICs and to foster industry-wide IP reuse capability." The Arteris NoC supports an array of IP protocols including ones from ARM and OCP.

ARC International announced that it has acquired Tenison Technology EDA. Ltd., a privately held EDA provider, for 1 million pounds. Per the Press Release: "The acquisition includes fifteen members of Tenison's engineering team, patents, and products such as the VTOC software suite and IP eXchange technology. The acquired products will provide highly accurate models of ARC's configurable processors and multimedia subsystems. Moreover, they will allow customers to simulate virtually all logic on any ARC-Based chip, including those using non-ARC technologies such as customer-developed IP and IP from other suppliers like ARM."

Carl Schlachte, President and CEO at ARC is quoted: "SoCs for consumer applications are increasingly dominated by chips incorporating multiple processors along with IP from multiple sources. To address the design challenges of customers using these technologies, ARC now will provide its own 'Star IP' and software tools along with Tenison's technology to enable customers to create power-efficient, high performance, and low cost SoCs. This will enhance ARC's ability to service customers using ARC subsystems and cores as part of an SoC design that includes other design components."

In related news, ARC announced an engineering center in Cambridge, England, and the appointment of David Greaves to ARC's Office of the CTO. Greaves is a faculty member and lecturer at the University of Cambridge Computer Laboratory, a Founder of Virata, and Founder and Chief Scientist of Tenison.

ARC then announced new development tools. The company says the new ARC xCAM tool provides cycle-accurate models and is based on technology acquired from Tenison. Per the Press Release: "The two new ARC xISS (instruction set simulator) tools operate up to 100x faster than previous versions. The xCAM and xISS products will help ARC customers more easily and quickly create and test software earlier in the SoC design cycle, thereby speeding time to market of customers' chips."

Agilent Technologies announced an integrated verification toolkit for signal integrity design for use with the company’s ADS EDA software platform. Per the Press Release: "The new toolkit identifies and analyzes sources of performance-degrading jitter in multi-Gigabit communication link designs. It helps designers find and remove the causes of jitter before hardware prototyping begins, eliminating costly redesign later in the development cycle."

Agilent also announced its Antenna Modeling Design System (AMDS), which the company describes as "a 3D, dedicated design, modeling and verification tool for antenna systems and placement" AMDS simulates a wireless appliance in its environment and helps assure compliance with regulatory and operator demands including over-the-air performance and SAR (specific absorption rate). Research In Motion has adopted AMDS for R&D purposes.

Apache Design Solutions announced that TMSC's
Reference Flow 8.0 includes Apache's RedHawk-ALP for power integrity of switched
memory. Sahara-PTE for thermal integrity including stacked chips, and  
Sentinel-CPM for IC-system power

Zuken announced Gerhard Lipski is "the first Western member of the company’s corporate board of directors. This appointment is in recognition of the growing global importance of Zuken’s Western market, which under the leadership of Mr Lipski, has seen revenue rise by a massive 41 percent during the last three years." Lipski has been with Zuken since 1997, and is currently President and CEO for Zuken Americas.


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-- Peggy Aycinena, EDACafe.com Contributing Editor.