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June 18, 2007
DAC 2007 – Perceptions of Primacy in Pleasantville
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor


by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


It’s always difficult to decipher the Design Automation Conference, particularly when it’s set in San Diego – California’s version of Pleasantville. The sun is ubiquitous there, the people clean-cut and courteous, the water tidy and blue. One could come away from a DAC set in such a venue and believe that a) DAC is dull or dying, or b) EDA is dull or dying. However, if you came away with such a conclusion you’d be a) wrong or b) dead wrong.


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DAC is neither dull nor dead, and neither is EDA. On the contrary, both DAC and EDA continue to be populated by the most intelligent, competitive, bickering, jealously-jockeying-for-position, alpha-male population anywhere within the semiconductor design and supply chain. A fact that makes a DAC set in Pleasantville one of the more interesting to participate in and/or observe.


Don’t be fooled for a minute just because the 44th DAC seemed quiet that the people within the EDA industry are courteous, tidy, or blue. They’re not. In fact, they’re discourteous, messy, and come in every color except blue. And this is the way things should be in an industry that needs disruptive thinking, rebellious behavior, and inventive irreverence to keep progressing forward, ever forward, into that ITRS roadmap that stretches off into the distance of the next decade, century, or millennium.


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Sunday morning, noon, and night


Sunday, June 3rd, dawned before dawn in San Diego with the start of the 10th annual Rock ‘n’ Roll Marathon that wound its way through 26.2 miles of city’s highways and byways. In that huge gathering of 20,000 runners, San Diego showed itself to be welcoming and awash in live music every mile or so along the course. It was a great moment for the city, but not so great for those hurrying to the San Diego Convention Center to attend DAC tutorials or construct booths on the Exhibition Show Floor. Streets were closed all over town which, when added to San Diego’s propensity for one-way streets and road construction projects, made it a pretty tough go for those traversing
the city by car.


The DAC tutorials and booth construction persevered, however. I attended snippets of two tutorials in the Convention Center on Sunday afternoon – a keynote from ArtisanSW CEO Jeremy Goulding which was part of the UML for SoC Design Workshop (with an audience of 45+ people), and a panel discussion which was part of the Low Power Coalition (LPC) Workshop (also with an audience of 45+).


Goulding invoked Geoffrey Moore and Henry Ford, and said early adopters are not always winners, and a proliferation of vendors is always needed for technology innovation. Goulding also noted that Gartner tracks 68 different “hype-cycle” technologies, but not UML. He concluded that since UML is neither a trendy technology nor remarkably successful to date, it’s destined to eventual greatness through a proliferation of vendors and mid-to-late cycle adoption. He said UML will handle increased design complexity and higher levels of abstraction once good standards for the language are put in place. His talk was well received, and UML Workshop organizers noted that
for the first time this year representatives from the Big Guys in EDA were all in attendance. I predict you’ll be hearing much more from the UML space in coming years.


The panel discussion at the Si2-sponsored LPC Workshop next door was not quite as inspiring. Clearly there’s a problem brewing in the EDA community between UPF (Accellera’s United Power Format, championed by Synopsys, Mentor, and Magma) and CPF (Si2’s Common Power Format, championed by LPC and Cadence). A pox on the houses of all of the players who have let this situation develop, but as noted earlier, EDA is nothing if not about Alpha Companies, and nobody that I spoke to at DAC believes the players involved in this controversy are going to stand down anytime soon. That’s sad news for the many smaller players in EDA who find themselves having to support both UPF and
CPF in their tool offerings. Hence, it was with some skepticism that I listened to the companies on the LPC panel – AMD, ARM, ArchPro, Atrenta, Cadence, Calypto, LSI Logic, NXP, and Sequence.


Standing at the back of the room, Si2 CEO Steve Schulz tried to bring coherence to a scattered conversation, and asked the panelists to talk about a possible CPF roadmap. Comments from panelists included: “CPF was powerful enough to describe a helluva lot of stuff more than 2 years ago, but is it powerful enough to do everything we want to do today? Not yet, because the industry has some work to do.” “There is a danger of moving too fast. We could put everything including the kitchen sink into the format and find there are no tools to support it.” “[Things will progress] once you have multiple proof points, more than just the Cadence flow we’ve got
now.”


Representatives of all of the Big Guys in EDA, folks from both sides of the low power format controversy, were very visibly present in the audience and as Si2’s Sumit DasGupta concluded the panel and the workshop – “LPC at Si2 is a customer-driven group formed to address issues related to low-power design flows. CPF 1.0 is available for free from Si2 and serves as the starting foundation for current and future work in low power. Join LPC and drive the industry forward.” – the applause was not deafening.


The UFP faction were up next, down the hall at their Design & Verification of Low Power ICs Workshop from 4 PM to 7 PM. For those interested in the Compare & Contrast Game, attending the CPF and UPF workshops in quick succession was a compelling opportunity. But the EDAC Annual Cocktail Confab and Executive Reception started at 5 PM in the Marriott next door to the Convention Center, and given a choice between UPF and an open bar, it seemed many voted with their feet. Hundreds showed up for the EDAC event, but as things turned out, they might have been better off opting for the UPF event still underway in the Convention Center. Because, although great thought and good
intentions undoubtedly went into assembling the panel discussion which was at the center of the 5-to-7 o’clock EDAC event, the conversation between the 11 men on stage seemed scripted and dull. Come on – 11 people? That’s not an event, that’s Death by Disaggregation.


The panel – billed as two panels for the price of one – was moderated by EN’s Ed Sperling and EDN’s Ron Wilson, both from Reed and both seated at the center of the stage. The right half of the stage was populated with EDA users including Qualcomm, eSilicon, National Semiconductor, and Broadcom. The left hand of the stage was populated by EDA suppliers and enigmatically included ARM and TSMC (these are EDA guys?) along with Analog Bits, Synopsys, and Magma. Sperling promised that the 75-minute panel would “break down walls” between vendors and users. Following are only some of the many words of wisdom from those 75 minutes that I typed into
my laptop between sips of white wine. Try to guess if the comments come from the right side of the stage or the left, and try to see if any walls are tumbling down.


The scaling era is finished. When are you going to enable [design] with tools that do everything from architecture down to silicon implementation? We’ve been dabbling in the ESL space, [but] John Cooley says few engineers are actually using it. The concept resonating now is virtual platforms. Predictability relies on modeling and extraction. The model needs to know how the silicon will behave. We need to know the impact of tradeoffs at the top of the design process. ESL? I’m not even sure what that is. Any amount of reuse is a good thing, but how can you re-architect a design? As we go forward, things are going to get harder. The IP industry is so fragmented, even if you’re using IP you’re not really using IP. Changing from technology to technology makes it hard to do reuse. Integrating IP is really hard, because there are no standard EDA tools that help you integrate. The only IP that doesn’t cause problems is obsolete IP. Reuse is a moot point in analog. If you’re doing something that’s never been done before, that’s not IP, that’s design services. Let’s quote Ronald Reagan: “Trust but verify.” Verification and IP are all linked. Verification has become a huge problem. Not only are designs getting bigger, they’re poorly architected and impossible to verify. There’s hope behind
SystemVerilog. It moves up in abstraction, is more object oriented, multi vendor, with less lines of code, and can create designs that are more regular and verifiable. The way to get better silicon is to use logic BIST. I’m enjoying being on this panel because of the sheer joy of beating up on the EDA vendors.


The panel ended with Sperling asking for a laundry list of needs from the right side of the stage. Broadcom wants SSTA; National wants faster circuit simulators; eSilicon wants to close the gap between the technology and the tools; and Qualcomm wants an environment that lets them model the design both in the technology and in the business space. Apparently the vendors on the panel already knew all this, because nobody on the left side of the stage seemed to be taking notes. Blessedly, the EDAC event came to a quick close freeing everybody to rush across the lobby of the Marriott to get to the next Whine & Cheese event – the First Annual Gary Smith EDA Forecast Presentation and
Cocktail Party.


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Compared to the EDAC event, the Gary Smith EDA “party” (7 to 9 o’clock) was a much rowdier gathering of the clan. Maybe it’s because everybody was already liquored up when they arrived, maybe it’s because the UPF Workshop attendees showed up, or maybe it’s because between Tom Starnes, Mary Ann Olsson, Daya Nadamuni, and Gary Smith there was actually some substantive facts thrown out to the hundreds in attendance.


Starnes lead off with a lengthy discussion of multi-core processors in modern day SoC design. He said MCUs offer the hope of added cache to speed things up, frequency increase to speed things up, more DSPs, and more streaming data – also to make things go faster. But, he acknowledged, not only is building these MCUs complex, but “pity the poor bastard who has to program the thing and make it work.” Starnes also challenged his audience to stick with him as he walked through high-tech details of MCUs from Freescale, TI, and Docomo. He ended his spiel by advising, “Multiple processors are here. Deal with it!”


May Ann Olson was next on stage and laid out the landscape of semiconductor production, chip and board design and manufacturing, and MEMS as a new frontier in EDA. Her slides threw out rhetorical conundrums such as: What software & IC designers don’t see: stacked die; What EDA software designers don’t envision: variable assembly options; What chip designers don’t think about: critical parameters. She concluded with comments about aging fabs and the migration of legacy manufacturing equipment to a hungry market in China.


Although the evening was growing long, Daya Nadamuni continued to challenge the audience with a discussion of the nightmare of parallel programming. She noted that the primary drivers for such gymnastics are server farms, data aggregators, and content distributors – anybody who needs to get a lot of bits from here to there, fast. She touched briefly on homogeneous versus heterogeneous MCUs, and concluded that the challenges boil down to the software and the development tools to support it. Software concurrency is creating roadblocks, per Nadamuni. She said the vendors have been slow to respond – the gauntlet’s been thrown down and it remains to be seen who will answer the
challenge.


Gary Smith wrapped up the evening by satisfying his fans with a bold-faced prediction of growth in EDA through 2011. He said the market will stand at $4,435 billion in 2006 and grow steadily to $6.585 billion in 2011. He then pointed out what many, deep into their wine, did not want to hear. There’s consolidation in the semiconductor world, which translates to fewer customers for the EDA world. As a result, and because of forces at work related to the earlier talks, Smith said EDA is changing to include hardware, software, and parallel processing. The tools are being rewritten for 65 and 45 nanometers, but embedded software has to be part of the product mix/offerings or the EDA
vendors will miss their chance at the brass ring. The tools need to be rewritten to function on parallel processors, and the tools need to be enhanced to support embedded software on parallel processors. Kind of a chicken and an egg thing, or cart and horse. Smith ended by saying, “This isn’t the end of EDA. It’s just the beginning!”


Wine or no whine, everybody in the room seemed swept up in his enthusiasm. Does it get any better than this on DAC Sunday?


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Monday morning, noon, and night


The Workshop for Women in Design Automation
(WWINDA) used to take place on Sunday’s at DAC. These days it happens on Monday mornings, so folks who are busy on Sunday preparing booths in the Exhibition Hall can come as well. This year’s event included a keynote from Oregon State University’s Terri Fiez that detailed her career progression from engineering student, to IEEE Fellow, to head of the EE Department in the OSU School of Engineering. The keynote was followed by a panel discussion on career development between EDA Industry Analyst Daya Nadamuni, Javelin Design President & CEO Diana Raggett, Qualcomm Senior VP Daphne Huckaby, and
firstRain President & CEO Penny Herscher – all folks who know more than a little about balance, transition, and leadership.


The morning concluded with the presentation of the Marie R. Pistilli Award to Cadence Senior Vice President Jan Willis. Cadence CTO Ted Vucurevich and firstRain CEO Penny Herscher spoke at length about Willis’ accomplishments, while the actual presentation of the award was made by DAC General Chair and University of Pittsburgh Professor Steve Levitan. As Willis is a highly visible member of the Executive Team at Cadence, many people from Cadence came into the room to be on hand for the presentation of her award. In addition, six graduate students were in attendance from the University of Pittsburgh, U.C. Berkeley, U.C. San Diego, and Stanford
sponsored by Cadence, Magma, EDA Confidential and Mentor Graphics, respectively. Surely I’m prejudiced as to the success of this year’s WWINDA having worked on the event with Workshop Chair Sabina Burns from Virage Logic, but it was a great morning of candid conversation and networking.


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By mid-afternoon on Monday, June 4th, General Motors’ Vice President for R&D Lawrence Burns was busy giving the first keynote at DAC. His was not a detailed technical talk, but an evangelical pitch in favor of GM’s hydrogen-fueled proof of concept automobile, the Sequel. Burns said there are 850 million cars in the world today, a number set to reach 1.1 billion by 2020. Where are all of those greenhouse gas emissions going to go, his argument went, unless those billion autos are only spewing out water vapor like GM’s Sequel? And Burns said, time is of the essence: “We have to find a way to free ourselves from petroleum fuels, because currently 98 percent
of the autos in the world [depend on it].”


For those cynics among you who believe the Big Iron Auto makers in the U.S. have dragged their feet for decades in the areas of alternative energy and/or more efficient vehicles, this keynote from GM was either a) extraordinary, or b) too little too late from the folks who had a hand in creating the environmental mess in the first place. But, oh well. GM came, GM spoke, and GM was very well received by the biggest crowd I’d seen at DAC to that point in the week. There were at least 500 people in the Convention Center ballroom and Burns got a very, very warm round of applause at the end – presumably from the many who would like to drive his Sequel, and from even more who would
like to add their engineering know-how and creativity to pushing such projects closer to a full-production reality.


By the way, GM’s Sequel sports a wagonload of electronic gadgetry – much of it developed in conjunction with researchers from Carnegie Mellon – including crash-avoidance technology, next-generation telematics, and driverless-vehicle enablers. Step up if you want to pitch in to solving all of the engineering problems further progress entails.


Following the hour with GM, I ran to an hour with IP. The 3 o’clock Pavilion Panel on the DAC Exhibition Hall was assembled to answer the question: “Just Who is Providing the IP?” Happily, Star IP provider ARM was on the panel along with one of its Star IP customers, STMicroelectronics. ARM’s Mike Muller and ST’s Paul Bromley launched into what turned out to be an authentically unscripted conversation about IP, who provides it, and when and where and why.


Sitting between them on the Panel Pavilion couch, and adding to the discussion, was Design & Reuse Center’s Gabriele Saucier, a last-minute addition to the panel because of my concerns (as moderator) that it’s not a ‘panel’ but an ‘advertorial’ when the conversation is only between a vendor and his customer. And, thanks to some quick work on the part of ARM’s Lauren Sarno, Madame Saucier was added to the conversation just 2 days prior to DAC. Meanwhile, as I was moderating this panel and not typing during the discussion, the following summary of the conversation is based on impressions more than notes. I’m paraphrasing here
what I believe to have been the high points of this hour-long give-and-take.


ARM is a Big Guy in the IP industry, but they acknowledge they still have ways to grow and improve. They do not pretend to be able to answer everyone’s IP needs, but in the areas that they do participate, they insist their IP is the best – well validated and vouchsafed by a huge organization. Nonetheless, a company the size of ST may not always turn to ARM, or any other third-party provider for that matter, to meet all of their IP needs. They have lots of internal IP that they can use to speed up projects through the magic of design reuse. ST, however, is not as adept as they would like to be at cataloging and mining all of their internal IP. Hence, they may actually be turning
to third-party vendors for IP that will be supported by an external provider because it’s a quicker end to a means than trying to work internally to find inaccessible IP, which even when located may not be adequately documented.


Meanwhile, despite ARM’s mantra that IP should only be bought from large, proven vendors, the Design&Reuse site includes IP offerings from over 400 different vendors – including some in China and India – and it’s still a bit of the Wild West out there when it comes to IP. ARM is not pleased that there are so many vendors because it does not help to improve the unfortunate impression among potential customers that IP comes with problems or from fly-by-night organizations. ST, on the other hand, is not committed to the ‘Fewer is Better’ IP vendor proposition. Currently, they work with dozens of vendors to meet their third-party IP requirements. Despite
other disagreements, ARM, ST, and D&R are all in accordance that standards are the path to Nirvana when it comes to IP.


Once this conversation got rolling, we could have continued for another hour or two, but between 4 PM and 7 PM on DAC Monday, the options for the overly-caffeinated were too complex to stay put for that long.


Starting at 4:30 in the UPF booth in the Exhibition Hall – manned by folks from Accellera, Synopsys, Mentor, and Magma – there was champagne and some really nice hors d’oeuvres. Things were just getting started there when I dashed by, but it looked like it was going to be fun. There was also food and beverage, and potentially IP Nirvana as well, to be had at the SPIRIT Consortium meeting upstairs in the Convention Center starting at 6. Again, mine was a drive-by visit, but first impressions said the SPIRIT folks were expecting well over 100 people to show up for presentations from 13 different companies demonstrating their successes-to-date working with the SPIRIT IP-XACT
standard.


Amidst this overlap of UPF and SPIRIT, there was a CEDA lecture and networking event, also on the 2nd floor of the Convention Center. CEDA, the Council on EDA, is an IEEE-sponsored organization and their Monday evening event included a talk by University of Washington’s Richard Shi based on his IEEE Transactions on CAD Best Paper, “On Symbolic Model Order Reduction.” Again, I only ran by long enough to say hello to a few folks as the event was getting into gear. Meanwhile, also at the very same time on the 2nd floor of the convention center, Sun and Synopsys were hosting their Annual University Reception. Sun’s Shrenik Mehta, currently Accellera Chair,
was busy greeting the many academics who were arriving for that early evening event when I stopped in. Again, I was only there briefly, but the next day Shrenik told me that the talk given during the evening by U.C. Berkeley’s Jan Rabaey was outstanding.


Okay – time check here. UPF, SPIRIT, CEDA, University Reception all co-located and concurrent, but did you know Si2 was also having a meeting at the same time, also on the 2nd floor of the Convention Center? Gosh – with all of these people, meetings, and topics, who was it that was suggesting that DAC and/or EDA is dull or dying? Hmm. Guess they weren’t in San Diego between 4 and 7 and Monday, June 4th.


And Monday was not over yet. For those lucky enough to be on the guest list, Mentor Graphics was hosting their annual Press & Analyst dinner at the Coronado Hotel across the water on Coronado Island. By car or taxi, this is about a 15-minute ride from the Convention Center and for those who suspected the dinner would be delish, they were not disappointed. Mentor spiced up the cocktail hour with presentations from customers UMC, MIPS and TI, and then served a sumptuous dinner, with equally sumptuous wine, rounded out with a performance from a black-light dance team. Mentor’s festivities wrapped up at 10, leaving time (unbelievably) for one more event before the evening was through.


Virage Logic hosted a late-evening Brandy & Cigar event back in downtown San Diego at the Salomar Hotel. Even though most of us were into an 18-hour day at that point, this was a great gathering of folks. Everybody there was either too tired to be tense, or too relaxed to be tired, and just about everybody who was anybody from the EDA vendor community was there. Of course the topic of the hour was the hottest topic of the day.


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Perceptions of Primacy in Pleasantville


Embarrassingly, I seemed to have been the last among the thousands at DAC on Monday to have heard the crucial rumor that Cadence was going to go private via a $6.4 billion infusion of cash from either KKR (Kohlberg Kravis Roberts), the Blackstone Group, or both. But heck, between the Women’s Workshop, the GM keynote, and the IP Panel, it had been a busy day. By 4 PM, I suddenly found I had some rumor-mill catching up to do.


The Cadence story appears to have started early on with a report in the New York Times quoting unnamed sources about the deal, which was then picked up by everybody and their brother on Monday and spun out as a “news” story in every publication even remotely connected to Cadence’s world. Not surprisingly, Cadence stock spiked immediately on the “news” and CEO Mike Fister was being hailed all over DAC as some kind of miracle worker. Comments like, “Heck, if he can get Cadence valuation up to $6.4 billion, you’ve got to hand it to the guy.”


Others were not quite so complimentary. Many let me know over the course of Monday afternoon and evening that this type of thing might be good as a source of windfall profits (is that a term we even use anymore?) for a few executives at Cadence, but in the long run it wasn’t good for the shareholders, the customers, or the employees. One CEO was bold enough to suggest that if a company can’t innovate, their only option is to go private and let their legacy tools run their course as cash cows before the company is put out to pasture. Many, however, did agree that a private buy-out was indeed good for anybody who was sick of messing around with the tedium of Sarbanes-Oxley, or the
demands of the investing public who kept asking why the company wasn’t growing or innovating faster. But even those with the most pointed criticisms, never failed to give begrudging respect to Mike Fister, EDA Man of the Hour on DAC Monday.


Then Tuesday dawned and we never heard about it again.


Cadence stock sagged back a bit, and by Wednesday at DAC, people forgot Monday had ever happened. The few who could remember 2 days back were frequently cynical, openly calling the whole thing a publicity grab and a move by “unnamed sources” to wrest control of the PR machine that runs in overdrive at DAC.


By the start of the following week, the Blackstone Group was, ironically, front-page news across the nation, but not because of Cadence. It seems Blackstone is set for an IPO in just a few weeks, and has been forced to reveal details of its executive compensation including $400 million in 2006 for CEO Stephen Schwarzman and $213 million in 2006 for Founder/COO Peter Peterson.


Also, per Associated Press reports, the Chinese government controls 9.7 percent of the company by way of a $3 billion investment in Blackstone Group in May 2007. Maybe they were anticipating the Blackstone transaction with respect to Cadence and wanted to get in on the action? In any case, now 9 days later it’s tough to find any news related to DAC Monday’s “hot” story about Cadence, Blackstone Group, and KKR.


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The real thing


As it turns out, however, there really was some news within EDA last week, it‘s just that few were in the loop. Although not officially acknowledged until 8 AM on Monday, June 11th, clearly many folks knew by mid-week last week that Mentor Graphics was acquiring DFM vendor Sierra Design for $90 million. The guys at CMP – Brian Fuller and Richard Goering, in particular – did a whole story about the deal standing in the breeze in front of the San Diego Convention Center during DAC, which they posted to the CMP site on Sunday, July 10th. It included full interviews with Mentor CEO Wally Rhines and Sierra CEO Pravin Madhani, clearly recorded during
DAC. The implications from this story are complex.


First, it would appear the guys at Reed lost out on this particular scoop – it was a CMP story from start to finish. So much for perceptions of primacy at Reed. CMP won this one outright.


Second, it would appear that Wally Rhines and his team at Mentor are tired of playing a cheerful, but distant 3rd to Cadence and Synopsys when it comes to having something sorta kinda like a complete design flow to offer their customers. Mentor is in the game.


Third, it would appear the folks who went on record for my EDA Weekly article on DFM in May missed the boat when they failed to mention Sierra Design as a significant player in the DFM space. Even Sierra’s Director of Marketing, Sudhakar Jilla, named Mentor, Synopsys, and Clear Shape in that article, but not Sierra Design. Or, is it the case that Sierra Design actually only provides a part of the DFM solution, but a part that Mentor thought it faster to buy than develop and hence the acquisition?


Finally, when it comes to perceptions of primacy in Pleasantville, or EDA for that matter, one should be careful of jumping to conclusions. As Terri Fiez emphasized at the close of her keynote at the Women’s Workshop in offering career advice to the upwardly mobile in her audience – when it comes to leadership, try everything that you’ve learned through experience or training, but realize that sometimes, “You just have to be the alpha male!”


Mike Fister may have been hailed as the Alpha Male of EDA on June 4th, but by June 11th, I think Wally Rhines had better claim to the title. Wally and Richard Goering, that is.


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Next time: DAC Tuesday & Wednesday


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News from in and around DAC


Agilent Technologies
announced the expansion of technologies in its Advanced Design System (ADS) and GENESYS design platforms to provide a “full spectrum” of software tools for microwave and RF designers. The company is increasing investments in RF/microwave design and simulation technologies to help designers of monolithic microwave integrated circuit (MMIC), systems-in-package (SIP) and RF boards stay competitive when incorporating the latest communications standards and techniques. "Because we are the only company using our own, internally developed commercial EDA tools to design components for the test and measurement instruments we market, we must stay at least two
steps ahead of today's industry, anticipating the direction of tomorrow's wireless technologies and products," sayeth Jim McGillivary, vice president and general manager of Agilent's EEsof EDA division.


Aldec announced a new Verilog linting engine, ALINT, that the company says complies with the second edition of the STARC "RTL Design Style Guide." ALINT supports rules that cover various levels of RTL design cycle, and “provides flexible configuration features that allow companies to control implementation of corporate design guidelines.”



Ansoft announced HFSS v11, which the company says includes new technology that delivers “greater accuracy, capacity, and performance” than earlier versions, including higher-order hierarchical basis functions combined with an iterative solver that uses smaller meshes and “more efficient solutions for large multi-wavelength structures … HFSS [simulates] very complex models two to five times faster using half of the memory compared to previous versions.”


AXIOM Design Automation announced it has endorsed the Unified Power Format for power-aware designs and fully supports UPF in its MPSim Verification Solution. Per the Press Release: “Now design engineers using Magma's IC implementation system and the verification engineer using the MPSim verification environment can use the same low-power description.”


Berkeley Design Automation announced that Luminary Micro has chosen Berkeley Design’s Analog FastSPICE circuit simulator for full-circuit verification and verification of complex blocks “at 5x to 10x the speeds previously available to Luminary … with full SPICE accuracy.”


Berkeley Design also announced that Newport Media has adopted the company's Analog FastSPICE circuit simulator.


Bluespec
announced Charlie Hauck is now CEO and succeeds Shiv Tasker, who assumes the role of chairman. The company says the changes were made to “better align Bluespec for anticipated growth due to strong demand for its broadened product offerings.” Hauck joined Bluespec in November 2006 from Faraday Technology where he was U.S. general manager. He has 25+ years’ experience in R&D, engineering, marketing and management in the semiconductor industry. Prior to Faraday Technology, he served as vice president of Engineering at Lexra. Hauck has a BSEE from the Johns Hopkins University and an MSEE from MIT. Before taking the helm at Bluespec, Tasker was
President and CEO of Phase Forward. Previously, he was Senior Vice President at Viewlogic Systems. Tasker has an MBA from U.T. Arlington, and a BS in Statistics and Economics from the University of Bombay.


Cadence Design Systems and TSMC announced that Cadence is providing “key capabilities” to TSMC Reference Flow 8.0. Per the Press Release: “The Cadence contribution within TSMC Reference Flow 8.0 is based on several new capabilities in the Cadence Encounter digital IC design platform and the Cadence Logic Design Team Solution.” Lucky TSMC.


Cadence also announced, in conjunction with TSMC, availability of the Cadence QRC Extraction tool for parasitic extraction for TSMC's 45-nanometer technology.


Cadence also announced that Realtek Semiconductor Corp. has completed an “aggressive low-power design” using Cadence’s Logic Design Team Solution. Interestingly, per the Press Release, “Realtek is a leading Taiwan IC design house offering a comprehensive range of communication network, computer peripheral, and multimedia ICs.”


Certess announced it has selected Verific Design Automation's HDL Component Software to serve as the front-end for Certess’ newly released Certitude functional qualification tool.


ClariPhy Communications and Helic S.A. announced an engineering collaboration over the past 12 months, which has been instrumental in the first-pass success of ClariPhy's single-chip, 10GBASE-LRM, mixed-signal CMOS transceiver. Per the Press Release: “ClariPhy selected Helic's EDA tool, VeloceRF, after diligent evaluation.” One would certainly hope so.


CLK Design Automation announced that has linked its Amber Analyzer incremental static timing and signal integrity analysis tool to Verific Design Automation's HDL Component Software. The companies say that Verific's Verilog Netlist Parser serves as the front-end to the Amber Analyzer and “runs smoothly on 64-bit machines.”


The Common Platform technology alliance
– IBM, Chartered Semiconductor Manufacturing and Samsung Electronics – announced availability of DFM technology models, data files and design kits from “leading” EDA and DFM companies, supporting Common Platform technology at 45 nanometers. Per the Press Release: “This is the second node, following 65 nanometers, where the alliance partners have driven comprehensive DFM solutions, which marry technology and tool support from leading EDA and DFM suppliers with manufacturing data and models from the Common Platform technology foundries to help ensure the success of chip designs at this advanced technology node across
all three manufacturers' fabs.”


CoWare, AXE, and BeatCraft announced that the AXE axLinux and BeatCraft JAKAR Media Framework have been integrated with the CoWare Virtual Platform. Per the Press Release: “The integration demonstrates the value of virtual platforms for software development and extends CoWare's ecosystem for the delivery of software-driven architecture development solutions. It also enables customers to leverage both AXE and BeatCraft expertise for virtual platform-based software development.”


Cree, Inc. and Applied Wave Research (AWR) announced a process design kit (PDK) supporting Cree's GaN process. Per the Press Release: “The kit enables monolithic microwave integrated circuit (MMIC) designers to use Cree's GaN MMIC process within AWR's Microwave Office software environment.”


Denali Software and Mentor Graphics announced availability of Denali's PureSpec verification IP products integrated with Mentor's AVM (Advanced Verification Methodology) SystemVerilog environment. The companies say the “integration is a result of a collaborative effort between Mentor and Denali to address the rapid migration towards SystemVerilog in their respective customer bases.”


Dust Networks and Kilopass Technology announced that Kilopass XPM memory is being used in Dust Networks’ embedded wireless sensor networking products. Per the Press Release: “Dust Networks’ SmartMesh-XD Mote-on-Chip (MoC) products employ the XPM non-volatile storage for analog tuning and secure storage of proprietary firmware … Kilopass’ XPM Memory is embedded in Dust’s SoC-based products, and uses a standard CMOS logic process with no extra steps. It is easily programmed in the factory and is virtually impossible to reverse engineer.” That’s good news.


EMA Design Automation
announced TimingDesigner 9.0, which the company says includes design kits with assembled diagrams and libraries for commonly used parts and interface protocol standards, and program modifications to accommodate the latest features of the newest operating systems. Per the Press Release: “Each kit consists of all documented timing protocols associated with one or more design components, and are assembled for easy importation into TimingDesigner's Manager Window allowing quick assembly of any timing project.” Manny Marcano, President and CEO of EMA, is quoted in that same Press Release: "Since acquiring TimingDesigner a short time ago, our design
team has been working diligently to add value to benefit our customers.”


EVE announced an addition to its ZeBu hardware-assisted verification family. Per the Press Release: “Using the MMB with ZeBu-UF, the SoC under verification can be connected to real peripherals or to test equipment to mimic a complete and scalable SoC verification environment tuned to perform all hardware and software validation tasks of any MultiMedia/Portable SoC. The MMB can be further expanded via daughter modules to accommodate additional interfaces such as HDMI, Still Digital Camera and Video Digital Analog converter.”


HARDI Electronics announced its HapsTrak compatible SerDes (high-speed serial transceiver) daughter board, which contains an ASIC SerDes evaluation chip from LSI Logic. The SerDes daughter board will be compatible with all previous and future generations of HAPS (HARDI ASIC Prototyping System) motherboards.


KLA-Tencor announced LithoWare, which the company describes as “a new Linux-based product enabling semiconductor circuit designers to dramatically reduce the time and cost to develop RET and OPC processes. LithoWare is a lithography optimization tool based on the industry-standard PROLITH models that reduces time-to-production by allowing customers to co-optimize the RET and the process conditions simultaneously, while minimizing calibration data collection.”


Magma Design Automation and TSMC announced that Magma's Blast and Talus, Quartz SSTA statistical analysis, Quartz DFM and SiliconSmart DFM tools are included in TSMC Reference Flow 8.0.


The MathWorks
announced Simulink Design Verifier, which the company says “generates tests and proves design properties for Simulink and Stateflow models using the Prover Plug-In from Prover Technology. Developers of embedded systems, especially complex or safety-critical systems, can now automatically obtain test cases to satisfy industry-standard metrics, such as modified condition/decision coverage (MC/DC), while uncovering design errors earlier in the development process when they are significantly less expensive to fix ... Simulink Design Verifier augments simulation with new verification and validation technology based on formal methods that significantly reduces the need to
hand-code tests for establishing complete model coverage and verifying requirements.”


Mentor Graphics and Chartered Semiconductor Manufacturing announced a partnership that the companies say will offer a series of mixed-signal Technology Design Kits (TDKs) supporting 65- and 90-nanometer process technology available from Chartered. Per the Press Release: “The kits have been validated and are available now for use with Mentor Graphics ICstudio design platform … The new TDKs enable the entire analog mixed-signal IC design flow to be tailored for customers using Common Platform technology processes.”


Mentor Graphics also announced that the Common Platform Technology alliance – IBM, Chartered and Samsung – have qualified the Calibre suite of DFM tools. Per the Press Release: “The collaboration between Mentor Graphics and the Common Platform foundries provides an integrated DFM solution to address both random and systematic yield limiters for 65-nanometer and 45-nanometer processes …The new DFM flow uses Mentor's Calibre YieldAnalyzer to perform critical area analysis (CAA) on all base and interconnect layers of a design.”


Mentor Graphics, covering all its bases, also announced along with TSMC that Mentor's DFM and DFT tools have been incorporated into TSMC Reference Flow 8.0. The new Reference Flow 8.0 features Mentor tools for critical area analysis and reduction, chemical-mechanical polishing (CMP) analysis and layer planarity control using smart fill algorithms, litho-friendly design, process variability aware analysis, and DFT flows based on Mentor Graphics’ Calibre and TestKompress “solutions.”


Mentor Graphics
also announced it has acquired Sierra Design Automation, a provider of high-performance place and route solutions. The company was purchased for $90 million, payable 50 percent in cash and 50 percent in Mentor Graphics common stock. Pravin Madhani, Sierra President and CEO, is quoted: "At 65 and 45 nanometers, discontinuities such as process variation, design size, low power and DFM are creating a major disruption in physical design. The merger with Mentor enables us to deliver a powerful design-to-fab flow that addresses these discontinuities in a comprehensive fashion." Wally Rhines, Mentor Chairman and CEO, is also quoted: "Our leading-edge customers are
telling us that they need a design-to-fab flow capable of handling dozens of process corners and multiple modes, all while addressing manufacturability challenges to achieve manufacturing closure of their designs. Mentor's and Sierra's leadership in these areas make us a natural fit. The acquisition of Sierra expands Mentor's leadership in DFM, and provides the integration that customers need between physical design, and back-end verification and yield-enhancement." ST Microelectronics provided endorsement of the acquisition in the Press Release.


MIPS Technologies announced that Cadence Design Systems, Magma Design Automation, Mentor Graphics, and Synopsys will team with the company to provide EDA software and tools support for its MIPS32 74K core family. Last month, MIPS Technologies announced its next-generation 32-bit processor family, which the company describes as “the industry's first fully synthesizable processors to surpass 1 GHz operating frequencies in TSMC 65-nanometer process technology.”


MunEDA announced a licensing agreement with Faraday Technology regarding MunEDA's DFM-DFY tool family, WiCkeD. Per the Press Release: “By choosing MunEDA's leading-edge technology to improve design performance and yield, Faraday is well armed for the new challenges in the nano era.”


Pro Design and videantis GmbH announced the integration of real-time H.264/AVC baseline profile encoder on a CHIPit Platinum prototyping system.


Pyxis Technology announced Phil Bishop has been named President and CEO. Bishop has 25+ years’ experience in high tech. Previously, he was President and CEO of Celoxica, where he took the company public. He has served as a non-executive chairman of the board for Silistix, has worked for Mentor Graphics as vice president and general manager of worldwide consulting, and held engineering and management roles at Motorola, Freescale, and Boeing. Bishop has a BSEE and a BSCE from the University of Michigan, and an MBA from Duke.


Reactive NanoTechnologies developed and manufactures NanoFoil, and announced $14.3 million in a Series C round of financing led by Siemens Venture Capital and existing investor, Sevin Rosen Funds. Per the Press Release: “NanoFoil, a reactive nano-layered material that precisely controls the instantaneous release of heat energy for joining and reaction initiation applications, enables rapid joining of similar and dissimilar materials without incurring thermal damage.”


Sagantec announced a DFM solution for correcting lithography hot spots found in physical IC designs developed in collaboration with Mentor Graphics. The new DFM flow uses Mentor Graphics' Calibre LFD to analyze the design layout and detect lithography hot spots. Sagantec's DFM-Fix tool uses the Calibre LFD analysis results to correct hot spots and optimize the overall layout, which is then verified by Calibre LFD. Per the Press Release: “This solution addresses a wide range of lithography-related issues and works with multiple design styles, including memory, custom and digital, and multiple levels of design, including library, IP core, block and full-chip.”


Sequence Design announced that CoolTime now addresses PGA (power gating analysis) and SSN (simultaneous switching noise) through automated analysis capabilities that the company says “enable faster, more accurate power signoff … CoolTime offers a fast ‘what-if’ PGA capability that enables users to rapidly determine switch turn-on sequence to control peak rush current and minimize wake-up time.”


Sequence Design also announced CoolTime-PGA will be added to the STARC (Japanese Semiconductor Technology Academic Research Center) advanced design flow, STARCAD-CEL.


Sequence Design also announced William Ruby has been named Vice President for Product and Applications Engineering. Prior to joining Sequence, Ruby was a senior exec at Golden Gate Technology. In 20+ years, Ruby has also worked with Intel, Cadence, Synopsys, and Siemens. He has an MBA from San Jose State, a BA in physics from U.C. Berkeley, and an MSEE from USC.


Si2, The Silicon Integration Initiative's Open Modeling Coalition, has finalized the Si2 Effective Current Source Modeling (ECSM) Statistical Extensions specification draft.
Per the Press Release: “The new specification will be released, after approval, as an Si2 standard after a 60-day patent exclusionary period completes. On release, the statistical version of ECSM will become available to the broad electronics industry, both users and EDA vendors alike, regardless of Si2 membership.”


Silicon Canvas
announced what the company calls the “first DFM-compliant technology files offering built-in DFM targeting TSMC advanced process technologies. In a new use model pioneered in Silicon Canvas' Laker custom IC design tools, when design for manufacturing and ‘recommended’ rules are included in the Laker tech files, the user can choose from a number of recommended rule sets, and Laker's built-in DFM features will automatically generate, or guide the user to generate, layout incorporating a more manufacturable and DFM-compliant configuration. These built-in Laker DFM features require no scripting and support advanced design requirements such as multiple
rule sets; conditional rules; recommended rules; discrete gate spacing; minimum area rules; routing jog avoidance; via-doubling; and more.”


Simberian announced an agreement with Mentor Graphics to partner in the OpenDoor program. The companies say, “Through this agreement, Simberian’s 3D full-wave field solver for multi-layered circuits, Simbeor can output electromagnetic models of transmission lines and via-holes directly to HyperLynx and Eldo formats for accurate system level design of high-speed serial PCB and packaging interconnects.”


Sonics announced availability of MemMax RD, which the company describes as “a new version of Sonics' MemMax Memory scheduler solution that contains a seamless interface and pre-verified configuration and initialization settings optimized for the Synopsys DesignWare DDR2 SDRAM Protocol Controller IP.”


Synopsys and TSMC announced Synopsys support for TSMC's Reference Flow 8.0 and 45-nanometer process technologies. Synopsys says it is supporting Reference Flow 8.0 in its Galaxy design platform, Discovery verification platform, and DFM products.


Synopsys also announced that Al Castino and John Schwarz have joined the company’s Board of Directors, which now includes 7 independent members. Castino will serve on Synopsys' Audit Committee; Schwarz will serve on the company's Compensation Committee. Both new directors will also serve on the company's Nominating and Corporate Governance Committee. Castino is Senior Vice President and CFO at Autodesk; Schwarz is CEO of Business Objects.


Synopsys
also announced its VMM Catalyst Program to further accelerate widespread adoption and support of the industry-leading VMM verification methodology for SystemVerilog. Per the Press Release: “The VMM Catalyst Program is open to EDA vendors, silicon and verification IP companies, and training and service providers to benefit mutual customers by advancing tool interoperability and the availability of IP and services using the VMM methodology. Industry support from more than 50 firms and widespread customer adoption has established the VMM methodology as the de facto standard methodology for verifying complex electronic chips. The VMM Catalyst program helps meet the growing
demand for productive and interoperable verification flows taking advantage of the full power of SystemVerilog.”


Synopsys also announced that a four winners of Synopsys' seventh annual Tenzing Norgay Interoperability Achievement Award for their “vital, initial support of a single standard for low-power design and verification. Texas Instruments, Nokia, Mentor Graphics, and Magma Design Automation together with Synopsys demonstrated strong support from the outset for an open, fast and inclusive standard to enable an interoperable low-power design and verification solution. The resulting Unified Power Format (UPF) is the newest Accellera standard approved in February 2007.”


Synopsys and Hitachi High-Technologies Corp. announced the companies have developed a “seamless link between Hitachi High-Tech's DesignGauge design data measuring system and Synopsys' Proteus optical proximity correction (OPC) solution.”


Synplicity
announced a definitive agreement to acquire all of the outstanding shares of HARDI Electronics AB, a company that develops of off-the-shelf ASIC prototyping boards (see news item above). The deal is said to involve $24.2 million in cash. Per the Press Release: “HARDI's ASIC Prototyping System (HAPS) is used worldwide by industry-leading companies such as Broadcom, Conexant, LG, LSI Logic, Marvell, Matsushita, Nokia, NXP, Philips, Samsung, Sharp, Sony, and TI … The ASIC prototyping market is one the fastest growing segments of the EDA industry, and this acquisition makes Synplicity the leader in this part of the ASIC verification market.”
Nice!


Synplicity also announced the Confirma platform, which the company describes as “a next generation, high-performance verification solution that dramatically improves the traditional ASIC and ASSP verification process … The Confirma platform includes Synplicity's Certify tool, the industry standard for multi-FPGA partitioning and implementation; as well as the company's recently introduced Identify Pro software with TotalRecall technology providing full visibility into the design under test; and, the HAPS FPGA-based prototyping hardware, the most flexible prototyping boards on the market today.”


Teseda Corp. announced an exclusive hardware licensing agreement with INTER ACTION Corp. and two new executives. John Molloy is now leader of the North American and European sales teams, and Ralph Sanchez is now leader of the engineering team. As a result of this agreement, INTER ACTION will be the worldwide hardware manufacturing and logistics partner for Teseda's diagnostic test offering.


Virage Logic
announced the appointment of Pete Rodriguez as Chief Marketing Officer and Kamalesh Ruparel as Vice President of Silicon Technology. Rodriguez has 23+ years’ semiconductor industry engineering, sales and senior management experience. He currently is a director for EXAR and previously was president, CEO and a director of Xpedion Design Systems, acquired by Agilent. Prior to Xpedion, he held senior management positions at Escalade, until its acquisition by Mentor Graphics. He held senior positions at LSI Logic, and various positions at Aerojet Electronics, Teledyne Microwave, and Siliconix. Rodriguez has a BS in Chemical Engineering from CalTech, an MSEE
from Cal Poly Pomona, and an MBA from Pepperdine University. Ruparel has 22+ years’ IC ecosystem experience and joins the company from Anchor Bay Technologies, where he served as vice president of engineering. Previously he was at Cisco Systems, Apple Computer, Vertex Semiconductor, and Texas Instruments. Ruparel has a BSEE from the U.T. Austin and an MS in CS from the Southern Methodist University in Dallas.


The VSI Alliance (VSIA) announced the public release of Quality IP (QIP) Metric version 4.0, which the organization says includes the verification IP (VIP) extension. Cadence, Denali, EDA Centrum, Freescale, LSI, Mentor Graphics, Synopsys, and UMC all say they participated in the development of the VIP extension. Importantly, the QIP Metric version 4.0 is available for free on the VSIA website.


XYALIS announced an “advanced methodology” for building CMP models through a collaboration with CIMA-Nanotech, and says it will be able to provide “high-accuracy thickness measurements” on wafers. Per the Press Release, “Thanks to ‘non destructive’ nanometric measurement equipment's, XYALIS is able to build CMP models … for estimating the critical areas where dummy filling is needed to smooth the thickness variation. With advanced processes starting at 65 nanometers and below, using a model-based estimator is a must to find critical areas and reduce the number of dummy tiles inserted and reduce parasitics and yield lost.”


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Peggy Aycinena is Editor of EDA Confidential and Contributing Editor to EDA Weekly.




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-- Peggy Aycinena, EDACafe.com Contributing Editor.


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