May 21, 2007
DAC & DFM – Once More, with Feeling
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| by Peggy Aycinena - Contributing Editor
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DAC looms. It’s less than 14 days to San Diego. Nobody’s ready. Nobody’s sleeping. Everybody’s in a state. Everybody’s frantic. Everybody’s wondering if this, that, or the other thing will get done in time for the opening bell. How did it come to this? Didn’t we promise ourselves last year that we’d be on time this year, ahead of schedule even?
Okay, okay. So it turns out were all mortal after all. Whatever. Here are a few suggestions that may help:
1) Stand up. Take a deep breath. Sit down. It’s all going to get done.
2) If you need a hotel in San Diego, go book one now. If you need a plane flight to San Diego, go book one now. If you haven’t
3) Once again, stand up. Take a deep breath. Sit down. It’s all going to get done.
4) See that “Print” button up on the upper right quadrant of this page? Click on it to see this newsletter all on one page. That will save some time not having to click through.
5) Get a cup of coffee. (Decaf would be best at this point, don’t you think?)
6) Read this article to completion. It’s a survey about DFM, and it’s pretty darn interesting. Particularly the part about who the Big Players are in DFM (see Question #9), and the part about what the Big Guys in EDA are going to do, or not do, about the Small Guys in DFM (see Question #10).
Oh yeah, and check out the part where folks are estimating the size of the DFM market (Question #11). Turns out everybody thinks it’s bigger than a breadbox, but probably not bigger than $500 million. There is a vote or two in there, however, for $1 billion or more. Hmmm. “Dollars for Marketing?” Should it be instead, “Dialing for Mega-Millions?”
7) Once again, stand up. Take a deep breath. Sit down.
8) Consider coming to the
Workshop for Women in Design Automation
at DAC. You think it’s just for the “weaker sex“? Think again. It’s for everybody/anybody who wants to learn about leadership, career development, career transitions, and balancing things like work and personal life. You already know how to do all that stuff? Lucky you.
Stars & Strikes Bowling Tournament, the Silicon Valley fundraiser. Last Saturday, May 12th, they were out in force at the “300 Bowling” alley in San Jose (who, by the way, donated their facilities to the event). And the folks from Cadence were not alone. Over 200 companies pitched in this year to support this fundraiser, including EDA folks like Denali, Magma, Synopsys, DesignAdvance, Clear Shape, LogicVision and
9) Finally, give kudos to Cadence. They’re the ones who, for 14 years now, have coordinated and seriously subsidized the annual
Si2 – many bowling in lanes right near Cadence’s. (Is that called bowling “adjacencies“?)
There were also lots of people from the San Francisco 49ers’ organization on hand, including most of the coaching staff, lots of hunkahunka players, and one or two sparkly 49er cheerleaders, as well. In fact, there were so many hundreds of people packed into that bowling alley between noon and 4 PM, the caterers might have feared they’d run out of food and beer, but I’m sure they didnt. The Cadence team looked far too organized to have let that happen.
Oh yeah, and there was a silent auction, and a live auction, and live music courtesy of Rockin/Rollin Ted Vucuravich (Cadence CTO) and The Chad Tuckers Band, and lots of other folks who appear to have brought the whole family to the event. And, as an added bonus, there was the amazing sight of huge football players bowling right along side some (slightly less bulky) software developers and CEOs, including Cadences Mike Fister, Denalis Sanjay Srivastava, and NVIDIA’s Jen-Hsun Huang.
I think you get the picture. It was pretty awesome. No wonder that last Saturday’s event raised over $1 million in the course of the afternoon. That’s a lot of money. This year’s recipient? The Silicon Valley Women’s Initiative, working to help lower-income women start businesses. The 2005 recipient was the Fisher House for families of wounded veterans on the campus of the Palo Alto VA Hospital. Well done, Cadence!
See you all in San Diego!
Design for Manufacturing – Once more, with feeling
Atul Sharan – President and CEO, Clear Shape
Chenmin Hu – President, Anchor Semiconductor
Dave Holt – CEO, Lightspeed Logic
Dave Reed – Vice President of Marketing, Blaze DFM
Gary Smith – President, Gary Smith EDA
Joe Sawicki – Vice President and GM of Design-to-Silicon Division, Mentor Graphics
John Lee – GM of Physical Verification Business Unit, Magma Design Automation
Kamal Aggarwal – Vice President of Marketing and Strategy, SoftJin Technologies
Michael Buehler-Garcia – VP of Marketing and Busn. Development, Ponte Solutions
Mitch Heins – Vice President of Business Development, Pyxis Technology
Prasad Subramanian – Vice President of Design Technology, eSilicon
Prashant Maniar – Chief Strategy Officer, Stratosphere Solutions
Rob Aitken – Fellow, ARM
Srini Raghvendra – Senior Director of Marketing for DFM solutions, Synopsys
Sudhakar Jilla – Director of Marketing, Sierra Design Automation
Tom Wong – Vice President of Marketing, Takumi Technology
Yervant Zorian – Vice President and Chief Scientist, Virage Logic
Ken Potts – Vice President of Product Marketing, Virage Logic
Questions and Answers – A Baker’s Dozen
1) DFM is not new, but some parts of it are newer than other parts. Please list the 3 oldest parts, and the 3 newest parts.
Atul Sharan – The oldest elements of DFM are Rules, Extraction Tables, and Spice Models. The newest aspects are Variability, Models, and a Model-based infrastructure that supplements a rule-based infrastructure.
Chenmin Hu – Three oldest parts: DRC, OPC, and PSM. Three newest parts: full-chip post-OPC verification, model-based litho-friendly design, hardware-accelerated litho simulation.
Dave Holt – Old Design Rules become New Design Guidelines. Old LVS/DRC become New LVS/DRC/DFM. Old PVT characterization becomes New 20+ corners characterization.
Dave Reed – Oldest: 1) Plain vanilla design rules; 2) Defect yield focus (via doubling, wide wires with slotting, end-of-line routing rules); 3) Resolution enhancement techniques (optical proximity correction, phase shift masks). Newest: 1) Electrical DFM (parametric yield focus); 2) Leakage power reduction (multi-Vt libraries; transistor gate-length biasing); 3) Process-aware analysis and optimization.
Gary Smith – The older parts are rule-based, the newer parts are model-based. Also, we are seeing many of the new tools use parallel processing to speed up their tools.
Joe Sawicki – Oldest: Physical Verification tools (DRC, LVS, Extraction, Recommended Rules); Optical Proximity Correction (OPC). Newest: Model-base DRC (the ability to create design rules both from complex equations, and full manufacturing simulations, in addition to traditional simple design rule syntax); Tools that combine layout analysis with layout improvements such as Critical Area Reduction and Critical Feature Improvement;
Model-based tools to simulate performance from “as-manufactured” layouts versus “as-drawn” layouts; Planarity (CMP) analysis integrated with Electrical DFM (extraction of electrical parameters from “as-manufactured” layout and planarity models used for post-improvement simulation/verification).
John Lee – Three oldest parts: Recommended rules, DFM fixing scripts based on DRC tools, Critical area analysis. Three newest parts: Lithography hot-spot analysis, Lithography hot-spot fixing, Lithography impact on timing/power.
Kamal Aggarwal – We at SoftJin define DFM to include all tools and techniques related to analysis and enhancements of design data for manufacturability purposes. This includes DFM tools that operate in post-layout (post tapeout) stage and also those that operate in the pre-tapeout stage. Conventional DFM tools include post layout DFM tools such as OPC/PSM (and other RET tools), and Mask Data Preparation tools. In our view, the new part to DFM includes 1) Use of manufacturability related information and concerns up in the design flow (at placement/routing stage or earlier), and 2) More sophisticated and high performance post-layout DFM tools needed
to solve the complex and computationally challenging problems at new technology nodes such as 65 nanometers and below.
Michael Buehler-Garcia – I think the intent of the question is old applications versus new applications. The core DFM issues/failure mechanism have always been there. The question is, which ones do the designers now need to also deal with – in addition to the fab? From a designer’s perspective, the “old/current” are Litho, CAA, and CMP. The new are the application of those issues beyond checking into how they affect core designer care-abouts, things like timing. In addition, new failure mechanisms like via etch will become part of the designers’ domain starting at 32 nanometers.
Mitch Heins – Oldest: 1) DRC; 2) DFM for Random yield limiters (wire spreading and redundant vias) which would include analysis for this in the form of CAA (critical area analysis); 3) RET (which includes OPC). Newest: 1) Litho hot-spot analysis (sometimes analogous to DFM analysis); 2) Statistical analysis; 3) Routing optimization. Note: Analysis and verification markets evolve before optimization markets.
Prasad Subramanian – Examples of the old DFM are DRC, metal fill, and antenna-related issues. Examples of the new DFM are wire spreading and widening, redundant via insertion, lithography-process check, etc.
Prashant Maniar – Old: Random defectivity-based characterization/analysis, Rules-based design/OPC/PSM, Ad-hoc layout optimization (e.g., via redundancy etc).
New: Process-model (litho/CMP) based extraction/timing analysis/routing, Parametric yield analysis, Variability modeling.
Rob Aitken – Three oldest: Design rules trading off manufacturability and density; Critical area analysis; Via/contact doubling. Three newest: Lithography simulation as part of layout; Quantitative links between methods (e.g., critical area, improved lithography, and CMP fixes); Quantitative links between DFM and power/performance numbers (e.g., poly/metal/device extraction).
Srini Raghvendra – DRC rules such as those of space, width, and density checks are examples of older’ DFM. Newer DFM steps include lithographic, CMP, and stress-analysis checks.
Sudhakar Jilla – Oldest parts include OPC simulation. Newest parts include DFM during design and new ways to model DFM.
Tom Wong – What is old? a) Litho check, OPC, talking about the lithography gap; b) CMP, CAA analysis; c) Wire spreading, contact doubling. What is new? a) DFM to address process variations is new. In the past, DFM addressed MDP TAT, printability (RET/OPC), and random defects (CAA); b) Convergence of DFM and DFY: The ultimate measure of success is YIELD! So All DFM tools must show tangible yield improvements. End-users are NOT interested in just detecting new litho problems (hot spots). They want the tools to fix those new problems after they have been detected. c) Model-based verification in addition to DRC: For any sub-wavelength design, passing
DRC can no longer guarantee working silicon or good yield. This is where model-based verification and litho analysis come in, but analysis alone does not help. Automatic problem fixing is required. d) Applying physical layout optimization to DFM. Designers are now able to use new point tools to detect DFM issues such as CAA analysis, litho analysis, and leakage analysis. But they have no way of trading-off one versus the other while fixing these identified problems. Only physical layout optimization addresses fixing while taking trade-off into account. This can be rule-based and/or model-based. e) There are simply too many hot spots at 65 nanometers and 45 nanometers. Hot-spot fixing must
Yervant Zorian & Ken Potts – DFM is the idea that design choices must be made in the manufacturing context. DFM enables design optimization to meet product specification, while achieving acceptable post-manufacturing yield. In the early days, we didn't talk about DFM. However, we still introduced tools that modeled the manufacturing realities for the designer. Early examples of this are SPICE, Extraction, and DRC. Although today we don't necessarily think of those as DFM components, they were created to ensure that the desired circuit behavior was achieved post-manufacturing. With the advent of the nanometer-design era, the atomistic, process, and temporal variations
have become first order in the design and manufacturing equation. Statistical models to predict circuit behavior as well as to predict yield are the newest areas of DFM.
Atul Sharan – Yes, Clear Shape Technologies is a DFM vendor.
Chenmin Hu – Anchor Semiconductor is a DFM solutions provider.
Dave Holt – No. We are a semiconductor IP vendor. Our most popular IP is mask-reconfigurable logic. The regular structure of the tile-based architecture used in our reconfigurable logic helps reduce lithography and stress-related variability challenges at nanometer-scale process nodes. This design approach, used in conjunction with an industry leading tool (such as Clear Shape's InShape), significantly reduces the DFM closure task for a design team, allowing them to focus their efforts on the design.
Dave Reed – Yes. Blaze was the first "electrical DFM" company focused on maximizing parametric yield for sub-100 nanometer chips. Blaze was the first pure-play DFM company to deliver customer silicon in March 2006.
John Lee – Absolutely yes.
Kamal Aggarwal – Yes, we are a DFM vendor but in a unique way. SoftJin offers building block (EDA components) that enable development of post-layout DFM tools. Our EDA component-based customized tool business model is different from the conventional standard product-based business model.
Michael Buehler-Garcia – Ponte is a DFM vendor.
Mitch Heins – We are an EDA supplier focusing on solving DFM issues during the design process. If DFM is defined as a discipline during the design flow (not post-GDSII) the answer is YES.
Prashant Maniar – Our tools primarily focus on characterizing and modeling parametric variability and using these models to reduce impact of variability on parametric yield and performance of a design. “DFM” has evolved into a “catch-all” acronym. To date, DFM vendors have taken the approach to utilize a model of defects or physical process step (e.g., litho, CMP) during layout analysis. Our Design for Yield (DFY) approach is an “electrical-metric based front-end” approach that enables designers to quantify the impact of variability on design performance and parametric yield. If the ultimate goal of DFM/DFY is to ensure that the design can
be manufactured with high yield, then Stratosphere Solutions fits under this umbrella.
Rob Aitken – No, ARM is a DFM user and includes DFM as part of its physical IP products.
Sudhakar Jilla – We are a DFM-only vendor. We address DFM as a part of place and route.
Tom Wong – Takumi Technology is a DFM vendor. Takumi offers software that can automatically repair hot spots on GDSII layouts by leveraging manufacturing data to address hot spots on cell and full-chip designs to improve device performance and yield. Takumi also offers design-driven defect analysis software for mask-defect analysis.
Yervant Zorian & Ken Potts – In the traditional EDA sense, no, we are not a DFM tool vendor. Virage Logic is part of the DFM ecosystem. The company provides the STAR Memory System that drastically improves SoC manufacturability and yield optimization. Customers such as Agere have seen yield improvements of up to 250 percent using the STAR Memory System.
3) In 20 words (max!), what does your tool do?
Atul Sharan – Clear Shape's InShape/OutPerform enable designers to perform variability-aware analysis and optimization based on true silicon behavior, maximizing process technology utilization.
Chenmin Hu – NanoScope is a pattern-centric platform with model-based simulation that enables hot-spot identification and layout optimization at design and manufacturing steps.
Dave Reed – Blaze MO dramatically reduces leakage power on sub-100 nanometer chips without requiring major disruptive changes to the design flow.
Joe Sawicki – Calibre nm platform provides user interface/data integration foundation for DFM toolset: physical verification, RET, OPC, MDP, design-centric tools (hot-spot detection, CMP analysis/fixing, CAA/fixing, critical feature analysis/fixing).
John Lee – Physical and electrical DFM prevention, correction, and analysis.
Kamal Aggarwal – Nirmaan, is a software development toolkit that enables semiconductor companies to develop post-layout DFM tools. We also offer tools for layout/mask data compression, comparison, and translation.
Michael Buehler-Garcia – Ponte provides solutions that allow designers, etc., to assess the impact of process variability and customize their DFM rules accordingly.
Mitch Heins – Our tool takes into account manufacturing models DURING the physical design flow to produce optimal routing QoR [Quality of Results], particularly on performance and yield.
Prashant Maniar – Our suite of products characterizes and models parametric variability and utilizes these statistical models to analyze a circuit’s statistical performance.
Srini Raghvendra – Our PrimeYield tool suite analyzes designs for DFM issues such as litho, stress, and CMP, and links to upstream design tools to help fix the problems.
Sudhakar Jilla – It is a P&R system which addresses variations in design modes, process corners, and lithography/CAA [critical area analysis].
Tom Wong – Takumi Enhance improves yield using automated, cost-aware, 2D layout optimization that can analyze, trade-off, and fix various layout hot spots.
Yervant Zorian & Ken Potts – Our system, the STAR Memory System, performs diagnostics, debug, and repair to improve reliability, manufacturability and yield.
4) When was the last time you talked to a real designer?
Atul Sharan – Today. Also, yesterday, and the day before. I talk to designers every day.
Chenmin Hu – We are constantly talking to designers to get their feedback on our products. We talked to them as recently as this week.
Dave Holt – Today. We have several ongoing projects at 65 nanometers and 45 nanometers with large IDMs (“real designers” in your parlance) using our mask-reconfigurable IP. There are multiple program reviews with different customers each week (2 different customer meetings this morning, for example).
Dave Reed – Today. We are in constant contact with our customers and talk to them everyday.
Gary Smith – Today at 5:45.
Joe Sawicki – We are in constant contact with our large installed base of physical verification (Calibre) tool users, which includes designers who must achieve DRC-clean designs. Our installed base includes foundries, IDMs, and fabless design houses. It’s our interaction with these users that enables us to identify new challenges and needed capabilities to provide manufacturing process insight back to designers, so they can take focused action to improve yield through design improvements.
Kamal Aggarwal – As a software toolkit provider, we regularly speak to our immediate customers that are in-house EDA groups in semiconductor, mask makers, or foundries. We also interact regularly with the end users of our tools which are tapeout engineers in IDMs, mask makers, foundries. As part of the side of our business, which is custom tool development for specific requirements of semiconductor companies, we talk to designers for their unique and emerging needs.
Michael Buehler-Garcia – Every day! Ponte has paying customers using our products at multiple customer sites.
Mitch Heins – We talk to them every day, as we firmly believe that great tools can only be developed with actual designs and real user feedback.
Prasad Subramanian – We are designers.
Prashant Maniar – Today. Our company philosophy is to engage early adopter customers right from the development of the product concept, and to continue receiving feedback at every stage of product and business development.
Srini Raghvendra – A few days ago. We are in constant touch with a number of leading-edge designers.
Sudhakar Jilla – We talk to our customers, i.e. designers, on a daily basis.
Tom Wong – Yesterday. We have worked with customers on a daily basis over the past three years since the company was founded. Companies such as Renesas, Toshiba, and NEC have deployed Takumi products into production.
Yervant Zorian & Ken Potts – The precise answer is today. However, that is only a piece of the story. The ecosystem requires that the ongoing dialogue be between the manufacturing domain, the design domain, and the IP domain. This dialogue enables the expertise of each area to integrate and then manifest as value to the designer. In the case of Star Memory System, designers use our tool everyday to improve their time to volume.
5) When was the last time a real designer used your tool?
Atul Sharan – The same answer as #4. Today.
Chenmin Hu – We have designers that are using our tools on a daily basis to analyze DFM issues to get improvement on yield.
Dave Reed – Today. We have numerous customer engagements in process right now, and are continually adding new names to our growing list of customers. Our first customer tapeout was in November 2005; first customer silicon was in March 2006.
Joe Sawicki – All three areas of DFM tools from Mentor (physical verification, manufacturing for design, and design centric) are being used daily by real designers on real designs at leading IDMs, fabless design houses, and foundries. In physical verification, Calibre is the industry leading tool for DRC sign-off. In MFD, Calibre nmOPC and OPCverify are among the leading computational lithography solutions. Mentor design-centric DFM tools are broadly deployed at leading companies such as AMD, UMC, Infineon, Chartered, IBM, and STARC.
John Lee – Today. We have production users at top customers worldwide.
Kamal Aggarwal – Since our core product, Nirmaan, is in the post-layout DFM space, a conventional RTL-to-GDSII designer does not use our product. However, our layout/mask-data translation and compression tools are used by physical design engineers. Our customized tools, developed as part of our customized tool development services, are used by designers across the design flow, from system level down to physical design.
Michael Buehler-Garcia – This morning, as they called us with questions on our new release.
Mitch Heins – Currently, we are engaging with beta customers, some of which are starting to test our tool. We anticipate a production release in late summer 2007
Prashant Maniar – Several customers are using our characterization technology at 65 nanometers and 45 nanometers. Our next generation tools will be available in 2H07.
Srini Raghvendra – This morning. Our tools have been deployed in production flows, and we expect that they are being used all the time.
Sudhakar Jilla – Our tool is being actively used in real tapeouts at 90 nanometers and 65 nanometers.
Tom Wong – Today. There is major collaborative work in progress with foundries, fabless companies, and mask shops. Takumi recently announced a partnership with Dai Nippon Printing to address how to use DFM methods to reduce cost of masks.
Yervant Zorian & Ken Potts – Real designers are using our STAR Memory System tool every day.
6) If never, when do you think the first time will be?
Editor’s Note: Apparently none of the “panelists” fell into this category, so there were no answers offered to this question.
7) Many point tools today are not fully integrated into the flow. Why should DFM tools be criticized for not being fully integrated into the flow?
Atul Sharan – Clear Shape does not have a problem with integration into the design flow. This is usually a general response from some of the large EDA vendors who do not have competitive DFM solutions.
Chenmin Hu – It is a real issue for designers’ acceptance of DFM tools. Many DFM tools are developed by small start-up companies that have no control of the integrated flow. Some of these point tools employ totally new technologies. As long as these DFM tools offer unique and strong value to address DFM issues that are not available through the major flow tool suppliers, the “not being fully integrated into the flow” will be a secondary issue.
Dave Holt – Today's flows are complex. Let's look at what the typical design team is trying to do in the flow's "backend":
b. signal integrity closure
c. achieve ATPG coverage goals
d. floorplan convergence, die-size reduction
e. achieve power (active and passive) targets
f. IR drop analysis and power grid design/re-design
g. DFM closure
And all of this is likely being done for a product targeting a consumer product that has a short lifecycle and absolute deadline as to the "beginning of the selling season." Hit it, or punt and move on to the next design cycle. And these must be done across 20+ corners in today's environments. Fixes for many of these cause problems with others. If the tool flow is not integrated, mostly or completely, then the design team plays "whack-a-mole" trying to fix one problem, then another, then another, etc. The term "constant-time-to-completion schedule" comes to mind.
Dave Reed – It is the vendor's responsibility to provide everything a designer needs to adopt a new tool into their flow. This means providing a complete solution, from library preparation to final chip-level signoff, along with the foundry enablement and design-to-manufacturing interface required for customers to put a DFM methodology into practice. At Blaze, we've spent a lot of time and effort making sure that our products work seamlessly within industry standard design flows. Our customers have been very happy with how easy our tool is to adopt.
Joe Sawicki – The objective of DFM tools is to improve TTM and manufacturing yield. Tools that are not integrated into design flows create more work for designers and distract them from their primary objectives. For this reason we have an R&D focus on integrating our solutions into the leading design environments and industry standard database formats. It is important to ensure true interoperability between DFM and traditional design environments. This enables designers to establish best-in-class solutions for each design stage, not just for the stage in which a single EDA vendor excels. Ideal DFM tools provide immediate and intuitive insight into how designs are
rendered in the manufacturing process, and provide directed guidance to designers on what specific design improvements will provide the greatest increase in overall yield.
John Lee – Timing optimization is tightly integrated into implementation tools today. So should DFM.
Kamal Aggarwal – I don’t think that is a major issue. For companies who are offering point tools, the tools are integrated into flows through standard file/database formats. Apart from that, more direct integration through APIs would happen on a case-by-case basis based upon customer demand.
Michael Buehler-Garcia – DFM tools are now migrating from point tools to integrated solutions, just as the core EDA tools did.
Mitch Heins – We believe that the DFM point-tool integration to mainstream flows is lagging because a significant change is needed in the existing infrastructure (libraries, models, formats, etc). The large EDA suppliers can drive such changes, but are lagging on innovation. The small DFM suppliers are showing major innovations, but are lacking the resources to drive such change. The large IC suppliers must take the lead to create an integrated infrastructure.
Prasad Subramanian – The drawback with most DFM tools is that they are used rather late in the design flow – after timing has been closed. The impact of changes to the design to correct for DFM-related problems is hence unknown.
Prashant Maniar – To deliver high customer value, yield/manufacturability analysis and optimization have to be pervasive in the design flow. The cost of design is already sky-rocketing. Lack of integration further increases design cost and creates a barrier to adoption of key technologies required to migrate designs to smaller geometries. Lack of integration is a lose-lose for everyone.
Rob Aitken – The same reason any tool should be criticized. Integration into a flow is what makes tools usable in production, instead of being science projects. That said, some DFM approaches require significant changes to the standard flow. In ARM’s case, a major consideration is whether a DFM tool will be used by a layout designer as part of design, or whether it will be used in a post-processing step. The integration, usability, and flow needs are very different depending on where/how it will be used.
Srini Raghvendra – DFM impacts yield and productivity. And DFM, more than most issues, needs a “holistic” approach. A point-tool approach to DFM is problematic, because you could ping-pong between several competing issues if you don’t look at DFM as a set of interrelated constraints.
Sudhakar Jilla – Because stand-alone DFM tools just identify the problems - they do not help the designer fix the problem. An integrated solution identifies and fixes the problems.
Tom Wong – DFM problems are not point problems and cannot be addressed as a point solution. It is a flow issue. Having said that, point tools are beginning to be integrated into DFM flows at major IDM and foundries. It is just that the flows are NOT owned by the three major EDA companies. They also provide point tools, just like the smaller DFM companies, to be a part of a larger "customer DFM" flow. Each IDM and foundry has its own unique flow based on their set of internal and commercial tools that were qualified in the past. DFM tools have to co-exist with tools that are already in the fab.
Yervant Zorian & Ken Potts – It’s a productivity issue. The tools must be integrated to meet time-to-market and yield requirements for optimum productivity and manufacturability.
8) What still needs to happen to make DFM a standard part of any/all design flows?
Atul Sharan – At 65 nanometers, mainstream designers need to realize two things: 1) They can get more out of 65-nanometer and even 90-nanometer process technologies if they account for variability, and 2) Some of their design failures today are actually due to variation in the behavior on silicon versus drawn-GDS. And at 45 nanometers, there will be no choice
DFM will be a standard part of flows.
Chenmin Hu – I would state the problem in a different way: What needs to happen to make the “standard” design flow adapt and incorporate DFM tools? Standard design flows will have to address the problems that the industry faces today, and those will only get worse at more advanced nodes. Most important is the pattern-to-silicon transfer. Whether using integrated tools or point tools, the design flow will have to ensure the design output fits the manufacturing process windows.
Dave Holt – The leading DFM companies will be acquired by the leading EDA companies, and the flows will be merged.
Dave Reed – Foundries must take the lead; they must adopt and endorse key, high-value DFM technologies and make them widely available to their customers.
Gary Smith – If you really mean "design" flow, it will take the silicon providers to insist upon it. If DFT was an example, it could take 8 years.
Joe Sawicki – First, the value of DFM needs to be validated through use in real production environments at major design firms and foundries, and documented with real production yield data. This is happening today with many Mentor Graphics customers. Second, DFM tools need to be tightly integrated with the design environments currently used by IC designers. The Calibre platform is integrated will all leading design environments. Finally, the tools need to have designer-friendly interfaces that give very specific and intuitive guidance on how designs can best be improved, or the ability to make fixes automatically. This is a key focus of Mentor’s DFM approach, and the
reason we have integrated our tools through the Calibre platform and industry standard data formats. In other words, the goal is to make designers’ lives easier and more productive in terms of the overall “go to market” process.
John Lee – 45 nanometers is the best opportunity for DFM to become part of all design flows.
Kamal Aggarwal – The post-layout DFM tools such as OPC and PSM are already part of the standard post-tapeout flow at today’s process nodes. For the pre-tapeout DFM tools, some of the must-have DFM features are also becoming part of the standard IC implementation tools of large vendors.
Michael Buehler-Garcia – The key is which design flow are we speaking about, and at what level? Most P&R tools already have DFM options included, and as such, I would suggest that DFM is already part of the SoC design flow. Likewise, is the integration of DFM into a flow going to be the integration of an actual new tool, or addition of the DFM issues as new cost functions into existing tools? Pont tools are still the current mode while this sorts itself out.
Mitch Heins – We need a few high-profile chips to die in the fab when they are taped out meeting current design rules. Or, to have a high-profile company lose market share to a competitor because they couldn't get enough parts out of the fab (read “yield issues“) to meet customer demand. Generally speaking, we need to cross the chasm between the domain expertise of the designers, product engineers, and process engineers along with the CAD support teams. This is not only a flow issue, but a collective effort to gather the knowledge required and build such flows over time.
Prasad Subramanian – DFM needs to be an inherent part of the physical design process. It needs to be integrated into placement, routing, and other physical design steps so that the design is correct by construction. This will enable the full impact of DFM to be considered during design.
Prashant Maniar – Focus on designer “actionability”. Designers are typically concerned about performance (be it speed, power, etc.) but can no longer ignore the impact of design tradeoffs on parametric yield. For parametric yield to become a pervasive metric in the COT/custom/analog design flows, several things need to occur: comprehensive process characterization, design-flow-relevant variability modeling, and accurate/fast statistical analysis of design. There are several gaps in each area.
Rob Aitken – The biggest issue with DFM is settling on the flow of information from the fabs, through the tools, to the users, and in some cases back to the fab. Several approaches are being tried at the moment, and it’s not clear what the final answer is. But without some approach, no DFM tool is much use.
Srini Raghvendra – Not all flows needs to retrofitted to be “DFM aware“, but the pieces are in place. Some design flows (90-nanometer and older nodes, for example) will not need to worry much about DFM flows. 65-nanometer design flows will need detection flows, but not necessarily fixing flows because the number of hot spots is quite small. 45-nanometer design flows will probably all be “DFM aware”.
Sudhakar Jilla – Ability to model the DFM effects.
Tom Wong – DFM is a problem statement. DFM problems can be fixed in many places in the flow depending on the needs of the end user and the type of problem. For example, random defects can be fixed at library development, place and route, or post-OPC stage. The methods are different; cost of fixing is different, but the results are the same. It is about improving yield at the end of the day. DFM will be standard when actual, meaningful yield/defect data is available and being used by the DFM tools to enhance yield. With IDMs it was relatively easy to incorporate DFM flows since the proprietary data did not have to leave the company. The foundries are progressing very well in
encrypting the proprietary data and making it available on an as-needed basis to the DFM tools.
Yervant Zorian & Ken Potts – Standards are required to give the industry a common metric. It is very hard today to know where the point of diminishing return is for DFM optimizations. Once the measurement is defined, the DFM analysis and optimization must be applied in the initial design phase (source level) vs. later in the design phase (transistor level). Finally, the architecture and function need to be specified with DFM in mind.
9) Who do you consider to be the big names (even if they're small companies) today in DFM?
Atul Sharan – Clear Shape Technologies. (We'd be demented to say anything else.)
Chenmin Hu – Both Mentor Graphics and Synopsys have been important players. We believe that Anchor Semiconductor is one of the very few DFM start-ups with serious revenue, long-term customers, and with their DFM products in customer production flow. ASML has just entered the market as a noticeable player with its acquisition of Brion.
Dave Holt – Clear Shape and Blaze DFM are the two who both seem to be adding real value.
Dave Reed – Blaze DFM (the electrical DFM company).
Gary Smith – Mentor, Clear Shape, Blaze DFM, ASML-Brion. But, look out for some of the new start-ups.
Joe Sawicki – DFM is essentially an extension of physical verification, and Mentor Graphics is the leading supplier of PV tools. We provide a broad and rapidly growing array of DFM tools that work in the customer’s chosen design environment. Expanding from our strong base of Calibre nmDRC products, we are extending our offerings to cover the entire DFM space. Mentor has a major R&D emphasis in DFM. We’re leveraging the Calibre Platform to produce innovative solutions to the challenges our existing customers are experiencing, and we’re unique in providing integrations with all major design environments, as opposed to captive DFM solutions.
John Lee – Magma, Synopsys, and Mentor.
Kamal Aggarwal – Apart from the large EDA companies and the top equipment vendors, a few start-ups such as Blaze DFM and Clear Shape have gained prominence in the last year or so.
Mitch Heins – Blaze DFM, Brion (ASML), Clear Shape, Magma to some extent, Mentor, PDF (“old” DFM parts), Ponte, Pyxis Technology (“new” DFM parts), and Synopsys.
Prasad Subramanian – Magma and Mentor Graphics.
Prashant Maniar – Mentor Graphics, PDF Solutions, Synopsys, Clear Shape, and of course, Stratosphere Solutions.
Srini Raghvendra – We (Synopsys) are an important part of the DFM ecosystem for several IDMs, foundries, and fabless companies.
Sudhakar Jilla – Mentor, Synopsys, Clear Shape.
Tom Wong – Takumi Technology – products are deployed into manufacturing at major semiconductor companies. Blaze DFM – coined the phrase electrical DFM. Clear Shape – publicized the phrase “contour-based” simulation. Being a big name is about customers actually paying for the tools and actually using them in production. It is not about getting designed into a flow for MarCom promotion.
Yervant Zorian & Ken Potts – Mentor Graphics (OPC), Clear Shape (layout/backend optimization), PDF Solutions (test chips), and Virage Logic (physical IP optimized for DFM).
10) Will the large vendors in EDA let small vendors in DFM thrive, or will they just buy them?
Atul Sharan – I will be curious to see the large EDA vendors answer your question.
Chenmin Hu – DFM goes far beyond EDA applications. Quite a few DFM start-ups have founders with manufacturing and equipment backgrounds. We expect to see more acquisitions, not only by the large EDA vendors, but also major equipment companies when the market picks up. There are still possibilities for small venders in DFM to thrive.
Dave Holt – The answer is not an "or" answer. It's an "AND" answer. The large vendors will let them thrive by letting the shakeout happen, and then they will buy the winners/survivors.
Dave Reed – Recently, some DFM companies have been acquired, or have tried to position themselves to be acquired, by large EDA vendors. Others have been bought by equipment manufacturers. Here at Blaze, we believe that there is a desperate need for a pure-play DFM company – one that understands both design and manufacturing and how to leverage that multi-disciplinary expertise to drive design requirements into manufacturing and bring manufacturing awareness into design.
Gary Smith – There is room for one large independent DFM vendor. The rest will come from the Big 4.
Joe Sawicki – Mentor develops more of its own technology and invests more in DFM R&D than its major EDA competitors, and we have a much larger R&D effort than DFM start-ups.
John Lee – The small vendors will either be acquired (look at who's not on the list in Question #9), or disappear.
Kamal Aggarwal – One cannot predict the future, but EDA history tells us that the industry is acquisition intensive and there is high likelihood of successful vendors getting acquired by large vendors.
Mitch Heins – Large EDA vendors will continue their tactics in the areas they perceive to be core competencies, and will react by buying DFM start-ups to the extent they prove a lynchpin technology with revenue from major accounts for which they compete for market share.
Prasad Subramanian – I believe they will buy them, for the same reason as in #8. DFM needs to be an integral part of the design flow and not an afterthought.
Prashant Maniar – This totally depends on what the small and large vendor is focused on. If the small vendor is building incremental innovation, then they will not survive. If the small vendor is focused on disruptive technologies (that fit well into the design flow
) and can build a sizeable market footprint, then they will thrive.
Rob Aitken – Because of the data delivery issues, the question is not entirely up to the large EDA vendors. The fabs also have a say.
Sudhakar Jilla – Big company strategies might be dictated by business and technical reasons rather than a technical issue. If they don't have something that the customers need, they will either develop it or buy it ready-made.
Tom Wong – Today, the market is fragmented. Neither the big nor the small guys have the entire DFM solution. They have to work together to move the industry forward. I think they will co-exist for sometime. Takumi has layout optimization for yield enhancement, automatic hot-spot repair for full chip and library layouts. Mentor has LFD, a detection tool for CAA and litho, but no correction capability. Clear Shape has InShape, another full chip litho hot-spot analysis tool; but no correction capability. Blaze DFM has electrical DFM tool, but relies on OPC tool to perform the layout changes. Both big and small players are trying to come up with products that address various
segments of the DFM market. Ultimately, it is a question of having a viable product that solves a real customer problem and has a place in customers' DFM flows. This establishes the value of such a product. If that happens to come from a small EDA vendor, that vendor is a clear target for acquisition. This has been the EDA eco-system for the last 20 years. There are clearly a few small EDA players with promising DFM products, and it is just a matter of time before they will be seen as "success" from both revenue and market position points of view.
Yervant Zorian & Ken Potts – They will likely let the EDA DFM tools provider thrive until the market matures and then consolidation and M&A activity will occur.
11) How large is the DFM market? A quantitative answer, please, not a qualitative one.
Atul Sharan – Joe Sawicki of Mentor predicted the total DFM market would be a $1.5 billion market in the next few years. We are with him on this one and even if he is 50% right, it constitutes a huge opportunity!
Chenmin Hu – It depends how you define the DFM market. The total market most likely is around $300-400 million. That’s $200 million from the manufacturing side and $100-200 million from the design side.
Dave Reed – For the semiconductor industry, parametric yield loss can conservatively be measured at $10 billion per year. By whatever amount DFM solutions can reduce that loss, that is the size of the electrical DFM market.
Gary Smith – We are just finalizing out survey, but it should come in between $150 million and $180 million.
Joe Sawicki – From the EDAC database:
Extraction: $90.6 million
Subtotal: $314.1 million
Mask Data Prep: $36.8 million
Subtotal: $174.2 million
Kamal Aggarwal – Our estimate, based upon secondary sources, is that the post-layout DFM market including RET and MDP tools is close to $200 million. We don’t have estimates for the pre-tapeout DFM tools market.
Michael Buehler-Garcia – Sorry, but the DFM market is too fractured, and as per the questions above, needs to link other flows to provide a single TAM number for DFM.
Mitch Heins – Old DFM market estimated between $300-500 million. New DFM market has the potential to reach a billion dollars (subject to new business models) if you reach both up and down the design and manufacturing chain.
Prasad Subramanian – I’m guessing it is less than $100 million.
Prashant Maniar – $250 million to $400 million, depending on what you lump into it.
Sudhakar Jilla – $200 million to $500 million, based on how you slice and dice it.
12) Why is everybody from the EDA vendors, to the press, to the tools users, fabs, fabless, and IDM guys so hot and bothered by DFM?
Atul Sharan – Because the PROBLEMS are REAL and the laws of PHYSICS are REAL. Variation due to lithography is real.
Chenmin Hu – There are fundamental underlying problems that occur with every new technology adoption process. Where DFM is concerned, it’s fear of the unknown brought on by the reality that manufacturing-process variability has exceeded the tolerance of targeted design performance. New design challenges demand a paradigm shift in the design-to-manufacturing ecosystem in the relationship between design and manufacturing. In other words, the EDA vendors and fabless designers as well as the fabs all must exit their comfort zones to get a handle on DFM. For example, the fabs and IDMs foresee potential manufacturing problems with new advanced processes and are already
raising red flags. In turn, the EDA vendors are trying to understand these manufacturing problems that have been fairly foreign to them until recently so that they can develop DFM tools to remedy the impending manufacturability and yield crisis. And tool users need to take steps to incorporate DFM tools in their new design flow.
Dave Holt – Because it is in everyone's interest to keep Moore's Law moving forward. And right now the economics of moving each step down the lithography curve imperil more and more designs as they won't have sufficient ROI. Thus, anything that can be done to improve the economics of nanometer-process nodes allows more business (design starts) to move to those processes.
Dave Reed – DFM has been on the radar screen for a long time, but it wasn't until recently that things such as leakage power became critical. At 130 nanometers, leakage power was negligible, but at 65 nanometers, leakage can account for more than 50 percent of a chip's total power consumption. When something goes from non-existent to acutely critical in such a short period of time, it gets people's attention.
Gary Smith – New problems, market inhibitors, new challenges, new opportunities to stay ahead of the fabless competition.
Joe Sawicki – The industry is excited about DFM because it directly affects TTM and manufacturing yield, the primary determinants of IC profitability. Foundries and designers working at 65 nanometers and beyond are realizing that designs at these geometries are much more sensitive to manufacturing process variations than in the past. Design rules can’t be specified as simple constraints any more. They’re now either complex multivariable equations or based on sophisticated simulations of the manufacturing process itself. What designers need are tools that give them insight into the impact of manufacturing variability on the yield of their designs. There’s a
great opportunity to have a big, positive impact on manufacturing yield at nanometer-design nodes by making relatively simple, and ideally automated, modifications to the physical design. Effective DFM tools provide specific guidance to designers and offer a complete solution that covers the general checks found in a physical verification tool, as well as the specific checks found in model-based solutions.
John Lee – Yield is a struggle for the fabs at 65 nanometers. 45 nanometers won't be easier.
Kamal Aggarwal – It’s one of the areas where new challenges and opportunities for EDA lie, which explains interest from the EDA community. Some of the DFM challenges at today’s process nodes are blurring conventional boundaries and forcing enhanced information exchange amongst fabs, fabless companies, and EDA companies. That explains the additional interest from various players in this space.
Michael Buehler-Garcia – Two reasons. (1) Technical: The impact of process variability as we migrate to smaller nodes is impacting “core designer issues” like timing, speed, and power. When DFM is tied to these core issues, it impacts all designers versus “the DFM Team”, whomever they are! (2) Business: DFM requires all elements of the design ecosystem to work together, so developing a business model where everyone gains is the end game. DFM will drive us to this model ahead of everything else.
Mitch Heins – Foundries are bothered because they can regulate profit margin based on defect density and yield. IDMs are bothered because they want to maximize fab "useful capacity utilization" for $3 billion fab ROI. EDA start-ups are bothered because it's not focused on the RTL-2-GDSII business of the broadliners. EDA leaders are bothered because of potential for new business models (Cadence CEO Mike Fister, Q1-07 analyst session). The press is bothered because of "Dollars For Marketing" and potential for innovation and growth. The tools users are bothered because all of the above are bothering them. If I were a design manager, I'd just be worried about whether or not my
chip was going to work. If you look at the physics of 45 nanometers and 32 nanometers, you have to have a lot of things work perfectly for your part to even work, let alone at speed, power, etc.
Prasad Subramanian – The resolution of the manufacturing equipment is unable to keep up with the shrinking geometries. As a result, patterns drawn in the mask are not necessarily the same as those that appear in silicon. This, along with the increase in process complexity, creates many more opportunities for manufacturing problems. DFM is the key to resolving these issues.
Prashant Maniar – Customers (fabs and designers) are struggling to migrate designs to smaller geometries to meet end-consumer requirements. Failure of successful migration has a significant economic downside to the industry. Fabs are trying to drive yields (defect limited, systematic, parametric) higher and designers are trying to make sure they get predictable performance and adequate yield for each part. This creates an opportunity for EDA vendors to sell new tools, and the press to write compelling stories for the industry
Rob Aitken – DFM is addressing a genuine issue: Without feedback from the manufacturing process, it’s difficult to draw the right balance between standard optimization criteria (power, performance, area) and yield/manufacturability. Each generation from 130 through 45 nanometers has needed additional information to be passed back and forth. The information exchange is happening, but tools make it easier and help it fit in the flow.
Srini Raghvendra – DFM addresses yield and time to market. Both of these issues directly affect our customers’ top and bottom lines, thus the intense interest.
Sudhakar Jilla – DFM is a new phenomenon caused by the current manufacturing limitations. Moore's law and manufacturing physics are not in sync. DFM calls for a new breed of tools to address the problem and hence the excitement.
Tom Wong – 1) Because you CANNOT make silicon yield if you do not have DFM solutions. It is all due to the lithography gap – we are using a 193-nanometer light source to print 90/65/45-nanometer silicon. 2) Because the VCs have invested a lot of money in DFM start-ups over the last 3 years. 3) Because Brion was acquired for over $250 million.
Yervant Zorian & Ken Potts – The challenges of next generation device physics are driving the increased need for DFM. This is readily apparent to all participants. The ecosystem will embrace DFM capabilities that take a system approach to the solution space, such as the Star Memory System.
13) Will you attend any DFM sessions at DAC? If so, which ones?
Atul Sharan – Not sure about any others, but I will definitely attend the sessions where several of Clear Shape's DFM customers will present to designers about their DFM approaches in our own suites!
Chenmin Hu – Yes, the DAC Pavilion Panel: “DFM: Prevention or Cure”.
Dave Holt – We have technical folks who will be in attendance. I'll be working on the floor meeting with customers, partners, and the press.
Dave Reed – Not only are we attending, but we're hosting a number of sessions. Hands-on tutorial: "Standard Cell Library and Hard IP Design" presented by Blaze DFM, Ponte Solutions, and Sagantec (June 4, 9am - 12pm, Room 11A). Hands-on tutorial: "Manufacturing-Aware Optimization" presented by Blaze DFM and TSMC. (June 6, 2:00-5:00 PM, Room 11A). Our engineering staff will also be presenting the following technical papers and tutorials: "Modeling for DFM/DFY" (June 4, 12:00 - 5:00 PM, Room 6A); "Line End Shortening is not Always a Failure" (June 5, 4:30 - 6:30 PM, Room 6F); "How Design Meets Yield in the Fab" (Friday full-day tutorial, June 8, Room 6D).
Gary Smith – Probably not.
Joe Sawicki – Mentor is giving a whole host of presentations and demos at DAC. We’ll have presentations at the Mentor DFM kiosk in the Mentor booth, presentations in the Mentor booth suites, and demos and presentations in the Intel, Common Platform, and UMC booths. In addition, IBM will be describing how they use Mentor DFM tools within the Common Platform Alliance at the Mentor Network event at DAC. (Monday, June 4, 4:00 at the Mentor booth).
Kamal Aggarwal – I plan to attend the Panel discussion entitled, “DFM – Prevention or Cure”.
Michael Buehler-Garcia – My schedule is not finalized yet.
Mitch Heins – Don't know yet.
Prasad Subramanian – It is unlikely I will attend any DFM sessions. I will spend more time talking to the DFM tool vendors instead.
Prashant Maniar – Yes. Several
Rob Aitken – Yes, but not sure yet which sessions.
Srini Raghvendra – I haven’t planned my DAC schedule yet.
Sudhakar Jilla – DAC DFM tutorials.
Ken Potts – Virage Logic’s Yervant Zorian will be a panelists in a session about linking design with back-end test.
Editor’s Note: Thanks to Ed Lee of Lee PR for help and commentary with regards to the questions used in this survey.
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-- Peggy Aycinena, EDACafe.com Contributing Editor.