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April 23, 2007
DATE 2007: Secrets et Surprises à la Côte d'Azur
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor


by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


Is there a more gloriously beautiful place in the world than the French Riviera? Any other locale that so completely defines glamour, luxury and the good life – beautiful people, balmy breezes, and azure seas.



Fortunate the folks, then, who attended the 10th annual European Design Automation and Test Conference in Nice this past week. Because, short of an azure sea or two, DATE lived up to all of the promise of the South of France. There was glamour at the parties, luxury in the endless booth food and wine, balmy breezes rustling through the palm trees lining the street outside the Acropolis Convention Center, and beautiful people everywhere. If you needed azure seas, however, you were out
of luck.


The Acropolis is a long half mile inland from the blue, blue Mediterranean Sea and if you were a delegate, exhibitor, or hanger-on at DATE, you were stuck indoors the bulk of the week concentrating on electronic design automation, test, manufacturing, and other adjacencies. That’s not to say that these topics are not compelling – even heart-stopping at times – but they just don’t compare to a long afternoon spent in a sunny seaside café lingering over a glass of red, watching the occasional yacht putter past or sailboat glide off into the distance.


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DATE got underway on Monday with a set of tutorials including the requisite hours dedicated to DFM and ESL -- this year featuring Blaze DFM’s Andrew Kahng et al and Bluespec’s Arvind and friends, respectively. Although I was committed in principle to attending some part of those workshops, I lingered instead in that sunny seaside café most of the day. And glad I was that I did, because it was my last view of the sea
in Nice. For the next three days, I was locked up with the rest of EDA in the efficient, modern construct of the Acropolis, and on the next I was among many who left Nice for good.


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Tuesday morning at DATE was opening day, and the plenary session was well attended. Not everyone was in their seats promptly at 8:50, but by the session’s end, the theater was full.


Rudy Lauwereins, 2007 DATE General Chair, welcomed one and all. He said the conference had merged the designers’ forum into the regular conference program, plus was set to showcase the best industrial designs from many companies.


He also said the program reflected the moving focus of DATE from traditional ASICs to system design and test, and embedded software, design and test. He announced that DATE was showcasing 100+ vendors on the exhibit hall floor, including more startups than ever before. He also announced that 5000 people would be at the conference over the course of the week.


DATE Technical Chair Jan Madsen said 92 paper would be presented, selected from the 845 submissions received from around the globe – 350 from Europe, 280 from the U.S., and the highest number ever received from China, Taiwan, and India. He also noted the most popular topics in 2007 appeared to be multi-core processors and network-on-chip.


Next, a host of awards were distributed. Aart de Geus presented the Phil Kaufman Award to Bob Dutton. Bernard Courtois presented the EDAA Lifetime Achievement Award to Tom Williams and DATE Fellow Awards to all previous DATE chairs. Yervant Zorian presented various IEEE awards and congratulated the latest IEEE Fellows in Design and Test. The next 60 minutes were consumed by the two keynotes, one from Toshiba R&D General Manager, Tohru Furuyama, and one from CoWare CEO Alan Naumann.


Furuyama reviewed the range of consumer products now blanketing the globe. He said maintaining the pace of innovation in electronics requires hardware/software codesign and multiprocessor architecture, including Toshiba’s flagship MeP processor core. He also invoked the IBM Cell processor, the ARM core, and the Venezia subsystem from Toshiba which includes the MeP core.


Furuyama went on to talk about the pros and cons of heterogeneous multi-core architecture versus homogeneous. Furuyama said heterogeneous architectures lend themselves to IP reuse, power efficiency, and minimizing chip costs for volume sales. Alternatively, homogenous architectures offer scalable platforms, flexibility, software tuning for bug fixes, and improved time to market. The cons? When heterogeneous architectures need bug fixes, post silicon, they require respins, while further progress in homogeneous architectures will require the development of more effective compilers.


Among many other bullets on his topic list, Furuyama also endorsed ESL, said RTL simulation is accurate, but slow, and celebrated that we’re almost at the point where behavioral synthesis is generating RTL code. Then he touched on various DFM issues – complex design rules, hot spots, and architectures from IMEC and STARC.


If you think this sounds like a lot before the first espresso of the day, you’re right. Dr. Furuyama was fascinating, but for travelers from distant shores such complex topics early in the morning were challenging.


Alan Naumann then took the stage, fully mic’d, and delivered his comments in the style of all great software commanders, striding around out in front of the proscenium arch. From there, he invoked Darwin, dinosaurs, and tar pits. He threw in references to Nice, Rome, evolution, iPods, digital cameras, market dynamics, change, digital consumers, algorithms, quad cores, Intel, TI, Motorola, Cannon, Sony, OKI, ST, Tensislica, ARM, EETimes, and finally Toshiba itself. Naumann made it clear he likes platform design and thought he might be quoting Chris Rowen when he opined: “The processor is the NAND gate of the 21st century.”


Finally, in light of a precipitous drop-off in ASIC design starts, Naumann again advised his audience to evolve quickly or fall into the tar pits – a nasty fate that befell the dinosaurs, he said.


Perhaps I was hallucinating and in need of my mid-morning caffeine, but the more Alan Naumann talked about RTL-design dinosaurs falling into the tar pits, the more I wanted to raise my hand and point out that the dinosaurs are the tar pits. The tar pits are the gooey remains of a moment in the biosphere that disappeared once and for all 65 million years ago. What fell later into the tar pits were the great mammals that wandered the globe, or at least Wilshire Boulevard, a mere ten-to-twenty thousand years ago – not the dinosaurs. Oh well, what’s a few million years between friends? Especially on a Tuesday morning in the
South of France.


I am hoping, however, that the next time Mr. Naumann gives a keynote about RTL designers, dinosaurs, and extinction, that I’m not sitting in a theater just one chair away from the CEO of Synopsys, whose company’s flagship product is based on an RTL view of the world. That was not my idea of fun, even in the South of France.


There was fun to be had based on the CoWare keynote, however, later in the week. I mentioned the dinosaur/tar pit conundrum in a meeting with some European technologists and to my amazement, although they were totally clear on the concept of a dinosaur, they had no idea what a “tar pit” was – or is. Guess tar pits are kind of a California thing, and one of those ideas that definitely gets lost in translation.


What didn’t get lost in translation, however, was Alan Naumann’s call for future design methods to include ESL tools for architectural exploration of multiple alternatives, software/hardware codesign, and application-specific processors that can be used in combination with multiprocessor SOCs. He admonished his audience to acknowledge that we need concurrent development of algorithms, architectures, and processors – and the engineers who can deal with the life forms that reside at these higher levels of abstraction.


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With the plenary session complete, I hit the show floor in time to see Mentor Graphic’s Wally Rhines unveil the newest product in the company’s product portfolio, the Veloce product family – Solo, Trio, and Quattro – based on Mentor‘s emulation-on-chip architecture. (By the way, the folks at Mentor want you to know that it’s not Veloce as in Verbose, but Veloce as in Velo-che with the accent on the ‘o‘.
They also want you to know that Veloce is Italian for fast.)


The unveiling of the Veloce emulation box took place in the Mentor booth on the DATE show floor in front of anybody who wanted to come. The folks at the company had rigged up a shower curtain that could be pushed aside at the given moment. Dr. Rhines gave some enthusiastic opening remarks, the spot lights went a’ spinning, the crowd swelled forward, and the curtain was pushed aside. But there was a problem – the box was on the floor and could not be seen by most in the crowd.


Did it matter? Are you kidding? Mentor had put out a spread in their booth that included a river of champagne and an array of hors d’ourves more dizzying than the strobe lights. The crowd was delighted. They surged past the CEO, and his box, and set upon the free food and beverages like there was no tomorrow. Maybe it was the enthusiasm of the moment, maybe like me, they had missed breakfast in order to make it to the plenary session, or maybe they were gourmands fascinated by
the cuisine of Provence. But whatever it was, the event was a hit.


Meanwhile, in the interests of full disclosure, this wasn’t the first time we in the Press had been fed and watered by Mentor in honor of the Veloce unveiling. The previous evening, we had all been invited over to the most iconic construct in Nice – the Negresco Hotel – for a set of testimonials from happy, pre-release Veloce customers (including NTT Electronics and TI) followed by a regal event in the Versailles Salon, also full of champagne and heavy hors d’ourves.


Secrets be told, Mentor had promised the Press a multi-course dinner that night, but by the time we arrived, the event had been downgraded to an upscale cocktail party. I wasn’t complaining as I had already committed to a different dinner that evening, but Dr. Rhines seemed disappointed. I think he had worked out a lively after-dinner speech further detailing the Cal-Stanford rivalry, but knew that without an audience the punch lines wouldn’t have legs.


But also, if it had been dinner instead of cocktails, there might not have been time for a great conversation between various members of the Press on the topic of Freedom of Speech. With the firing of Imus the previous week, the issue of ugly name calling was on the minds of many and we discussed it thoroughly over multiple glasses of champagne. After looking at the argument from both sides, I was convinced to wear the moniker of Prudish Church Lady with pride. Standing in the Negresco, surrounded by the elegant art brass and art nouveau glass of a bygone era, the moniker seemed poignantly replete with French irony as we gazed out to the misty Mediterranean beyond. The power of
champagne proven once again.


As far as dinner is concerned, however, I will share another secret with you. The Press will never starve, because we are never short on invitations and we see it as our commitment and contribution to the industry to never, ever decline. A free meal is a free meal, no matter the cuisine or the venue, and we do our best to make the companies that feed us feel they are an important part of our lives. It’s tough work, but somebody’s got to do it.


And, on occasion, even a kind-hearted CEO pitches in. Case in point: This past week at DATE, Dr. Rhines himself wanted be sure that the folks catering the meals at the Synopsys booth felt appreciated. So he made a courtesy call to the booth, enjoyed a roast beef sandwich, and declared the Synopsys efforts a success – a predictable success.


********************************


So, Tuesday at DATE continued unabated. I saw Gary Smith’s panel on reconfigurable devices. He started by asking the audience to participate in a DATE specialty – electronic voting via handheld devices. Gary asked for answers to a host of questions and determined that two-thirds of those in attendance were using reconfigurable devices and, among those, 47 percent were working with reconfigurable silicon, 22 percent with reconfigurable software, and 37 percent with systems that were reconfigurable on the fly. He also learned how his audience ranked concerns related to reconfigurable systems. Cost was at the top, followed by performance, and then reliability.


Cadence’s Eric Filseth, a panelist, said the huge investments now required for hardware design is serving as motivation to increase software on-chip, and hence reconfigurability. Panelist Ralph von Vignau from NXP made an argument for field programmable logic in this era where the shelf life for an SoC is growing shorter and shorter. He noted, however, that reconfigurable devices still need to be validated because “there is no such thing
as bug free hardware or software.” Toshiba’s Tohru Furuyama endorsed dynamic reconfigurability, and STMicro’s Vittoria Peduto said the cost of building fabs, combined with increasing mask costs, makes the move to reconfigurable devices inevitable. These are, of course, only the highlights of what turned out to be a surprisingly substantive conversation on a well-known topic. Credit Gary Smith for the success of the hour.


And speaking of Gary – once again at DATE, he was everywhere! He moderated or appeared on four different panels on Tuesday and Wednesday speaking on topics that ranged from ESL to DFM, from compilers to reconfigurable devices. He was a “Special Guest” in the Mentor Graphics booth on Wednesday from 4 pm to 6 pm, entertaining the cocktail crowd with Q&A regarding ESL. He was at the dinners, he was in the Press Room, he was meeting with folks everywhere, and his name was repeatedly invoked by the companies I met with to further justify and validate their technology and/or business models. The man is a total machine, and where he gets his energy is a secret I have yet to
uncover – yet!


Meanwhile, there were numerous other interesting panels and sessions on Tuesday, although it was impossible to attend them all. In the session on terascale integration, concerns were expressed about current abilities to parallelize programs and take advantage of multi-core devices through multi-threading. The obstacles here are huge – code that qualifies for multi-core devices needs to go lite on loop dependencies – and there is not yet a full complement of automatic tools available to condition code for the newly emerging multi-core devices.


The Executive Track panel on the viability of fabless companies in Europe touched on competing themes. Globalization of the semiconductor design and manufacturing chain provides little motivation for developing new regional specialties. Alternatively, the drive to further capitalize on the deep intellectual capital available in the European marketplace, and the desire to create additional job and investment opportunities in the region, is indeed motivation for additional fabless enterprises in Europe.


A complex conversation ensued – with 3i’s Robert Jelski, CSR’s Jon Hudson, Dibcom’s Khaled Maalej, Synopsys’ Antun Domic, and TSMC’s Gareth Jones – which included mention of Taiwan, IMEC, 24x7 communication across the globe, MEMS, startups, the commercializing of university-driven innovation, fab costs, market dynamics, politics, and the advantages of having everybody working under one roof. The discussion wove in and around the complex question at the core of the panel discussion, additional business opportunities in Europe. In the end, I was not sure if there
should or should not be more fabless players in Europe – the question of regional specialization was not resolved – but the highly charged issues that drive the question were certainly showcased.


Also on Tuesday, I peered into an absolutely packed meeting room with Grenoble’s Design & Reuse Gabrielle Saucier moderating a panel on SystemC at the OSCI lunch. The room was so crowded and hot! But clearly, people were so interested in the topic they had no desire to flee the conditions.


At that same lunch hour, I unfortunately mis-read my schedule and missed the Accellera lunch over at the Novotel where additional discussion of the new Unified Power Format (UPF) was taking place. However, ever since I saw the happy campers from Mentor, Magma, and Synopsys cohabitating the UPF booth at ISQED last month, I have been confident that the companies involved are moving forward together in lockstep. I’m also confident that reps from all three of these EDA leaders were at the Accellera UPF lunch in Nice. What I don’t know is what I missed for lunch. Which is tragic, because I never got any lunch at all on Tuesday. So, by the time I showed up for the marvelous EDAC
Executive Reception on the top of the Acropolis at 6 PM that evening, I was definitely ready for food and libation.


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EDAC did not let me down. How the EDAC crew sets up a party like this when they’re based in Silicon Valley still escapes me, but Bob Gardner, Jennifer Meola, and Karla Haley continue to make it look easy. The food was lovely and the wine was delish as we stood atop the conference center enjoying a view of the distant hills and the glow of Nice as the sun set to the west.


It was great to have a chance to talk there with EDAA award winner Tom Williams and his lovely wife, great to see Magma’s Rajeev Madhavan there, and also great to chat with Jasper’s Kathryn Kranen about her impressions of the show.


Lest this brief narrative descend into a society column, however, I will add that EDAC Chair Aart de Geus gave a marvelously gracious welcome to everyone in attendance, and reminded his community that the Richard Newton Chair at U.C. Berkeley is up and running courtesy of his many friends and admirers in the EDA Community. After Aart finished his comments, a particularly patrician European turned to me and said, “Now that is a class act! Aart de Geus puts such a distinguished face on the EDA industry!”


I will second that motion regarding Dr. de Geus and invite you to tune in next time, here in EDA Weekly, for further discussion of DATE – in particular the Special Day on Aeronautics and Space that took pace on Thursday. Meanwhile, I hope that you’ll take some time to glance through the EDA news items below. They represent a cross section of some of the news that has come my way before and during the conference, and also represent the wide diversity of companies and people who made DATE so interesting.


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And with that, I will end on a particular emotional note. On Wednesday morning at DATE, I was in a session about security and ubiquitous computing. The talk was being presented by Ingrid Verbauwhede of the Katholieke University in Leuven. Her co-presenter was Patrick Schaumont from Virginia Tech.


As Dr. Verbauwhede took the stage, she asked the entire audience to stand in silence to acknowledge the deaths at Virginia Tech out of respect for her colleague, Dr. Schaumont. As difficult Internet access, both at my hotel and in the Acropolis Center, had prevented my seeing any news for over 24 hours at that point, I did not have a clue what Dr. Verbauwhede was referring to. I only knew that the audience stood immediately and within the profound silence in the room, I heard the European heart beating in one with the American heart.


After the session was over, I rushed to find out what Dr. Verbauwhede had referred to and quickly learned what everyone else seemed to know. As the mother of three wonderful young people, all of whom live, work, and study in university communities in the United States, the news out of Virginia Tech was horrifying beyond words. The news out of Virginia Tech was every parent’s worst nightmare come true.


Now I sit in a café in Rome, completing this part of my DATE report and sharing a glass of wine with Van Morrison who is singing on a radio nearby. Suddenly it seems right to take a moment to send this message to my children, and to the children of every parent in the world:


Have I told you lately that I love you

Have I told you that there’s no one above you

You fill my heart with gladness

You take away my sadness

You ease my troubles

That’s what you do.



Van Morison


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News from the DATE and the World of EDA


Five EDA companies -- AWR, Ciranova, Silicon Canvas, Silicon Navigator, and Synopsys -- announced an agreement to collaborate on the creation and distribution of an interoperable PCell library (IPL). The IPL supports the OpenAccess database from Si2 and is available as open-source software that any interested party can use. Hence, the 5 organizations involved say an invitation is open to all other interested parties to join in the fun. The Press Release includes the Wow Factor: “For the first time in semiconductor industry history, an integrated circuit designer will be able to use the same PCell libraries in tools from all five vendors, plus with
OpenAccess-based tools from other vendors or universities, or developed in-house.“ Meanwhile, Mentor Graphics says it’s supporting the effort to ensure that library components are “truly interoperable across toolsets and foundries.”


ACE (Associated Compiler Experts) announced the OpenCoSy compiler community initiative, which the company says will move to “enable and encourage users of ACE’s CoSy to share advanced compiler technology components and to co-develop leading-edge compilers … OpenCoSy affords academic institutions the ability to share and publish results, as well as commercial organizations the freedom to invest, share, protect and sell compiler IP as they see fit.”


Apache Design Solutions announced its RedHawk-ALP physical power integrity tool for advanced low power and leakage control designs. The company says the new products “targets power savings and leakage control techniques used in 65 and 45-namometer designs including VTCMOS (Variable Threshold CMOS) circuits with substrate back-biasing, MTCMOS power-gated memories and custom macros, an on-chip LDO (Low Drop-Out) voltage regulator.”


Applied Wave Research (AWR) announced a 20-percent increase in sales for fiscal year 2007. AWR also announced that Dane Collins, former executive vice president, has taken over as CEO. The company says changes in the executive team are being made as part of an overall strategic plan that maps to the long-term goals of the company.


ArchPro Design Automation announced the expansion of its European distribution network, managed by In Region’s Modesto Casas, with the addition of distributors FirstEDA in the U.K., AmbLot in France, and Germany’s eVision Systems.


ARM announced the launch of RealView Development Suite version 3.1. Per the company, the new release includes “performance improvements and tuning for ARM processor support, better optimization for the full Cortex processor family, including the Cortex-M1 processor … the first ARM product designed specifically for FPGA implementation.”


Atrenta announced that it has appointed Dieter Rudolf and Martin McIntyre to help expand the company's Central and Northern European business operations. Atrenta already has offices in France and 30+ European customers. Rudolf and McIntyre will focus on expanding Atrenta's business opportunism with additional offices in Germany and the U.K.


Blaze DFM closed a Series B round of funding for $10 million. The company also announced it has completed the merger with Aprio Technologies. The combined company will continue on as Blaze DFM. New Blaze investors in this round include El Dorado Ventures and Mobius Venture Capital, who were investors earlier in Aprio. Lightspeed Venture Partners, who led Blaze’s Series A funding, also participated in this latest round.


Bluespec announced that The Association for Computing Machinery (ACM) has named Arvind, founder of Bluespec, a 2006 ACM Fellow. Arvind is the Johnson professor of Computer Science and Engineering at MIT and receiving this award for his contributions to dataflow computing and verification. He was on hand at DATE presenting a tutorial on Monday about ESL design.


Cadence Design Systems announced that UMC has joined the Power Forward Initiative (PFI), “formed to advance the adoption of the Common Power Format (CPF) which captures essential design intent for power and links the design, implementation and verification domains.”


Calypto Design Systems announced that its PowerPro CG product, that the company designed to reduce power at the RTL level, will support Si2’s Common Power Format 1.0 (CPF) . Calypto also says it has joined the Si2’s Low-Power Coalition (LPC) “to further work with customers and EDA vendors on improving interoperability between power optimization, design and verification tools.”


Carbon Design Systems announced that its models are plug-and-play with CoWare’s Platform Architect design environment. Per the company, “these models support a programmer friendly view of the hardware for system validation and have transaction-level interfaces for high-speed execution.”


CebaTech announced the CebaIP Platform, which the company says is a protocol-complete hardware and software framework for developing end-to-end data and storage networking solutions. Platform configurations initially supported include GZIP-based compression and decompression with optional AES support, and a second configuration that includes partial TCP/IP offload with optional link aggregation, VLAN, and large send offload (LSO) support.


Chartered Semiconductor Manufacturing announced realignment of various senior management roles. Kay Chai Ang becomes senior vice president of worldwide sales and marketing. Simon Yang becomes senior vice president of fab operations, in addition to his existing role as CTO. Mike Rekuc becomes president of the Americas region. And, Dominique Simon becomes vice president of business development and global accounts.


Ciranova and Si2 are announced an escrow agreement whereby Si2 becomes the beneficiary of Ciranova’s PyCell Studio just in case Ciranova product is no longer available for free to customers. Ciranova says it is committed to making the use of its PyCell technology free and open, and that now Si2 as an even more important standards keeper.


CoFluent Design announced it has opened operations in the U.S. and established CoFluent Design, Inc. as a fully-owned subsidiary of CoFluent Design. The company also named Hagay Zamir as Business Development Director for the U.S., based in San Jose. Prior to CoFluent, he was at Summit Design and CARDtools Systems. The company also announced CoFluent Studio was selected to be part of the CIM PACA (Center for Integration of Microelectronics in Provence) collaborative research platform.


Computer Simulation Technology (CST) announced its CST Microwave Studio 2006B is offering increased performance for signal integrity analysis. Per the Press Release: “Engineers studying signal integrity, power integrity, or general EMC/EMI effects can now investigate their structures using CTS’s full-wave 3D EM simulator … without having to introduce approximations.”


Concept Engineering announced a new detailed standard parasitic format (DSPF) interface to the company’s SpiceVision PRO and SGvision PRO products that the company says will “enable design engineers to better understand, manage, and fix parasitic structures within complex digital, mixed-signal, and analog ICs. The layout of an IC contains an enormous number of parasitic devices resulting from the interconnections and components of the chip. Such parasitic networks, often modeled as DSPF files, describe the parasitic resistance and capacitance of signal nets within an IC.”


Coupling Wave Solutions (CWS) introduced WaveIntegrity, a software platform for modeling signal integrity and noise propagated though IC substrate, interconnect, and package. Propagated noise can be monitored at any point in the system, from power supply nodes to a specific location at the surface of the silicon substrate. The tool has been developed in partnership with NXP and STMicroelectronics.


The Design Automation Conference (DAC) announced that Jan Willis, Senior Vice President for Industry Alliances at Cadence Design Systems, is the 2007 recipient of the Marie R. Pistilli Women in Electronic Design Automation Achievement Award. Per the Press Release: “Jan Willis is being recognized for her commitment and dedication to fostering the careers of women in EDA.”


EDAC’s Maret Statistics Service announced that EDA industry revenue for Q4 2006 was $1.493 million, which is 19 percent more than Q4 2005. MSS also announced that 2006 full-year revenue for EDA was $5.274 million, a 15-percent increase over 2005. In addition, MSS says that 25,390 people were employed in the EDA industry in Q4 2006, which was up 10 percent over Q4 2005.


EMA Design Automation announced that it has contracted with ALS Design in France as the first international VAR to sell EMA’s TimingDesigner. The companies say, “ALS Design is the market leader in France for EDA solutions and the provider of high-performance training services.”


Esterel announced that the IEEE has begun work on the IEEE P1778 Standard for Esterel v7 Language Reference Manual, which the company says will stabilize and fully define the syntax and semantics of the language. Per the Press Release: “Esterel v7 expresses he interaction of hardware, software, and temporal synchronization, and helps increase design efficiency and reliability for semiconductor and other embedded systems. It is scheduled for completing in mid-2008.”


EVE announced the formation of EVE Design Automation Pvt. Ltd., a wholly owned subsidiary based in Bangalore, India, known as EVE DA. The new subsidiary is headed by Montu Makadia and will market and support the company’s ZeBu platforms of accelerators, emulators, and FPGA prototypes.


GateRocket announced availability of its RocketDrive Device Native verification product that the company says gives FPGA designers “the power to validate designs with one to two orders of magnitude faster simulation, and realize actual device behavior early in the design process. RocketDrive is a hardware and software solution that adds significant value to existing design verification environments without a change in design flow or verification methodology. Traditional emulation environments strive to be technology independent, but suffer from long and arduous startup efforts for each project and produce inaccurate results. GateRocket’s new approach
leverages the strength and uniqueness of the FPGA device and the flexibility of popular simulators to deliver a unique and accurate verification solution for these advanced design projects.” The company says its new product complements design tools from all leading EDA vendors including Cadence, Mentor Graphics, Synopsys, and FPGA tools from Altera and Xilinx.


IMEC announced it has developed a “generic and versatile method” to synthesize stable, biocompatible magnetic nanoparticles. IMEC says by tuning the endgroups, the functionalized nanoparticles can be used for a wide variety of biomedical applications, including accurate drug delivery, improved diagnostics, and targeted cancer therapy.


Impinj announced availability of the company’s AEON/OTP nonvolatile memory (NVM) cores in the 90-nanometer manufacturing process at TSMC, which the company says makes Impinj “the first and only provider of one-time- and multiple-time-programmable (OTP and MTP) NVM cores in advanced logic CMOS processes.”


INC3, the third International Nanotechnology Conference, took place this week in Brussels with approximately 250 technologists and policy makers from around the world. They discussed developments in nanotechnology, the challenges and bottlenecks, the economic and societal implications and the need for collaboration across industry, academia, governments, and financial institutions. Per organizers, “The presentations emphasized that the multi-disciplinary skills and tasks needed for further nanotechnology innovations exceed the resources and capabilities of any single company, nation or region.”


Invarium announced “a leading U.S.-based semiconductor equipment manufacturer” has selected the company’s full-chip DimensionPPC technology for mask design and patterning process optimization. Per the press release, “the equipment manufacturer, rated one of the top 10 tool suppliers by VLSI Research, will use DimensionPPC to enable rapid back-end-of-the-line (BEOL) integration on its test ICs at the 45 and 32-nanometer nodes.


KLA-Tencor and Clear Shape Technologies announced they are collaborating on DFM solutions, “enabling design-aware photomask inspection at 45nm and below.” The collaboration involves KLA-Tencor's Terascan HR photomask inspection system and Clear Shape's Variability Platform products. Not surprisingly, “the two companies expect this collaboration to enable customers to achieve improved device yield and, ultimately, faster production ramp for the most advanced designs.”


Lynguent and Dolphin Integration announced they will integrate their modeling and simulation solutions and provide them to designers of analog/mixed-signal ICs. Lynguent's ModLyng graphical tool will create models tuned for Dolphin’s Integration's single-kernel SMASH product for mixed-signal simulation.


Magma Design Automation and Mentor Graphics announced the implementation and verification of a design in which low-power requirements were specified in the Unified Power Format (UPF). “Based on Magma's Talus IC implementation platform and Mentor Graphics' Questa verification platform, the flow has been shown to reduce turnaround time for advanced low-power nanometer ICs. It is the first complete flow to support the new standard.”


The MathWorks announced the release of Fixed-Point Toolbox 2, which the company says “provides enhanced floating-to-fixed-point conversion capabilities and accelerated fixed-point MATLAB algorithms that execute at compiled C-code speed … Design engineers now have a cohesive workflow for optimizing and verifying embedded algorithms entirely within MATLAB.”


Mentor Graphics announced with great fanfare three new hardware-assisted verification platforms, the Veloce Solo, Trio, and Quattro products based on the company’s new Emulation-on-Chip architecture. The company says the new products are significant announcements in the area of emulation, and offer “megahertz-class verification run-time speeds without compromising debug productivity and modeling accuracy for designs up to 128 million ASIC gates. This new verification family delivers the industry’s fastest target-less and in-circuit emulation (ICE) capability that facilitates concurrent hardware-software validation and embedded system verification for
key vertical market applications such as multimedia/graphics, computing, networking and wireless designs.”


Also per the press release: “The rack-mountable, multi-user Veloce Trio addresses the needs of logic and system designers for up to 16 million ASIC gates in a data center-like environment. The single user Veloce Solo addresses the needs of designers developing systems up to a complexity of 16 million ASIC gates in an acceleration or in-circuit emulation mode. The multi-user Veloce Quattro is architected to address the needs of design teams developing systems up to a complexity of 128 million ASIC gates in an acceleration and/or in-circuit emulation mode.”


MOSIS announced access to IBM’s 65-nanometer silicon foundry process through its multi-project wafer (MPW) service, which the company says allows designers to obtain samples or small production quantities of digital or mixed-signal devices “at less than 10 percent of the cost of using a dedicated production runs by sharing masks and wafers with other chip designs.”


OCP-IP announced a white paper discussing a standardized OCP-bus compliant debug interface -- an optional OCP port implementing a Debug Interface Socket, which can be added to al cores and IP blocks to support uniform on-chip system analysis. The white paper was authored by the OCP-IP working group that includes TI, MIPS, and Pixelworks. OCP-IP also announced a collaboration with Synopsys to provide Synopsys DesignWare Verification IP as part of OCP-IP’s CoreCreator verification toolset, replacing OCP Bus Functional Models (BFM) currently in the toolset.


OSCI, the Open SystemC Initiative (OSCI), has released a report that the organization says confirms “the worldwide adoption of SystemC is strong and continues to grow, and that SystemC user groups in all geographies are quickly adding members and taking an active role in promoting standardization efforts.” The report analyzes user survey data from recent SystemC industry events and is available for download at the OSCI website.


Pyxis Technology announced Joe Hutt is now president and CEO. Hutt is an investor in the company, previously on the company’s board of directors, and most recently vice president of engineering. Before Pyxis, he was an exec at Magma, and served at Synopsys and IBM. The company also announced Mitch Heins moves from vice president of business development to vice president of engineering. Previously, Heins was at HPL Technologies, Petersen Advanced Lithography, Cadence, Ambit, the precursor organization to Si2, and TI. Meanwhile, Naeem Zafar, previous Pyxis president and CEO, has joined Altair Ventures.


Real Intent announced its Meridian clock domain crossing (CDC) verification software. The company says the tool verifies that data traversing asynchronous clock domains is received reliably, verifies the structure and the protocols required for CDC safe design, and pinpoints design problems with a minimum amount of sign-off.


Sandwork says its SpiceCheck tool, part of the company’s analysis verification and debugging (AVAD) suite for analog and mixed-signal design, performs transistor-level design rule screening from static connectivity to post-layout signal integrity evaluation. The company also says, “SpiceCheck is the only fully Tcl programmable netlist-driven static rule checker that is also capable of dynamic waveform probing.”


Sequence Design Automation and NEC System Technologies announced that NEC has joined the In-Sequence Technology Partner Program. The companies say they have interfaced NEC-ST’s CyberWorkBench ESL synthesis with Sequence’s Power Theater “to offer users ESL productivity combined with an ability to analyze various architectures for performance, area, and power.”


Silicon Canvas announced the rollout of what the company calls the first automated DFM features designed for designers in its Laker product. The DFM features need no scripting and support various design requirements including multiple rule sets, conditional rules, recommended rules, discrete gate spacing, minimum area rules, and routing jog avoidance. Per the press release: “Additional DFM rules are being developed on an on-going basis and will be rolled out as they become available.”


Silicon Navigator announced it has appointed Kevin Moynihan as COO, reporting to company CEO George Janac. Previously, Moynihan was a business unit vice president at KLA-Tencor.


Synopsys announced that Splashpower, a U.K. company in wireless systems design, has chosen Synopsys’ Saber simulator. Per the press release, “Splashpower engineers chose the Saber simulator solution because of its ability to easily model and simulate the complex electro-magnetic environment of their advanced wireless power transmission system.”


Synopsys also announced the latest release of Design Compiler, Design Compiler 2007. The company says the new release “extends topographical technology to accelerate design closure for designs utilizing advanced low-power and test techniques, boosting designers productivity and IC performance … Topographical technology supports new test compression technology in Design Compiler 2007 to achieve high test quality while reducing test time and test data volume by more than 100 times.”


Synopsys also announced IC Compiler 2007.03, which the company says includes “significant advances in IC designer productivity through faster runtime, higher capacity, smarter multi-corner/multi-mode (MCMM) optimizations, and improved predictability … [It also includes] physical design support for 45-nanometer technology.”


Temento Systems announced innovations in its DiaLite Platform Edition with what the company says is “a more powerful range of instrumentation IP, including PSL or SVA assertions for checking IP communication protocols on-chip, and TemStorage external storage memory which records off-chip signal traces up to 120 channels.”


Tensilica announced it now supports Avnet LX60 FPGA boards for high-speed hardware-based simulations of its Diamond Standard processor family. The company says software developers can use these boards, which allow Diamond Standard processor cores to run on Xilinx Virtex-4 FPGAs, “to speed their software design, debug and program optimization processes.”


Test Systems Strategies (TSSI) announced two new products, TD-Scan and TD-Sim. TD-Scan Supports ATPG outputs with compression technologies from Cadence, Mentor Graphics, and Synopsys, and is designed to translate scan patterns (ATPG) in WGL or STIL format to a target ATE program format. TD-Sim is designed to translate scan patterns and functional patterns from logic simulators in the format of VCD or EVCD event files.


VaST Systems announced that ESLX has joined VaST’s Galaxy network of SystemC service providers, which provides SystemC training and services to help customers with their engineering competency in SystemC-based system-level design. ESLX is a consulting services company specializing in system-level hardware and software design methodologies.


VSIA announced the Hong Kong University of Science and Technology (HKUST) donated its Deliverables Checklist to VSIA. Per the Press Release, “Together the VSIA and HKUST will further develop the methodology and tools within the VSIA QIP Metric with the addition of the Deliverables Checklist. The two groups will also discuss ongoing work on QIP and other VSIA standards and are collaborating on a memorandum of understanding to extend this work to three universities in Mainland China.”


X-FAB Semiconductor Foundries AG and ZMD AG have agreed that X-FAB will take over ZFOUNDRY (ZMD Analog Mixed Signal Services GmbH & Co. KG), the wafer production facilities of ZMD, located in Dresden, effective immediately. ZFOUNDRY will be integrated into the X-FAB Group as a subsidiary of the X-FAB Semiconductor Foundries AG. In addition, the companies agreed to maintain close collaboration long-term regarding wafer manufacture. A wafer delivery contract ensures that X-FAB will become the principal supplier of foundry services for ZMD which, in turn, becomes one of the Top 10 customers of the X-FAB Group.


Xoomsys has named Raul Camposano to be CEO. Previously, he served with distinction as CTO of Synopsys. Camposano has published 70+ articles and three books on EDA, and was elected an IEEE Fellow in 1999. He has an MS from the University of Chile, and a PhD in computer science from the University of Karlsruhe. I spoke with Raul by phone prior to my trip to DATE, and it’s clear he is delighted with his new role at Xoomsys. I’m predicting his arrival will mean great things for the company.


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Peggy Aycinena is Editor of EDA Confidential and Contributing Editor to EDA Weekly.


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-- Peggy Aycinena, EDACafe.com Contributing Editor.


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