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February 19, 2007
Fast-SPICE with Nascentric
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor


by Jack Horgan - Contributing Editor
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Introduction

On December 28 EVE announced that it had acquired Tharas Systems. On January 11 Nascentric announced the appointment of Rahm Shastry (former Tharas CEO) as its new president and CEO. This was less than 2 weeks including XMAS and New Years. Tharas is a hardware accelerator company while Nascentric is a software company with offerings in the Fast-SPICE simulation market. I had an opportunity to talk to Rahm along with Dennis George, Nascentric Director of Marketing.


My thesis advisor was Kandula Sitaram Sastry. I couldn’t remember whether there was an ‘h’ or not in his last name. I had to look it up.

Shastry is spelled both ways. But it is always pronounced with an ‘h’ in it. In different parts of India they spell it differently. But where I come from, it is pretty much Shastry. There is also a variant Sastri. If you want to be politically correct, I don’t think it matters.


Would you give us a brief biography?

I joined Nascentric in December. Prior to that I was at Tharas for 5 1/2 years. Tharas Systems was a Santa Clara based company doing hardware acceleration for Verilog designs. Our unique value proposition was a processor based system, a massively parallel system. That was something we sold to a lot of the big companies who did not want to spend all their money on emulation. I was there 5 ½ years. We sold the company last December to EVE (Emulation Verification Engineering). EVE has an emulation product and Tharas has an acceleration product. It is a great marriage for the two companies. The EVE and Tharas combination can now effectively compete with Cadence who has everything. Prior to Tharas I had gone on my own outside of EDA for about a year. I dabbled in mobile internet and e-commerce type of businesses. But I had been in EDA for a long time since 1988. I veered back into EDA in 2001. Prior to that I was at Cadence for 3 years. At the time I left Cadence I was managing the hardware functional verification product line: NC Verilog, equivalence checker, formal checker and so on. Before Cadence I started a company in 1995 called Triquest Design Automation. I was CEO of the company. Our goal was to develop synthesis tools to go against Synopsys who was good at it. It was a brutal one. It was pretty hard. We had domain based synthesis. We were focused
on control logic, data path and behavioral synthesis. In 1997 we decided it was very hard to against Cadence so we got acquired by a company called Summit Design who has since become part of Mentor Graphics.


Prior to that I was Viewlogic for 7 years. I was the technical marketing manager. I also managed the Asia Pacific and Japan operations in the early 90s. It was more of a marketing oriented role starting at the application level.


Prior to my EDA career I earned a masters degree in computer engineering from Stony Brook. From ’82 to ’88 I worked in chip design (MOS, CMOS and NMOS) and then at Apollo Computer on system level design for network chips. That’s my background.


Quite impressive. So EVE and Tharas were in the same overall market but still complementary.

Correct. We did not compete. We were adjacent. In the design flow when the RTL code is not stable but large enough where you can not really use software simulation, you use an accelerator. With an accelerator you can compile and get the design running. You can only do this with an accelerator. When the RTL is not stable, changing on a daily basis, you use an accelerator. But accelerator performance is limited by Amdahl’s law. If your testbench is 5% of the total time, the maximum performance you can typically get is 20x because you can not accelerate the test bench. The testbench could be all C, C++, e, Vera or whatever. As the RTL stabilizes, there is a different mode of
operation which historically is emulation. At that time you are not testbench bound, so you can run 100x faster than an accelerator. That’s where EVE excelled. That’s the reason why they are extremely complementary products and we rarely competed with each other. EVE’s product is FPGA based. FPGAs have their own peculiarities. Compile time is horrendous while performance is awesome. The Tharas accelerator is processor based and like a software simulator it has very fast compile times but the performance is limited by Amdahl’s law.


Tharas was about 20 people at the time of the acquisition by EVE?

Yes. There was also a team in India. They were not Tharas employees but worked full time for Tharas as contractors. There were 9 to 10 people there.


How big was EVE?

EVE was about 60 to 65 people worldwide before the acquisition. They are probably about 80 people now.


How did the two companies get together? Who approached whom?

I know Lauro (Rizzatti GM of EVE-USA) and Luc (EVE CEO and President). This is how it works, especially in the Silicon Valley. Luke, the CEO of EVE, had approached me about a year or a year and a half ago because they wanted to have our compiler. The compiler that Tharas had was extremely fast. But that deal didn’t go anywhere for a multitude of reasons. We didn’t know how to license it to them. This year after DAC I approached them. Of course the VCs are always involved. The last thing that happened was I approached EVE and said “Let’s sit together. A year ago we did not do a deal but let’s talk about what we can do, figure out how to
effectively compete against our common enemy, Cadence, in this market.” That resulted in the acquisition.


When large companies acquire smaller companies, the CEO of the acquired company often ends up heading a division. Perhaps, when the acquiring company is small, there is no room for another executive.

Luc actually wanted me to stay at EVE. He offered me to become the general manager of the accelerator division. I looked at myself and my career. That was not what I wanted to do. EVE required a GM who was more operational. I am okay at operations but what I am most interested in is the strategic vision and how to realize the vision and parlay that into a successful company for the founders and employees. That’s what I feel good about. That’s when the Nascentric opportunity came about. I thought it was a very interesting opportunity and that’s how I started talking to the principals at Nascentric.


For the last 5+ years you have been with a company whose principal product (Hammer) was hardware and now you have joined a software company. Is there any significance to that shift?

If I look at my career, my first company was a hardware based company. Cadence, ViewLogic and Triquest were all software companies. After I left my chip and system design jobs, I went to EDA. That made sense to me because I knew the chip design process and the system design process so that I could add value into the EDA market. I have always been interested in software companies except at Tharas. At Tharas we did functional acceleration and Verilog. Gate level was the lowest level you could go. We were focussed on RTL and behavioral whereas at Nascentric the challenge is more at the SPICE level. That’s exciting to me. It’s a slightly different value proposition but
nevertheless extremely important. Since I had done chip design before, I know what it takes to characterize the various components on a chip accurately. Once it is characterized then of course it will go to hardware accelerator. I see this more of a challenge.


Like I said to Dennis “I need to understand what we are doing and the players in the market in order to run the business.” The strategy and the operation are just the same. It is just that you have to put your ear to the ground and figure out what you can do, prioritize things. There are the same challenges. We are competing here in the Nascentric world against the same big companies. They all have a presence and product lines with certain capabilities. What we are trying to figure out is how can we be better than them. Build better, faster, more capacity and address the sub 65 nm issues. Then they come with a whole set of priorities. That’s all we have today.
That’s pretty exciting to me.


The former Nascentric CEO, Vess Johnson, has moved over to VP of Consulting Services. Was Nascentric looking for a new CEO?

Yes. The Nascentric board went out seeking a new CEO. That’s’ how I started talking to Nascentric. Sometimes it happens. Startups in general are tough and EDA startups are even harder. Vess is a great mentor to the team. He is very valuable to the team. He is adding huge value now in the role he is playing. This is like a symphony orchestra. Everybody has a role to play. The board of governors has appointed me to be the conductor.


Nascentric is in the Fast-SPICE market. How would you define the Fast-SPICE market?

Traditionally SPICE is by default the simulator that people trust. Silicon vendors, chip designer all trust SPICE simulation for the accuracy of its models. The problem is that SPICE was built in 1960. It is very slow. It is great if you have 50 to 100 transistors you want to simulate. But nowadays there could be millions of transistors. If I want to calculate IP, lets say an IP vendor like Qualcomm, nobody is building everything from scratch. They are buying IP blocks. They are acquiring or they have already built it themselves. 80% of the new chip is pretty much the same as the old chip. They do the interfaces. If you look at the IP market, look at SRAM or some custom digital
designs you can not use SPICE. It does not work. What they do is they have what is called a cut netlist.


If you want to simulate the whole SRAM, you can not do it today. It is millions of transistors. So they cut the netlist. They characterize what would be worse case paths. They’ve got some heuristics and other things that people use but it is still an approximation. With Nascentric you do not have to cut the netlist. Just simulate the way you doing because our simulator can run so much faster and has so much more capacity. We can easily simulate SPICE runs out of stream at 20,000 equivalent transistors.


Dennis: Some of what we are hearing from a lot of IP vendors is that even the cut netlist is presenting tremendous problems in the design process itself because at 65 nm there are so many more parasitics that even cut netlist has so many devices in it that it is causing problems as well. They really need a simulator that we traditionally think of as a Fast-SPICE simulator, able to handle all the parasitics, all the devices and able to simulate that accurately enough so that accuracy is not lost due to people having to throw things away in the traditional flow.


You know that the Nascentric product has been delayed. It is amazing technology. I am pretty excited abut it. Some of the good stuff we are working on will actually lend itself to Fast-SPICE simulation, 1000x faster than SPICE and be able to handle the capacity of millions of transistors, capacitors and resistors, all the RC effects and at the same time have accuracy with plus or minus 2 or 3 percent of SPICE. That’s what we are trying to offer in our product line. Frankly there are other products in the market today. We are not the only one. But we have some differentiators that we believe will be extremely interesting too the customer base.


Who are some of these other vendors and what are the differentiators?

Dennis: If you think about the Fast-SPICE market, it is divided up into Synopsys, Cadence and Magma has also entered the market as well. Again the real issue is that what those guys really have is a traditional SPICE simulator. It is an engine that is based upon SPICE itself. SPICE has not changed in 30 years.


What they have done for the most part is that they have figured out better data management strategies or they have figured out ways to throw away more parasitics so that they can get the performance and the capacity they need. What we have done with AuSIM is a different approach. The technology is based upon being able to do a better job of modeling unique devices so we basically have a multi-engine architecture. That means we create special models and engines to operate on transistors differently than on interconnects or operate on the transistors differently than on a slightly larger sub-block or cell type of entity. Because we manipulate things that way we have the ability to optimize the data is represented in the data structures and the way it is manipulated in terms of the calculations for the simulation itself. We get a much more accurate result and we are able to simulate faster. The key differentiator is really being able to run the simulation much faster than the competition as well as having the architecture that allows us to take advantage of new technologies that are on the horizon such as multiprocessor and multicore machines as well as the capacity that is required to handle all the additional parasitics. Not too long ago you may have seen that we were awarded several patents for the way we are modeling those devices. We should be announcing
additional patents shortly.


Nascentric AuSIM’s Multi-engine Architecture


The product was originally called Nascim but was renamed AuSIM. Any significance or just some marketing guy with a cute idea?

Denis: A couple of reasons. One is the feedback from customers was that we needed a more appropriate name. We needed a name change to make sure we were clearly differentiated from the name of other simulators in the market.


Rahm: What Denise is trying to allude to is that Synopsys had a product called Nanosim. NanoSim is close to Nascim. That’s not what we wanted. We wanted something different which is why we changed the name. Au stands for gold. Au also stands for “Awesome” simulator. Further some of the technology comes from Austin, Texas. It is really an awesome simulator, a play on words.


You said that there was a new release or a next generation version of the product that has been delayed. Can you describe the feature set and the performance as well as the timeframe for its availability?

We have several beta sites evaluating the next generation system. We alluded to that in an interview a couple of weeks ago. In the next 6 to 8 weeks we will announce the product. Right now we take in the SPICE netlist and do what we call an intelligent topological assessment. We analyzed that this is a transistor so let’s use the transistor engine on this. Here is an interconnection


In sub 65nm if you want to analyze a post layout netlist, oh my god, it is dominated by RC delays and all the stuff that is going on. What we have is a transistor engine, an interconnect engine, a cell based and block based engines. Once we compress the topology we apply different focused engines. Here is where we differentiate from SPICE. SPICE does not do that. Each of these engines will operate on its own. With all the new technology coming out in the marketplace we will be able to leverage those resources. We want ot be in the Fast-SPICE market. Obviously, we want to be much faster than the competition for us to be considered and we need to be able to handle the capacity and be able
to be plus or minus 2% to 3% of SPICE. We are very close to announcing that.


I am being cagey not to give you the details because we want to talk about it once the product is out of beta. Then we can talk about some of the customer successes.


The company is headquartered in Austin and yet you are located in San Jose.

I am in between. We have an office in San Jose. We are going to add primarily outbound application engineering as well as good engineering talent, if we can find it here. I am going back and forth between the two places. I take the usual Austin flights back and forth. Every other week I will typically be there.


Has there been any additional funding associated with your coming on board?

Yes. We have already added $7 million so far. We are trying to get even more. We have not announced it yet. We have not closed on the funding yet. We are still working on a few things. It will help us to sustain development as well as expand the sales footprint. As we go to market there will be a need for cash.


What are the principally challenges you and for Nascentric?

The challenges are the same as for any EDA startup. Version 1.0 goes to the customer and the customer comes back and says I need this and this in order to put the product into my flow. The challenge is that we accept those and we have to prioritize those and deliver to the customer. The other side of the challenge would be traditionally compete against the big boys.


The large companies do not really sell technology. They just take a chunk of the budget. If a customer has a $40 million budget, they say give me $30 million and you can take as many copies of this, that and whatever you want. You can mix and remix all this stuff. By the way I have been guilty of this while I was at Cadence. It is particularly challenging for us to differentiate ourselves in that environment. We need to have a significant advantage on performance, accuracy and be able to deliver to the customer and say okay here’s what we can offer you. That’s really the challenge.


Then there is always the traditional challenge of a startup. Big companies will say I know that Cadence has been around 40 years and will probably be here for the next 20 years. Prove to me that you will be around. We have to find those perspective customers who have vision, the visionaries, and who have the wherewithal within their companies to go and root for us. It’s a tall order. It’s doable and I have done it before.


If I am a prospect for you product and what you are selling is performance and capacity, how long does it take me to evaluate, to benchmark your product?

That’s a very good question. We are actually being evaluated in a competitive benchmark right now. I can tell you from that experience the prospective customer will come and say these are all the things I need for my evaluation. Do you have that? Let’s say we have all those things. We come in and install our software and work with you. You find out that we have XYZ but we don’t have ABC. Often the specs, the requirements are not complete. Sometimes it is easy to do it overnight. Being a startup we can actually send out our VP of Engineering to the customer. He will take the source code along on his laptop and make the changes onsite. There is no way you can
expect Synopsys or Cadence to do that. That’s a different ballgame. They are in a different space.


We believe that we can turn things around very quickly, in a matter of weeks. At the end of the day, we have to show customers not only that we are better, faster, and more accurate and have more capacity but that also we are able to adapt to changing requirements faster. That’s where the winning recipe is at Nascentric.


Denise: That’s a good point. When you look at designs, every design is a little bit different. Every design type is a little bit different. If you are looking at memories there may be some memories that have a lot of feed forward or feedback in them and there may be memories that don’t. Depending upon the type of memories you are running will determine what the overall performance the customer might expect to see. One of the benefits that we bring is that because we are such a young simulator company is that we go into those environments where we are being evaluated against other simulators and once we can find out exactly the type of memory someone is designing, we can
modify or even create anew engine specifically optimized to suit that deign type. The customer can basically get a simulator that’s very well tuned to their specific design type.


Rahm: Also keep in mind that we don’t have the burden of legacy. A lot of our competitors have been in the market for a long time. This is really Marketing 101. They simply can not turn around quickly even if they wanted to due to the sheer weight of their baggage. We are fundamentally executing a game changing play her. Our technology will differentiate itself because once you get below 65 nm, it’s a game changing event. No longer will device delays be good enough. The interconnect dominates the parasitics and the interplay between the parasitics. All this stuff is going on is unbelievable. Even the traditional Fast-SPICE simulator companies have to go back to the drawing
board. It’s not just us that have to do this. Everyone is being pushed because once you go to 65 nm and 45 nm, the whole thing is different. That’s exactly why we believe we have an opportunity to shine in the market..


How do you see the market on a geographical basis? Do certain geographies represent a greater opportunity?

I would say that 40% is the US, 40% Japan/Asia. Keep in mind that we are closely tied to the fabrication of the chip. In Silicon Valley a lot of things happen. In North America out of the 40% probably 60% to 70% is here in the Bay area and northern California. The strategy for the company is to start out in North America where we want to be successful. We will slowly enter the Asian market as we move along later this year.


As you enter the Asian market, do you intend to go direct or to use distributors?

My experience has been that in this market you need partners, primarily distributors. In Japan for example, it just does not make sense to go direct. The costs are prohibitively high. You have to understand local culture and so we usually go with distributors in Japan. We will augment that with a person hired by the company based here in the US or in the Asian market. The same thing goes for Korea and Taiwan. The way we will go is to start from Japan and then go to Korea, Taiwan, China and India.


Do you have an estimate for the size of the Fast-SPICE market?

Denise: The way we look at the Fast-SPICE market is that there is a traditional market that has been for analysis and verification of large memories, SRAM, DRAM and flash as well as mixed signal. And then there is an expanded Fast-SPICE market. People need to be able to get a bit more accuracy than they have been able to traditionally get with Fast-SPICE tools for things like characterization if someone is generating a compiler they need to be able to characterize hundreds of different data points on that memory to create that compiler. They need much more accuracy then what they have been able to get. They need a simulator that has more capacity than what they have been able
to get with traditional SPICE cut methods. If we take a look at all that combined market, you are probably looking at $200 million to $250 million.


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  • Judge Clears Way for Broadcom Customers to Use Its 3G Cellular Chips without Threat of Infringement Claims by Qualcomm

  • ARM Builds Graphics Stack and Broadens Portfolio With Mali200 and Mali55 Processors

  • Runcom Launches the First Commercial Mobile WiMAX Wave-2 Baseband Integrated Circuit With MIMO Capability

  • AMD Ushers in Breathtaking Multimedia for Mobile Devices With Next-Generation AMD Imageon(TM) Media Processors

  • Freescale introduces industry's first multi-stage RFICs optimized for TD-SCDMA applications

  • SanDisk Introduces New 8GB JEDEC-Compatible iNAND Embedded Flash Drive for Latest Storage-Hungry Mobile Applications

  • Avago Technologies Announces Industry's Smallest Integrated RF Front-End Module for GSM/UMTS Band 1 Handsets

  • Freescale Achieves RF Power Breakthrough for GSM Wireless Markets

  • Micron Unveils New 1-Gigabit Mobile DRAM Chip and Will Bundle With NAND For Compact Multichip Packages

  • Micron Technology Aims to Perfect Camera Phone Pictures and Video with New Image Sensor Innovations

  • Broadcom Expands Its Mobile Technology Leadership with Industry's First 65nm Single-Chip EDGE System Solution

  • Marvell Expands its 3G Portfolio

  • Cellular3G Integrates CEVA-X DSP Core Into UMTS Baseband Chip for 3G Mobile Phone Applications

  • NFC Forum Issues White Paper, "the Keys to Truly Interoperable Communications"






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    -- Jack Horgan, EDACafe.com Contributing Editor.


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